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feat(ci): add sleep cache safe check for wifi power save

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sibeibei
2026-05-12 19:22:54 +08:00
committed by BOT
parent f5c26b4dd2
commit baba004e0d
6 changed files with 22 additions and 1 deletions
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examples/wifi/power_save/pytest_wifi_power_save.py
+14 -1
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@@ -1,4 +1,4 @@
# SPDX-FileCopyrightText: 2021-2025 Espressif Systems (Shanghai) CO LTD
# SPDX-FileCopyrightText: 2021-2026 Espressif Systems (Shanghai) CO LTD
# SPDX-License-Identifier: Apache-2.0
import logging
@@ -64,6 +64,19 @@ def test_wifi_power_save_pd_top(dut: Dut) -> None:
_run_test(dut)
@pytest.mark.wifi_ap
@pytest.mark.parametrize(
'config',
[
'pd_modem',
],
indirect=True,
)
@idf_parametrize('target', ['esp32c6', 'esp32c5', 'esp32c61'], indirect=['target'])
def test_wifi_power_save_pd_modem(dut: Dut) -> None:
_run_test(dut)
@pytest.mark.wifi_ap
@pytest.mark.xtal_26mhz
@pytest.mark.parametrize(
examples/wifi/power_save/sdkconfig.ci.c2_xtal26m
+1
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@@ -1,3 +1,4 @@
CONFIG_IDF_TARGET="esp32c2"
CONFIG_XTAL_FREQ_26=y
CONFIG_EXAMPLE_GET_AP_INFO_FROM_STDIN=y
CONFIG_ESP_SLEEP_CACHE_SAFE_ASSERTION=y
examples/wifi/power_save/sdkconfig.ci.esp32c2_rev2_xtal26m
+1
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@@ -2,3 +2,4 @@ CONFIG_IDF_TARGET="esp32c2"
CONFIG_XTAL_FREQ_26=y
CONFIG_EXAMPLE_GET_AP_INFO_FROM_STDIN=y
CONFIG_ESP32C2_REV_MIN_200=y
CONFIG_ESP_SLEEP_CACHE_SAFE_ASSERTION=y
examples/wifi/power_save/sdkconfig.ci.esp32c3_rev1
+1
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@@ -1,3 +1,4 @@
CONFIG_IDF_TARGET="esp32c3"
CONFIG_ESP32C3_REV_MIN_101=y
CONFIG_EXAMPLE_GET_AP_INFO_FROM_STDIN=y
CONFIG_ESP_SLEEP_CACHE_SAFE_ASSERTION=y
examples/wifi/power_save/sdkconfig.ci.pd_modem
+4
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@@ -0,0 +1,4 @@
CONFIG_EXAMPLE_GET_AP_INFO_FROM_STDIN=y
CONFIG_ESP_SLEEP_CACHE_SAFE_ASSERTION=y
CONFIG_ESP_PHY_MAC_BB_PD=y
CONFIG_ESP_WIFI_ENHANCED_LIGHT_SLEEP=y
examples/wifi/power_save/sdkconfig.ci.pd_top
+1
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@@ -2,3 +2,4 @@ CONFIG_EXAMPLE_GET_AP_INFO_FROM_STDIN=y
CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP=y
CONFIG_ESP_PHY_MAC_BB_PD=y
CONFIG_ESP_MODEM_CLOCK_ENABLE_CHECKING=y
CONFIG_ESP_SLEEP_CACHE_SAFE_ASSERTION=y