Mirrors/esp-idf
1
0
Fork 0
mirror of https://github.com/espressif/esp-idf.git synced 2026-10-01 18:50:34 +03:00
Code Issues Packages Projects Releases Wiki Activity

feat(uhci): Add support for uhci on esp32h21

Browse Source
This commit is contained in:
C.S.M
2026-03-24 19:00:10 +08:00
parent 118f64c32a
commit ba8b4cfd9e
25 changed files with 190 additions and 229 deletions
Download Patch File Download Diff File Expand all files Collapse all files
components/esp_driver_uart/src/uhci.c
+2 -3
View File
@@ -23,7 +23,6 @@
#include "driver/uhci.h"
#include "driver/uhci_types.h"
#include "hal/uhci_periph.h"
#include "soc/soc_caps.h"
#include "hal/uhci_hal.h"
#include "hal/uhci_ll.h"
#include "hal/dma_types.h"
@@ -43,7 +42,7 @@ static const char* TAG = "uhci";
typedef struct uhci_platform_t {
_lock_t mutex; // platform level mutex lock.
uhci_controller_handle_t controller[SOC_UHCI_NUM]; // array of UHCI instances.
uhci_controller_handle_t controller[UHCI_LL_NUM]; // array of UHCI instances.
} uhci_platform_t;
static uhci_platform_t s_uhci_platform = {}; // singleton platform
@@ -483,7 +482,7 @@ esp_err_t uhci_new_controller(const uhci_controller_config_t *config, uhci_contr
// Auto search a free controller
bool ctrl_found = false;
_lock_acquire(&s_uhci_platform.mutex);
for (int i = 0; i < SOC_UHCI_NUM; i++) {
for (int i = 0; i < UHCI_LL_NUM; i++) {
if (uhci_ctrl_occupied(i) == false) {
s_uhci_platform.controller[i] = uhci_ctrl;
ctrl_found = true;
components/esp_driver_uart/test_apps/uhci/README.md
+2 -2
View File
@@ -1,2 +1,2 @@
| Supported Targets | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S3 |
| ----------------- | -------- | -------- | -------- | -------- | -------- | -------- |
| Supported Targets | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-H21 | ESP32-P4 | ESP32-S3 |
| ----------------- | -------- | -------- | -------- | -------- | --------- | -------- | -------- |
components/esp_hal_uart/esp32c3/include/hal/uhci_ll.h
+1
View File
@@ -14,6 +14,7 @@
#include "soc/system_struct.h"
#include "hal/misc.h"
#define UHCI_LL_NUM (1UL)
#define UHCI_LL_GET_HW(num) (((num) == 0) ? (&UHCI0) : (NULL))
#define UHCI_LL_MAX_RECEIVE_PACKET_THRESHOLD (8192)
components/esp_hal_uart/esp32c5/include/hal/uhci_ll.h
+1
View File
@@ -14,6 +14,7 @@
#include "soc/pcr_struct.h"
#include "hal/misc.h"
#define UHCI_LL_NUM (1UL)
#define UHCI_LL_GET_HW(num) (((num) == 0) ? (&UHCI) : (NULL))
#define UHCI_LL_MAX_RECEIVE_PACKET_THRESHOLD (8192)
components/esp_hal_uart/esp32c6/include/hal/uhci_ll.h
+1
View File
@@ -14,6 +14,7 @@
#include "soc/pcr_struct.h"
#include "hal/misc.h"
#define UHCI_LL_NUM (1UL)
#define UHCI_LL_GET_HW(num) (((num) == 0) ? (&UHCI0) : (NULL))
#define UHCI_LL_MAX_RECEIVE_PACKET_THRESHOLD (8192)
components/esp_hal_uart/esp32h2/include/hal/uhci_ll.h
+1
View File
@@ -11,6 +11,7 @@
#include "soc/pcr_struct.h"
#include "hal/misc.h"
#define UHCI_LL_NUM (1UL)
#define UHCI_LL_GET_HW(num) (((num) == 0) ? (&UHCI0) : (NULL))
#define UHCI_LL_MAX_RECEIVE_PACKET_THRESHOLD (8192)
components/esp_hal_uart/esp32h21/include/hal/uhci_ll.h
+159
View File
@@ -0,0 +1,159 @@
/*
* SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdio.h>
#include "hal/uhci_types.h"
#include "soc/uhci_struct.h"
#include "soc/pcr_struct.h"
#include "hal/misc.h"
#define UHCI_LL_NUM (1UL)
#define UHCI_LL_GET_HW(num) (((num) == 0) ? (&UHCI0) : (NULL))
#define UHCI_LL_MAX_RECEIVE_PACKET_THRESHOLD (8192)
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
UHCI_RX_BREAK_CHR_EOF = 0x1,
UHCI_RX_IDLE_EOF = 0x2,
UHCI_RX_LEN_EOF = 0x4,
UHCI_RX_EOF_MAX = 0x7,
} uhci_rxeof_cfg_t;
/**
* @brief Enable the bus clock for UHCI module
*
* @param group_id Group ID
* @param enable true to enable, false to disable
*/
static inline void uhci_ll_enable_bus_clock(int group_id, bool enable)
{
(void)group_id;
PCR.uhci_conf.uhci_clk_en = enable;
}
/**
* @brief Reset the UHCI module
*
* @param group_id Group ID
*/
static inline void uhci_ll_reset_register(int group_id)
{
(void)group_id;
PCR.uhci_conf.uhci_rst_en = 1;
PCR.uhci_conf.uhci_rst_en = 0;
}
static inline void uhci_ll_init(uhci_dev_t *hw)
{
typeof(hw->conf0) conf0_reg;
conf0_reg.val = 0;
conf0_reg.clk_en = 1;
hw->conf0.val = conf0_reg.val;
hw->conf1.val = 0;
}
static inline void uhci_ll_attach_uart_port(uhci_dev_t *hw, int uart_num)
{
hw->conf0.uart0_ce = (uart_num == 0) ? 1 : 0;
hw->conf0.uart1_ce = (uart_num == 1) ? 1 : 0;
}
static inline void uhci_ll_set_seper_chr(uhci_dev_t *hw, uhci_seper_chr_t *seper_char)
{
if (seper_char->sub_chr_en) {
hw->conf0.seper_en = 1;
typeof(hw->esc_conf0) esc_conf0_reg;
esc_conf0_reg.val = hw->esc_conf0.val;
HAL_FORCE_MODIFY_U32_REG_FIELD(esc_conf0_reg, seper_char, seper_char->seper_chr);
HAL_FORCE_MODIFY_U32_REG_FIELD(esc_conf0_reg, seper_esc_char0, seper_char->sub_chr1);
HAL_FORCE_MODIFY_U32_REG_FIELD(esc_conf0_reg, seper_esc_char1, seper_char->sub_chr2);
hw->esc_conf0.val = esc_conf0_reg.val;
hw->escape_conf.tx_c0_esc_en = 1;
hw->escape_conf.rx_c0_esc_en = 1;
} else {
hw->conf0.seper_en = 0;
hw->escape_conf.val = 0;
}
}
static inline void uhci_ll_set_swflow_ctrl_sub_chr(uhci_dev_t *hw, uhci_swflow_ctrl_sub_chr_t *sub_ctr)
{
typeof(hw->escape_conf) escape_conf_reg;
escape_conf_reg.val = hw->escape_conf.val;
if (sub_ctr->flow_en == 1) {
typeof(hw->esc_conf2) esc_conf2_reg;
esc_conf2_reg.val = hw->esc_conf2.val;
typeof(hw->esc_conf3) esc_conf3_reg;
esc_conf3_reg.val = hw->esc_conf3.val;
HAL_FORCE_MODIFY_U32_REG_FIELD(esc_conf2_reg, esc_seq1, sub_ctr->xon_chr);
HAL_FORCE_MODIFY_U32_REG_FIELD(esc_conf2_reg, esc_seq1_char0, sub_ctr->xon_sub1);
HAL_FORCE_MODIFY_U32_REG_FIELD(esc_conf2_reg, esc_seq1_char1, sub_ctr->xon_sub2);
HAL_FORCE_MODIFY_U32_REG_FIELD(esc_conf3_reg, esc_seq2, sub_ctr->xoff_chr);
HAL_FORCE_MODIFY_U32_REG_FIELD(esc_conf3_reg, esc_seq2_char0, sub_ctr->xoff_sub1);
HAL_FORCE_MODIFY_U32_REG_FIELD(esc_conf3_reg, esc_seq2_char1, sub_ctr->xoff_sub2);
escape_conf_reg.tx_11_esc_en = 1;
escape_conf_reg.tx_13_esc_en = 1;
escape_conf_reg.rx_11_esc_en = 1;
escape_conf_reg.rx_13_esc_en = 1;
hw->esc_conf2.val = esc_conf2_reg.val;
hw->esc_conf3.val = esc_conf3_reg.val;
} else {
escape_conf_reg.tx_11_esc_en = 0;
escape_conf_reg.tx_13_esc_en = 0;
escape_conf_reg.rx_11_esc_en = 0;
escape_conf_reg.rx_13_esc_en = 0;
}
hw->escape_conf.val = escape_conf_reg.val;
}
static inline void uhci_ll_enable_intr(uhci_dev_t *hw, uint32_t intr_mask)
{
hw->int_ena.val |= intr_mask;
}
static inline void uhci_ll_disable_intr(uhci_dev_t *hw, uint32_t intr_mask)
{
hw->int_ena.val &= (~intr_mask);
}
static inline void uhci_ll_clear_intr(uhci_dev_t *hw, uint32_t intr_mask)
{
hw->int_clr.val = intr_mask;
}
static inline uint32_t uhci_ll_get_intr(uhci_dev_t *hw)
{
return hw->int_st.val;
}
static inline void uhci_ll_rx_set_eof_mode(uhci_dev_t *hw, uint32_t eof_mode)
{
if (eof_mode & UHCI_RX_BREAK_CHR_EOF) {
hw->conf0.uart_rx_brk_eof_en = 1;
}
if (eof_mode & UHCI_RX_IDLE_EOF) {
hw->conf0.uart_idle_eof_en = 1;
}
if (eof_mode & UHCI_RX_LEN_EOF) {
hw->conf0.len_eof_en = 1;
}
}
static inline void uhci_ll_rx_set_packet_threshold(uhci_dev_t *hw, uint16_t length)
{
hw->pkt_thres.pkt_thrs = length;
}
#ifdef __cplusplus
}
#endif
components/esp_hal_uart/esp32p4/include/hal/uhci_ll.h
+1
View File
@@ -14,6 +14,7 @@
#include "soc/hp_sys_clkrst_struct.h"
#include "hal/misc.h"
#define UHCI_LL_NUM (1UL)
#define UHCI_LL_GET_HW(num) (((num) == 0) ? (&UHCI0) : (NULL))
#define UHCI_LL_MAX_RECEIVE_PACKET_THRESHOLD (8192)
components/esp_hal_uart/esp32s3/include/hal/uhci_ll.h
+1
View File
@@ -14,6 +14,7 @@
#include "soc/system_struct.h"
#include "hal/misc.h"
#define UHCI_LL_NUM (1UL)
#define UHCI_LL_GET_HW(num) (((num) == 0) ? (&UHCI0) : (NULL))
#define UHCI_LL_MAX_RECEIVE_PACKET_THRESHOLD (8192)
components/soc/esp32c3/include/soc/Kconfig.soc_caps.in
-4
View File
@@ -803,10 +803,6 @@ config SOC_UART_WAKEUP_SUPPORT_ACTIVE_THRESH_MODE
bool
default y
config SOC_UHCI_NUM
int
default 1
config SOC_COEX_HW_PTI
bool
default y
components/soc/esp32c3/include/soc/soc_caps.h
-3
View File
@@ -359,9 +359,6 @@
#define SOC_UART_WAKEUP_SUPPORT_ACTIVE_THRESH_MODE (1)
/*--------------------------- UHCI CAPS -------------------------------------*/
#define SOC_UHCI_NUM (1UL)
/*-------------------------- COEXISTENCE HARDWARE PTI CAPS -------------------------------*/
#define SOC_COEX_HW_PTI (1)
components/soc/esp32c5/include/soc/Kconfig.soc_caps.in
-4
View File
@@ -1311,10 +1311,6 @@ config SOC_UART_WAKEUP_SUPPORT_CHAR_SEQ_MODE
bool
default y
config SOC_UHCI_NUM
int
default 1
config SOC_COEX_HW_PTI
bool
default y
components/soc/esp32c5/include/soc/soc_caps.h
-3
View File
@@ -534,9 +534,6 @@
#define SOC_UART_WAKEUP_SUPPORT_START_BIT_MODE (1)
#define SOC_UART_WAKEUP_SUPPORT_CHAR_SEQ_MODE (1)
/*--------------------------- UHCI CAPS -------------------------------------*/
#define SOC_UHCI_NUM (1UL)
/*-------------------------- COEXISTENCE HARDWARE PTI CAPS -------------------------------*/
#define SOC_COEX_HW_PTI (1)
components/soc/esp32c6/include/soc/Kconfig.soc_caps.in
-4
View File
@@ -1059,10 +1059,6 @@ config SOC_UART_WAKEUP_SUPPORT_CHAR_SEQ_MODE
bool
default y
config SOC_UHCI_NUM
int
default 1
config SOC_COEX_HW_PTI
bool
default y
components/soc/esp32c6/include/soc/soc_caps.h
-3
View File
@@ -439,9 +439,6 @@
#define SOC_UART_WAKEUP_SUPPORT_START_BIT_MODE (1)
#define SOC_UART_WAKEUP_SUPPORT_CHAR_SEQ_MODE (1)
/*--------------------------- UHCI CAPS -------------------------------------*/
#define SOC_UHCI_NUM (1UL)
/*-------------------------- COEXISTENCE HARDWARE PTI CAPS -------------------------------*/
#define SOC_COEX_HW_PTI (1)
components/soc/esp32h2/include/soc/Kconfig.soc_caps.in
-4
View File
@@ -1063,10 +1063,6 @@ config SOC_UART_WAKEUP_SUPPORT_CHAR_SEQ_MODE
bool
default y
config SOC_UHCI_NUM
int
default 1
config SOC_COEX_HW_PTI
bool
default y
components/soc/esp32h2/include/soc/soc_caps.h
-3
View File
@@ -463,9 +463,6 @@
#define SOC_UART_WAKEUP_SUPPORT_START_BIT_MODE (1)
#define SOC_UART_WAKEUP_SUPPORT_CHAR_SEQ_MODE (1)
/*--------------------------- UHCI CAPS -------------------------------------*/
#define SOC_UHCI_NUM (1UL)
/*-------------------------- COEXISTENCE HARDWARE PTI CAPS -------------------------------*/
#define SOC_COEX_HW_PTI (1)
components/soc/esp32h21/include/soc/Kconfig.soc_caps.in
+4
View File
@@ -15,6 +15,10 @@ config SOC_UART_SUPPORTED
bool
default y
config SOC_UHCI_SUPPORTED
bool
default y
config SOC_GDMA_SUPPORTED
bool
default y
components/soc/esp32h21/include/soc/soc_caps.h
+1
View File
@@ -27,6 +27,7 @@
#define SOC_ANA_CMPR_SUPPORTED 1
#define SOC_DEDICATED_GPIO_SUPPORTED 1
#define SOC_UART_SUPPORTED 1
#define SOC_UHCI_SUPPORTED 1
#define SOC_GDMA_SUPPORTED 1
#define SOC_AHB_GDMA_SUPPORTED 1
#define SOC_GPTIMER_SUPPORTED 1
components/soc/esp32h21/register/soc/uhci_struct.h
+14 -180
View File
@@ -1,5 +1,5 @@
/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0 OR MIT
*/
@@ -241,187 +241,31 @@ typedef union {
uint32_t val;
} uhci_quick_sent_reg_t;
/** Type of reg_q0_word0 register
/** Type of reg_qn_word0 register
* a
*/
typedef union {
struct {
/** send_q0_word0 : R/W; bitpos: [31:0]; default: 0;
/** send_word0 : R/W; bitpos: [31:0]; default: 0;
* a
*/
uint32_t send_q0_word0:32;
uint32_t send_word0:32;
};
uint32_t val;
} uhci_reg_q0_word0_reg_t;
} uhci_reg_qn_word0_reg_t;
/** Type of reg_q0_word1 register
/** Type of reg_qn_word1 register
* a
*/
typedef union {
struct {
/** send_q0_word1 : R/W; bitpos: [31:0]; default: 0;
/** send_word1 : R/W; bitpos: [31:0]; default: 0;
* a
*/
uint32_t send_q0_word1:32;
uint32_t send_word1:32;
};
uint32_t val;
} uhci_reg_q0_word1_reg_t;
/** Type of reg_q1_word0 register
* a
*/
typedef union {
struct {
/** send_q1_word0 : R/W; bitpos: [31:0]; default: 0;
* a
*/
uint32_t send_q1_word0:32;
};
uint32_t val;
} uhci_reg_q1_word0_reg_t;
/** Type of reg_q1_word1 register
* a
*/
typedef union {
struct {
/** send_q1_word1 : R/W; bitpos: [31:0]; default: 0;
* a
*/
uint32_t send_q1_word1:32;
};
uint32_t val;
} uhci_reg_q1_word1_reg_t;
/** Type of reg_q2_word0 register
* a
*/
typedef union {
struct {
/** send_q2_word0 : R/W; bitpos: [31:0]; default: 0;
* a
*/
uint32_t send_q2_word0:32;
};
uint32_t val;
} uhci_reg_q2_word0_reg_t;
/** Type of reg_q2_word1 register
* a
*/
typedef union {
struct {
/** send_q2_word1 : R/W; bitpos: [31:0]; default: 0;
* a
*/
uint32_t send_q2_word1:32;
};
uint32_t val;
} uhci_reg_q2_word1_reg_t;
/** Type of reg_q3_word0 register
* a
*/
typedef union {
struct {
/** send_q3_word0 : R/W; bitpos: [31:0]; default: 0;
* a
*/
uint32_t send_q3_word0:32;
};
uint32_t val;
} uhci_reg_q3_word0_reg_t;
/** Type of reg_q3_word1 register
* a
*/
typedef union {
struct {
/** send_q3_word1 : R/W; bitpos: [31:0]; default: 0;
* a
*/
uint32_t send_q3_word1:32;
};
uint32_t val;
} uhci_reg_q3_word1_reg_t;
/** Type of reg_q4_word0 register
* a
*/
typedef union {
struct {
/** send_q4_word0 : R/W; bitpos: [31:0]; default: 0;
* a
*/
uint32_t send_q4_word0:32;
};
uint32_t val;
} uhci_reg_q4_word0_reg_t;
/** Type of reg_q4_word1 register
* a
*/
typedef union {
struct {
/** send_q4_word1 : R/W; bitpos: [31:0]; default: 0;
* a
*/
uint32_t send_q4_word1:32;
};
uint32_t val;
} uhci_reg_q4_word1_reg_t;
/** Type of reg_q5_word0 register
* a
*/
typedef union {
struct {
/** send_q5_word0 : R/W; bitpos: [31:0]; default: 0;
* a
*/
uint32_t send_q5_word0:32;
};
uint32_t val;
} uhci_reg_q5_word0_reg_t;
/** Type of reg_q5_word1 register
* a
*/
typedef union {
struct {
/** send_q5_word1 : R/W; bitpos: [31:0]; default: 0;
* a
*/
uint32_t send_q5_word1:32;
};
uint32_t val;
} uhci_reg_q5_word1_reg_t;
/** Type of reg_q6_word0 register
* a
*/
typedef union {
struct {
/** send_q6_word0 : R/W; bitpos: [31:0]; default: 0;
* a
*/
uint32_t send_q6_word0:32;
};
uint32_t val;
} uhci_reg_q6_word0_reg_t;
/** Type of reg_q6_word1 register
* a
*/
typedef union {
struct {
/** send_q6_word1 : R/W; bitpos: [31:0]; default: 0;
* a
*/
uint32_t send_q6_word1:32;
};
uint32_t val;
} uhci_reg_q6_word1_reg_t;
} uhci_reg_qn_word1_reg_t;
/** Type of esc_conf0 register
* a
@@ -774,7 +618,7 @@ typedef union {
} uhci_date_reg_t;
typedef struct {
typedef struct uhci_dev_t {
volatile uhci_conf0_reg_t conf0;
volatile uhci_int_raw_reg_t int_raw;
volatile uhci_int_st_reg_t int_st;
@@ -788,20 +632,10 @@ typedef struct {
volatile uhci_ack_num_reg_t ack_num;
volatile uhci_rx_head_reg_t rx_head;
volatile uhci_quick_sent_reg_t quick_sent;
volatile uhci_reg_q0_word0_reg_t reg_q0_word0;
volatile uhci_reg_q0_word1_reg_t reg_q0_word1;
volatile uhci_reg_q1_word0_reg_t reg_q1_word0;
volatile uhci_reg_q1_word1_reg_t reg_q1_word1;
volatile uhci_reg_q2_word0_reg_t reg_q2_word0;
volatile uhci_reg_q2_word1_reg_t reg_q2_word1;
volatile uhci_reg_q3_word0_reg_t reg_q3_word0;
volatile uhci_reg_q3_word1_reg_t reg_q3_word1;
volatile uhci_reg_q4_word0_reg_t reg_q4_word0;
volatile uhci_reg_q4_word1_reg_t reg_q4_word1;
volatile uhci_reg_q5_word0_reg_t reg_q5_word0;
volatile uhci_reg_q5_word1_reg_t reg_q5_word1;
volatile uhci_reg_q6_word0_reg_t reg_q6_word0;
volatile uhci_reg_q6_word1_reg_t reg_q6_word1;
volatile struct {
uhci_reg_qn_word0_reg_t word0;
uhci_reg_qn_word1_reg_t word1;
} q_data[7];
volatile uhci_esc_conf0_reg_t esc_conf0;
volatile uhci_esc_conf1_reg_t esc_conf1;
volatile uhci_esc_conf2_reg_t esc_conf2;
components/soc/esp32p4/include/soc/Kconfig.soc_caps.in
-4
View File
@@ -1683,10 +1683,6 @@ config SOC_LP_I2S_SUPPORT_VAD
bool
default y
config SOC_UHCI_NUM
int
default 1
config SOC_COEX_HW_PTI
bool
default y
components/soc/esp32p4/include/soc/soc_caps.h
-3
View File
@@ -643,9 +643,6 @@
/*-------------------------- LP_VAD CAPS -------------------------------------*/
#define SOC_LP_I2S_SUPPORT_VAD (1)
/*--------------------------- UHCI CAPS -------------------------------------*/
#define SOC_UHCI_NUM (1UL)
/*-------------------------- COEXISTENCE HARDWARE PTI CAPS -------------------------------*/
#define SOC_COEX_HW_PTI (1)
components/soc/esp32s3/include/soc/Kconfig.soc_caps.in
-4
View File
@@ -783,10 +783,6 @@ config SOC_UART_WAKEUP_SUPPORT_ACTIVE_THRESH_MODE
bool
default y
config SOC_UHCI_NUM
int
default 1
config SOC_USB_OTG_PERIPH_NUM
int
default 1
components/soc/esp32s3/include/soc/soc_caps.h
-3
View File
@@ -328,9 +328,6 @@
#define SOC_UART_WAKEUP_SUPPORT_ACTIVE_THRESH_MODE (1)
/*--------------------------- UHCI CAPS -------------------------------------*/
#define SOC_UHCI_NUM (1UL)
/*-------------------------- USB CAPS ----------------------------------------*/
#define SOC_USB_OTG_PERIPH_NUM (1U)