From 1a814e95c3e6fee20f2d6e3db8181bbd7324ebc6 Mon Sep 17 00:00:00 2001 From: Konstantin Kondrashov Date: Thu, 3 Sep 2026 13:18:35 +0300 Subject: [PATCH] feat(efuse): Adds efuse ADC calibration support for ESP32S31 --- components/efuse/esp32s31/esp_efuse_table.c | 690 ++++++++- components/efuse/esp32s31/esp_efuse_table.csv | 118 +- .../efuse/esp32s31/include/esp_efuse_table.h | 81 +- .../soc/esp32s31/register/soc/efuse_reg.h | 1253 ++++++++++++----- .../soc/esp32s31/register/soc/efuse_struct.h | 882 ++++++++---- 5 files changed, 2324 insertions(+), 700 deletions(-) diff --git a/components/efuse/esp32s31/esp_efuse_table.c b/components/efuse/esp32s31/esp_efuse_table.c index 061d95242d6..2874c080b2b 100644 --- a/components/efuse/esp32s31/esp_efuse_table.c +++ b/components/efuse/esp32s31/esp_efuse_table.c @@ -9,7 +9,7 @@ #include #include "esp_efuse_table.h" -// md5_digest_table 1cdb8731d5e8193ceb48139f9db95994 +// md5_digest_table d75d0e39a18319b5287c3790c42a8d06 // This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY. // If you want to change some fields, you need to change esp_efuse_table.csv file // then run `efuse_common_table` or `efuse_custom_table` command it will generate this file. @@ -183,16 +183,16 @@ static const esp_efuse_desc_t WR_DIS_XTS_DPA_PSEUDO_LEVEL[] = { {EFUSE_BLK0, 14, 1}, // [] wr_dis of XTS_DPA_PSEUDO_LEVEL, }; -static const esp_efuse_desc_t WR_DIS_RMA_NONCE_ENA[] = { - {EFUSE_BLK0, 14, 1}, // [] wr_dis of RMA_NONCE_ENA, +static const esp_efuse_desc_t WR_DIS_SDC_NONCE_ENA[] = { + {EFUSE_BLK0, 14, 1}, // [] wr_dis of SDC_NONCE_ENA, }; -static const esp_efuse_desc_t WR_DIS_RMA_CHIP_INFO_SOURCE[] = { - {EFUSE_BLK0, 14, 1}, // [] wr_dis of RMA_CHIP_INFO_SOURCE, +static const esp_efuse_desc_t WR_DIS_SDC_CHIP_INFO_SOURCE[] = { + {EFUSE_BLK0, 14, 1}, // [] wr_dis of SDC_CHIP_INFO_SOURCE, }; -static const esp_efuse_desc_t WR_DIS_RMA_DISABLE_FAST_VEF[] = { - {EFUSE_BLK0, 14, 1}, // [] wr_dis of RMA_DISABLE_FAST_VEF, +static const esp_efuse_desc_t WR_DIS_SDC_DISABLE_FAST_VEF[] = { + {EFUSE_BLK0, 14, 1}, // [] wr_dis of SDC_DISABLE_FAST_VEF, }; static const esp_efuse_desc_t WR_DIS_ENA_XTS_SHADOW[] = { @@ -315,6 +315,42 @@ static const esp_efuse_desc_t WR_DIS_PKG_VERSION[] = { {EFUSE_BLK0, 20, 1}, // [] wr_dis of PKG_VERSION, }; +static const esp_efuse_desc_t WR_DIS_OCODE[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of OCODE, +}; + +static const esp_efuse_desc_t WR_DIS_ACTIVE_HP_DBIAS[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of ACTIVE_HP_DBIAS, +}; + +static const esp_efuse_desc_t WR_DIS_ACTIVE_LP_DBIAS[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of ACTIVE_LP_DBIAS, +}; + +static const esp_efuse_desc_t WR_DIS_LSLP_HP_DBG[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of LSLP_HP_DBG, +}; + +static const esp_efuse_desc_t WR_DIS_LSLP_HP_DBIAS[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of LSLP_HP_DBIAS, +}; + +static const esp_efuse_desc_t WR_DIS_DSLP_LP_DBG[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of DSLP_LP_DBG, +}; + +static const esp_efuse_desc_t WR_DIS_DSLP_LP_DBIAS[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of DSLP_LP_DBIAS, +}; + +static const esp_efuse_desc_t WR_DIS_LP_HP_DBIAS_VOL_GAP[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of LP_HP_DBIAS_VOL_GAP, +}; + +static const esp_efuse_desc_t WR_DIS_PVT_DBIAS[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of PVT_DBIAS, +}; + static const esp_efuse_desc_t WR_DIS_SYS_DATA_PART1[] = { {EFUSE_BLK0, 21, 1}, // [] wr_dis of BLOCK2, }; @@ -323,6 +359,18 @@ static const esp_efuse_desc_t WR_DIS_OPTIONAL_UNIQUE_ID[] = { {EFUSE_BLK0, 21, 1}, // [] wr_dis of OPTIONAL_UNIQUE_ID, }; +static const esp_efuse_desc_t WR_DIS_TEMP_CALIBRATION[] = { + {EFUSE_BLK0, 21, 1}, // [] wr_dis of TEMP_CALIBRATION, +}; + +static const esp_efuse_desc_t WR_DIS_SPI_LDO_1V8_DREF[] = { + {EFUSE_BLK0, 21, 1}, // [] wr_dis of SPI_LDO_1V8_DREF, +}; + +static const esp_efuse_desc_t WR_DIS_SPI_LDO_1V8_MUL[] = { + {EFUSE_BLK0, 21, 1}, // [] wr_dis of SPI_LDO_1V8_MUL, +}; + static const esp_efuse_desc_t WR_DIS_BLOCK_USR_DATA[] = { {EFUSE_BLK0, 22, 1}, // [WR_DIS.USER_DATA] wr_dis of BLOCK_USR_DATA, }; @@ -355,6 +403,54 @@ static const esp_efuse_desc_t WR_DIS_BLOCK_SYS_DATA2[] = { {EFUSE_BLK0, 28, 1}, // [WR_DIS.SYS_DATA_PART2] wr_dis of BLOCK_SYS_DATA2, }; +static const esp_efuse_desc_t WR_DIS_ADC1_DIFF_K[] = { + {EFUSE_BLK0, 28, 1}, // [] wr_dis of ADC1_DIFF_K, +}; + +static const esp_efuse_desc_t WR_DIS_ADC1_DIFF_B[] = { + {EFUSE_BLK0, 28, 1}, // [] wr_dis of ADC1_DIFF_B, +}; + +static const esp_efuse_desc_t WR_DIS_ADC1_P_K[] = { + {EFUSE_BLK0, 28, 1}, // [] wr_dis of ADC1_P_K, +}; + +static const esp_efuse_desc_t WR_DIS_ADC1_P_B[] = { + {EFUSE_BLK0, 28, 1}, // [] wr_dis of ADC1_P_B, +}; + +static const esp_efuse_desc_t WR_DIS_ADC1_N_K[] = { + {EFUSE_BLK0, 28, 1}, // [] wr_dis of ADC1_N_K, +}; + +static const esp_efuse_desc_t WR_DIS_ADC1_N_B[] = { + {EFUSE_BLK0, 28, 1}, // [] wr_dis of ADC1_N_B, +}; + +static const esp_efuse_desc_t WR_DIS_ADC2_DIFF_K[] = { + {EFUSE_BLK0, 28, 1}, // [] wr_dis of ADC2_DIFF_K, +}; + +static const esp_efuse_desc_t WR_DIS_ADC2_DIFF_B[] = { + {EFUSE_BLK0, 28, 1}, // [] wr_dis of ADC2_DIFF_B, +}; + +static const esp_efuse_desc_t WR_DIS_ADC2_P_K[] = { + {EFUSE_BLK0, 28, 1}, // [] wr_dis of ADC2_P_K, +}; + +static const esp_efuse_desc_t WR_DIS_ADC2_P_B[] = { + {EFUSE_BLK0, 28, 1}, // [] wr_dis of ADC2_P_B, +}; + +static const esp_efuse_desc_t WR_DIS_ADC2_N_K[] = { + {EFUSE_BLK0, 28, 1}, // [] wr_dis of ADC2_N_K, +}; + +static const esp_efuse_desc_t WR_DIS_ADC2_N_B[] = { + {EFUSE_BLK0, 28, 1}, // [] wr_dis of ADC2_N_B, +}; + static const esp_efuse_desc_t WR_DIS_USB_DEVICE_EXCHG_PINS[] = { {EFUSE_BLK0, 28, 1}, // [] wr_dis of USB_DEVICE_EXCHG_PINS, }; @@ -364,7 +460,7 @@ static const esp_efuse_desc_t WR_DIS_SOFT_DIS_JTAG[] = { }; static const esp_efuse_desc_t RD_DIS[] = { - {EFUSE_BLK0, 32, 7}, // [] Disable reading from BlOCK4-9, + {EFUSE_BLK0, 32, 7}, // [] Disable reading from BLOCK4-9, }; static const esp_efuse_desc_t RD_DIS_BLOCK_KEY0[] = { @@ -387,6 +483,58 @@ static const esp_efuse_desc_t RD_DIS_BLOCK_KEY4[] = { {EFUSE_BLK0, 36, 1}, // [RD_DIS.KEY4] rd_dis of BLOCK_KEY4, }; +static const esp_efuse_desc_t RD_DIS_ADC1_DIFF_K[] = { + {EFUSE_BLK0, 37, 1}, // [] rd_dis of ADC1_DIFF_K, +}; + +static const esp_efuse_desc_t RD_DIS_ADC1_DIFF_B[] = { + {EFUSE_BLK0, 37, 1}, // [] rd_dis of ADC1_DIFF_B, +}; + +static const esp_efuse_desc_t RD_DIS_ADC1_P_K[] = { + {EFUSE_BLK0, 37, 1}, // [] rd_dis of ADC1_P_K, +}; + +static const esp_efuse_desc_t RD_DIS_ADC1_P_B[] = { + {EFUSE_BLK0, 37, 1}, // [] rd_dis of ADC1_P_B, +}; + +static const esp_efuse_desc_t RD_DIS_ADC1_N_K[] = { + {EFUSE_BLK0, 37, 1}, // [] rd_dis of ADC1_N_K, +}; + +static const esp_efuse_desc_t RD_DIS_ADC1_N_B[] = { + {EFUSE_BLK0, 37, 1}, // [] rd_dis of ADC1_N_B, +}; + +static const esp_efuse_desc_t RD_DIS_ADC2_DIFF_K[] = { + {EFUSE_BLK0, 37, 1}, // [] rd_dis of ADC2_DIFF_K, +}; + +static const esp_efuse_desc_t RD_DIS_ADC2_DIFF_B[] = { + {EFUSE_BLK0, 37, 1}, // [] rd_dis of ADC2_DIFF_B, +}; + +static const esp_efuse_desc_t RD_DIS_ADC2_P_K[] = { + {EFUSE_BLK0, 37, 1}, // [] rd_dis of ADC2_P_K, +}; + +static const esp_efuse_desc_t RD_DIS_ADC2_P_B[] = { + {EFUSE_BLK0, 37, 1}, // [] rd_dis of ADC2_P_B, +}; + +static const esp_efuse_desc_t RD_DIS_ADC2_N_K[] = { + {EFUSE_BLK0, 37, 1}, // [] rd_dis of ADC2_N_K, +}; + +static const esp_efuse_desc_t RD_DIS_ADC2_N_B[] = { + {EFUSE_BLK0, 37, 1}, // [] rd_dis of ADC2_N_B, +}; + +static const esp_efuse_desc_t RD_DIS_USB_DEVICE_EXCHG_PINS[] = { + {EFUSE_BLK0, 37, 1}, // [] rd_dis of USB_DEVICE_EXCHG_PINS, +}; + static const esp_efuse_desc_t DIS_USB_JTAG[] = { {EFUSE_BLK0, 42, 1}, // [] Represents whether the function of usb switch to jtag is disabled or enabled. 1: disabled 0: enabled, }; @@ -428,11 +576,11 @@ static const esp_efuse_desc_t KM_RND_SWITCH_CYCLE[] = { }; static const esp_efuse_desc_t KM_DISABLE_DEPLOY_MODE[] = { - {EFUSE_BLK0, 66, 5}, // [] Represents whether the deploy mode of key manager is disable or not. 1: disabled 0: enabled. bit 0: ecsda; bit 1: flash & spi boot srambler; bit2: hmac & aes; bit3: ds & rma nonce; bit4: psram, + {EFUSE_BLK0, 66, 5}, // [] Represents whether the deploy mode of key manager is disable or not. 1: disabled 0: enabled. bit 0: ecsda; bit 1: flash & spi boot srambler; bit2: hmac & aes; bit3: ds & SDC nonce; bit4: psram, }; static const esp_efuse_desc_t KM_DEPLOY_ONLY_ONCE[] = { - {EFUSE_BLK0, 71, 5}, // [] Represents whether corresponding key can only be deployed once. 1 is true; 0 is false. 0: ecsda 1: flash & spi boot srambler 2: hmac & aes 3: ds & rma nonce 4: psram, + {EFUSE_BLK0, 71, 5}, // [] Represents whether corresponding key can only be deployed once. 1 is true; 0 is false. 0: ecsda 1: flash & spi boot srambler 2: hmac & aes 3: ds & SDC nonce 4: psram, }; static const esp_efuse_desc_t FORCE_USE_KEY_MANAGER_KEY[] = { @@ -444,11 +592,11 @@ static const esp_efuse_desc_t FORCE_DISABLE_SW_INIT_KEY[] = { }; static const esp_efuse_desc_t KM_XTS_KEY_LENGTH_256[] = { - {EFUSE_BLK0, 82, 1}, // [] Represents whether to configure flash encryption use xts-128 key. else use xts-256 key. 0: 128-bit key 1: 256-bit key, + {EFUSE_BLK0, 82, 1}, // [] Represents whether to configure flash encryption use xts-128 key. else use xts-256 key. 0: 128-bit key 1: 256-bit key, }; static const esp_efuse_desc_t WDT_DELAY_SEL[] = { - {EFUSE_BLK0, 83, 1}, // [] Represents the threshold level of the RTC watchdog STG0 timeout.0: Original threshold configuration value of STG0 *2 1: Original threshold configuration value of STG0 *4 2: Original threshold configuration value of STG0 *8 3: Original threshold configuration value of STG0 *16, + {EFUSE_BLK0, 83, 1}, // [] Represents the threshold level of the RTC watchdog STG0 timeout. 0: Original threshold configuration value of STG0 *2 1: Original threshold configuration value of STG0 *4 2: Original threshold configuration value of STG0 *8 3: Original threshold configuration value of STG0 *16, }; static const esp_efuse_desc_t DIS_SM_CRYPT[] = { @@ -456,7 +604,7 @@ static const esp_efuse_desc_t DIS_SM_CRYPT[] = { }; static const esp_efuse_desc_t SPI_BOOT_CRYPT_CNT[] = { - {EFUSE_BLK0, 85, 3}, // [] Enables flash encryption when 1 or 3 bits are set and disables otherwise {0: "Disable"; 1: "Enable"; 3: "Disable"; 7: "Enable"}, + {EFUSE_BLK0, 85, 3}, // [] Represents whether SPI boot encrypt/decrypt is disabled or enabled. Odd number of 1: enabled Even number of 1: disabled {0: "Disable"; 1: "Enable"; 3: "Disable"; 7: "Enable"}, }; static const esp_efuse_desc_t SECURE_BOOT_KEY_REVOKE0[] = { @@ -492,7 +640,7 @@ static const esp_efuse_desc_t KEY_PURPOSE_4[] = { }; static const esp_efuse_desc_t ECC_FORCE_CONST_TIME[] = { - {EFUSE_BLK0, 121, 1}, // [] Represents whether permanently turn on ECC const-time mode. 1: turn on 0: turn off, + {EFUSE_BLK0, 121, 1}, // [] Represents whether permanently turn on ECC const-time mode. 1: turn on 0: turn off, }; static const esp_efuse_desc_t ECDSA_DISABLE_SOFT_K[] = { @@ -504,7 +652,7 @@ static const esp_efuse_desc_t SEC_DPA_LEVEL[] = { }; static const esp_efuse_desc_t XTS_DPA_CLK_ENABLE[] = { - {EFUSE_BLK0, 125, 1}, // [] Represents whether to enable xts clock anti-dpa attack function.0: Disabled. 1: Enabled, + {EFUSE_BLK0, 125, 1}, // [] Represents whether to enable xts clock anti-dpa attack function. 0: Disabled. 1: Enabled, }; static const esp_efuse_desc_t XTS_DPA_PSEUDO_LEVEL[] = { @@ -596,39 +744,39 @@ static const esp_efuse_desc_t BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION[] = { }; static const esp_efuse_desc_t BOOTLOADER_ANTI_ROLLBACK_EN[] = { - {EFUSE_BLK0, 208, 1}, // [] Represents whether the ani-rollback check for the 2nd stage bootloader is enabled.1: Enabled0: Disabled, + {EFUSE_BLK0, 208, 1}, // [] Represents whether the ani-rollback check for the 2nd stage bootloader is enabled. 1: Enabled 0: Disabled, }; static const esp_efuse_desc_t BOOTLOADER_ANTI_ROLLBACK_UPDATE_IN_ROM[] = { - {EFUSE_BLK0, 209, 1}, // [] Represents whether the ani-rollback SECURE_VERSION will be updated from the ROM bootloader.1: Enable0: Disable, + {EFUSE_BLK0, 209, 1}, // [] Represents whether the ani-rollback SECURE_VERSION will be updated from the ROM bootloader. 1: Enable 0: Disable, }; static const esp_efuse_desc_t RECOVERY_BOOTLOADER_FLASH_SECTOR[] = { {EFUSE_BLK0, 210, 12}, // [] Represents the starting flash sector (flash sector size is 0x1000) of the recovery bootloader used by the ROM bootloader If the primary bootloader fails. 0 and 0xFFF - this feature is disabled, }; -static const esp_efuse_desc_t RMA_ENA[] = { - {EFUSE_BLK0, 222, 2}, // [] Represents whether rma function is supported in download mode. 2'b01/2'b10: enabled2'b00/2'b11: disabled, +static const esp_efuse_desc_t SDC_ENA[] = { + {EFUSE_BLK0, 222, 2}, // [] Represents whether SDC function is supported in download mode. 2'b01/2'b10: enabled 2'b00/2'b11: disabled, }; -static const esp_efuse_desc_t RMA_SESSION_COUNTER[] = { - {EFUSE_BLK0, 224, 3}, // [] Represents the number of times the RMA session has been entered, +static const esp_efuse_desc_t SDC_SESSION_COUNTER[] = { + {EFUSE_BLK0, 224, 3}, // [] Represents the number of times the SDC session has been entered, }; -static const esp_efuse_desc_t RMA_NONCE_ENA[] = { - {EFUSE_BLK0, 227, 2}, // [] Represents whether random number NONCE is used in RMA and whether the KM module is used to generate the NONCE. 2'bx0: No NONCE 2'b1x: Use KM generate NONCE., +static const esp_efuse_desc_t SDC_NONCE_ENA[] = { + {EFUSE_BLK0, 227, 2}, // [] Represents whether random number NONCE is used in SDC and whether the KM module is used to generate the NONCE . 2'bx0: No NONCE 2'b1x: Use KM generate NONCE, }; -static const esp_efuse_desc_t RMA_CHIP_INFO_SOURCE[] = { - {EFUSE_BLK0, 229, 1}, // [] Represents whether HUK_info is selected as the source for calculating CHIP_info in RMA.1: use HUK_info 0: use UNIQ_id, +static const esp_efuse_desc_t SDC_CHIP_INFO_SOURCE[] = { + {EFUSE_BLK0, 229, 1}, // [] Represents whether HUK_info is selected as the source for calculating CHIP_info in SDC. 1: use HUK_info 0: use UNIQ_id, }; -static const esp_efuse_desc_t RMA_DISABLE_FAST_VEF[] = { - {EFUSE_BLK0, 230, 1}, // [] Represents whether disable FAST_VEF in RMA session.1: disable0: enable, +static const esp_efuse_desc_t SDC_DISABLE_FAST_VEF[] = { + {EFUSE_BLK0, 230, 1}, // [] Represents whether disable FAST_VEF in SDC session. 1: disable 0: enable, }; static const esp_efuse_desc_t PVT_0_GLITCH_EN[] = { - {EFUSE_BLK0, 231, 1}, // [] Represents whether to enable PVT power glitch monitor function.1:Enable. 0:Disable, + {EFUSE_BLK0, 231, 1}, // [] Represents whether to enable PVT power glitch monitor function. 1:Enable. 0:Disable, }; static const esp_efuse_desc_t PVT_0_GLITCH_MODE[] = { @@ -636,7 +784,7 @@ static const esp_efuse_desc_t PVT_0_GLITCH_MODE[] = { }; static const esp_efuse_desc_t PVT_1_GLITCH_EN[] = { - {EFUSE_BLK0, 234, 1}, // [] Represents whether to enable PVT power glitch monitor function.1:Enable. 0:Disable, + {EFUSE_BLK0, 234, 1}, // [] Represents whether to enable PVT power glitch monitor function. 1:Enable. 0:Disable, }; static const esp_efuse_desc_t PVT_1_GLITCH_MODE[] = { @@ -644,7 +792,7 @@ static const esp_efuse_desc_t PVT_1_GLITCH_MODE[] = { }; static const esp_efuse_desc_t PMU_FLASH_POWER_SEL[] = { - {EFUSE_BLK0, 237, 1}, // [] FLASH power select. 1'b1: use 3.3V1'b0: use 1.8V, + {EFUSE_BLK0, 237, 1}, // [] FLASH power select. 1'b1: use 3.3V 1'b0: use 1.8V, }; static const esp_efuse_desc_t PMU_FLASH_POWER_SEL_EN[] = { @@ -656,15 +804,15 @@ static const esp_efuse_desc_t POWER_GLITCH_EN[] = { }; static const esp_efuse_desc_t ENA_XTS_SHADOW[] = { - {EFUSE_BLK0, 243, 1}, // [] Represents whether to enable XTS-AES shadow core countermeasure against fault injection attacks. 0: Disabled 1: Enabled, + {EFUSE_BLK0, 243, 1}, // [] Represents whether to enable XTS-AES shadow core countermeasure against fault injection attacks. 0: Disabled 1: Enabled, }; static const esp_efuse_desc_t ENA_SPI_BOOT_CRYPT_SCRAMBLER[] = { - {EFUSE_BLK0, 244, 1}, // [] Represents whether to enable ciphertext scrambler for external memory . 0: Disabled 1: Enabled, + {EFUSE_BLK0, 244, 1}, // [] Represents whether to enable ciphertext scrambler for external memory . 0: Disabled 1: Enabled, }; static const esp_efuse_desc_t RE_ENABLE_JTAG_SOURCE[] = { - {EFUSE_BLK0, 245, 1}, // [] Represents which Crypto peripheral is selected for re-enabling JTAG. 0: RMA 1: HMAC, + {EFUSE_BLK0, 245, 1}, // [] Represents which Crypto peripheral is selected for re-enabling JTAG. 0: SDC 1: HMAC, }; static const esp_efuse_desc_t MAC[] = { @@ -677,8 +825,8 @@ static const esp_efuse_desc_t MAC[] = { }; static const esp_efuse_desc_t MAC_EXT[] = { - {EFUSE_BLK1, 56, 8}, // [] Stores the extended bits of MAC address, - {EFUSE_BLK1, 48, 8}, // [] Stores the extended bits of MAC address, + {EFUSE_BLK1, 56, 8}, // [] Represents the extended bits of MAC address, + {EFUSE_BLK1, 48, 8}, // [] Represents the extended bits of MAC address, }; static const esp_efuse_desc_t WAFER_VERSION_MINOR[] = { @@ -721,10 +869,58 @@ static const esp_efuse_desc_t PKG_VERSION[] = { {EFUSE_BLK1, 134, 2}, // [] Package version, }; +static const esp_efuse_desc_t OCODE[] = { + {EFUSE_BLK1, 136, 8}, // [] OCode calibration, +}; + +static const esp_efuse_desc_t ACTIVE_HP_DBIAS[] = { + {EFUSE_BLK1, 144, 4}, // [] Active HP DBIAS of fixed voltage, +}; + +static const esp_efuse_desc_t ACTIVE_LP_DBIAS[] = { + {EFUSE_BLK1, 148, 4}, // [] Active LP DBIAS of fixed voltage, +}; + +static const esp_efuse_desc_t LSLP_HP_DBG[] = { + {EFUSE_BLK1, 152, 2}, // [] LSLP HP DBG of fixed voltage, +}; + +static const esp_efuse_desc_t LSLP_HP_DBIAS[] = { + {EFUSE_BLK1, 154, 4}, // [] LSLP HP DBIAS of fixed voltage, +}; + +static const esp_efuse_desc_t DSLP_LP_DBG[] = { + {EFUSE_BLK1, 158, 4}, // [] DSLP LP DBG of fixed voltage, +}; + +static const esp_efuse_desc_t DSLP_LP_DBIAS[] = { + {EFUSE_BLK1, 162, 5}, // [] DSLP LP DBIAS of fixed voltage, +}; + +static const esp_efuse_desc_t LP_HP_DBIAS_VOL_GAP[] = { + {EFUSE_BLK1, 167, 5}, // [] DBIAS gap between LP and HP, +}; + +static const esp_efuse_desc_t PVT_DBIAS[] = { + {EFUSE_BLK1, 172, 4}, // [] PVT DBIAS, +}; + static const esp_efuse_desc_t OPTIONAL_UNIQUE_ID[] = { {EFUSE_BLK2, 0, 128}, // [] Optional unique 128-bit ID, }; +static const esp_efuse_desc_t TEMP_CALIBRATION[] = { + {EFUSE_BLK2, 128, 10}, // [] Temperature calibration, +}; + +static const esp_efuse_desc_t SPI_LDO_1V8_DREF[] = { + {EFUSE_BLK2, 138, 4}, // [] SPI LDO 1.8 V DREF, +}; + +static const esp_efuse_desc_t SPI_LDO_1V8_MUL[] = { + {EFUSE_BLK2, 142, 3}, // [] SPI LDO 1.8 V multiplier, +}; + static const esp_efuse_desc_t USER_DATA[] = { {EFUSE_BLK3, 0, 256}, // [BLOCK_USR_DATA] User data, }; @@ -753,12 +949,56 @@ static const esp_efuse_desc_t KEY4[] = { {EFUSE_BLK8, 0, 256}, // [BLOCK_KEY4] Key4 or user data, }; -static const esp_efuse_desc_t SYS_DATA_PART2[] = { - {EFUSE_BLK9, 0, 32}, // [BLOCK_SYS_DATA2] System data part 2 (reserved), +static const esp_efuse_desc_t ADC1_DIFF_K[] = { + {EFUSE_BLK9, 0, 11}, // [] Fitted slope (K) of ADC1 in differential mode, +}; + +static const esp_efuse_desc_t ADC1_DIFF_B[] = { + {EFUSE_BLK9, 11, 10}, // [] Intercept (B) of ADC1 in differential mode, +}; + +static const esp_efuse_desc_t ADC1_P_K[] = { + {EFUSE_BLK9, 21, 11}, // [] Fitted slope (K) of ADC1 in P mode, +}; + +static const esp_efuse_desc_t ADC1_P_B[] = { + {EFUSE_BLK9, 32, 10}, // [] Intercept (B) of ADC1 in P mode, +}; + +static const esp_efuse_desc_t ADC1_N_K[] = { + {EFUSE_BLK9, 42, 11}, // [] Fitted slope (K) of ADC1 in N mode, +}; + +static const esp_efuse_desc_t ADC1_N_B[] = { + {EFUSE_BLK9, 53, 10}, // [] Intercept (B) of ADC1 in N mode, +}; + +static const esp_efuse_desc_t ADC2_DIFF_K[] = { + {EFUSE_BLK9, 63, 11}, // [] Fitted slope (K) of ADC2 in differential mode, +}; + +static const esp_efuse_desc_t ADC2_DIFF_B[] = { + {EFUSE_BLK9, 74, 10}, // [] Intercept (B) of ADC2 in differential mode, +}; + +static const esp_efuse_desc_t ADC2_P_K[] = { + {EFUSE_BLK9, 84, 11}, // [] Fitted slope (K) of ADC2 in P mode, +}; + +static const esp_efuse_desc_t ADC2_P_B[] = { + {EFUSE_BLK9, 95, 10}, // [] Intercept (B) of ADC2 in P mode, +}; + +static const esp_efuse_desc_t ADC2_N_K[] = { + {EFUSE_BLK9, 105, 11}, // [] Fitted slope (K) of ADC2 in N mode, +}; + +static const esp_efuse_desc_t ADC2_N_B[] = { + {EFUSE_BLK9, 116, 10}, // [] Intercept (B) of ADC2 in N mode, }; static const esp_efuse_desc_t USB_DEVICE_EXCHG_PINS[] = { - {EFUSE_BLK9, 192, 1}, // [] Represents whether enable usb device exchange pins of D+ and D- or not. 1: enabled 0: disabled, + {EFUSE_BLK9, 192, 1}, // [] Represents whether enable usb device exchange pins of D+ and D- or not. 1: enabled 0: disabled, }; @@ -975,18 +1215,18 @@ const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_XTS_DPA_PSEUDO_LEVEL[] = { NULL }; -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RMA_NONCE_ENA[] = { - &WR_DIS_RMA_NONCE_ENA[0], // [] wr_dis of RMA_NONCE_ENA +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SDC_NONCE_ENA[] = { + &WR_DIS_SDC_NONCE_ENA[0], // [] wr_dis of SDC_NONCE_ENA NULL }; -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RMA_CHIP_INFO_SOURCE[] = { - &WR_DIS_RMA_CHIP_INFO_SOURCE[0], // [] wr_dis of RMA_CHIP_INFO_SOURCE +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SDC_CHIP_INFO_SOURCE[] = { + &WR_DIS_SDC_CHIP_INFO_SOURCE[0], // [] wr_dis of SDC_CHIP_INFO_SOURCE NULL }; -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RMA_DISABLE_FAST_VEF[] = { - &WR_DIS_RMA_DISABLE_FAST_VEF[0], // [] wr_dis of RMA_DISABLE_FAST_VEF +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SDC_DISABLE_FAST_VEF[] = { + &WR_DIS_SDC_DISABLE_FAST_VEF[0], // [] wr_dis of SDC_DISABLE_FAST_VEF NULL }; @@ -1140,6 +1380,51 @@ const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PKG_VERSION[] = { NULL }; +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_OCODE[] = { + &WR_DIS_OCODE[0], // [] wr_dis of OCODE + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ACTIVE_HP_DBIAS[] = { + &WR_DIS_ACTIVE_HP_DBIAS[0], // [] wr_dis of ACTIVE_HP_DBIAS + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ACTIVE_LP_DBIAS[] = { + &WR_DIS_ACTIVE_LP_DBIAS[0], // [] wr_dis of ACTIVE_LP_DBIAS + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LSLP_HP_DBG[] = { + &WR_DIS_LSLP_HP_DBG[0], // [] wr_dis of LSLP_HP_DBG + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LSLP_HP_DBIAS[] = { + &WR_DIS_LSLP_HP_DBIAS[0], // [] wr_dis of LSLP_HP_DBIAS + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DSLP_LP_DBG[] = { + &WR_DIS_DSLP_LP_DBG[0], // [] wr_dis of DSLP_LP_DBG + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DSLP_LP_DBIAS[] = { + &WR_DIS_DSLP_LP_DBIAS[0], // [] wr_dis of DSLP_LP_DBIAS + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LP_HP_DBIAS_VOL_GAP[] = { + &WR_DIS_LP_HP_DBIAS_VOL_GAP[0], // [] wr_dis of LP_HP_DBIAS_VOL_GAP + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PVT_DBIAS[] = { + &WR_DIS_PVT_DBIAS[0], // [] wr_dis of PVT_DBIAS + NULL +}; + const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SYS_DATA_PART1[] = { &WR_DIS_SYS_DATA_PART1[0], // [] wr_dis of BLOCK2 NULL @@ -1150,6 +1435,21 @@ const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_OPTIONAL_UNIQUE_ID[] = { NULL }; +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_TEMP_CALIBRATION[] = { + &WR_DIS_TEMP_CALIBRATION[0], // [] wr_dis of TEMP_CALIBRATION + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_LDO_1V8_DREF[] = { + &WR_DIS_SPI_LDO_1V8_DREF[0], // [] wr_dis of SPI_LDO_1V8_DREF + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_LDO_1V8_MUL[] = { + &WR_DIS_SPI_LDO_1V8_MUL[0], // [] wr_dis of SPI_LDO_1V8_MUL + NULL +}; + const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_USR_DATA[] = { &WR_DIS_BLOCK_USR_DATA[0], // [WR_DIS.USER_DATA] wr_dis of BLOCK_USR_DATA NULL @@ -1190,6 +1490,66 @@ const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_SYS_DATA2[] = { NULL }; +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_DIFF_K[] = { + &WR_DIS_ADC1_DIFF_K[0], // [] wr_dis of ADC1_DIFF_K + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_DIFF_B[] = { + &WR_DIS_ADC1_DIFF_B[0], // [] wr_dis of ADC1_DIFF_B + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_P_K[] = { + &WR_DIS_ADC1_P_K[0], // [] wr_dis of ADC1_P_K + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_P_B[] = { + &WR_DIS_ADC1_P_B[0], // [] wr_dis of ADC1_P_B + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_N_K[] = { + &WR_DIS_ADC1_N_K[0], // [] wr_dis of ADC1_N_K + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_N_B[] = { + &WR_DIS_ADC1_N_B[0], // [] wr_dis of ADC1_N_B + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_DIFF_K[] = { + &WR_DIS_ADC2_DIFF_K[0], // [] wr_dis of ADC2_DIFF_K + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_DIFF_B[] = { + &WR_DIS_ADC2_DIFF_B[0], // [] wr_dis of ADC2_DIFF_B + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_P_K[] = { + &WR_DIS_ADC2_P_K[0], // [] wr_dis of ADC2_P_K + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_P_B[] = { + &WR_DIS_ADC2_P_B[0], // [] wr_dis of ADC2_P_B + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_N_K[] = { + &WR_DIS_ADC2_N_K[0], // [] wr_dis of ADC2_N_K + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_N_B[] = { + &WR_DIS_ADC2_N_B[0], // [] wr_dis of ADC2_N_B + NULL +}; + const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USB_DEVICE_EXCHG_PINS[] = { &WR_DIS_USB_DEVICE_EXCHG_PINS[0], // [] wr_dis of USB_DEVICE_EXCHG_PINS NULL @@ -1201,7 +1561,7 @@ const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SOFT_DIS_JTAG[] = { }; const esp_efuse_desc_t* ESP_EFUSE_RD_DIS[] = { - &RD_DIS[0], // [] Disable reading from BlOCK4-9 + &RD_DIS[0], // [] Disable reading from BLOCK4-9 NULL }; @@ -1230,6 +1590,71 @@ const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY4[] = { NULL }; +const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC1_DIFF_K[] = { + &RD_DIS_ADC1_DIFF_K[0], // [] rd_dis of ADC1_DIFF_K + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC1_DIFF_B[] = { + &RD_DIS_ADC1_DIFF_B[0], // [] rd_dis of ADC1_DIFF_B + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC1_P_K[] = { + &RD_DIS_ADC1_P_K[0], // [] rd_dis of ADC1_P_K + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC1_P_B[] = { + &RD_DIS_ADC1_P_B[0], // [] rd_dis of ADC1_P_B + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC1_N_K[] = { + &RD_DIS_ADC1_N_K[0], // [] rd_dis of ADC1_N_K + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC1_N_B[] = { + &RD_DIS_ADC1_N_B[0], // [] rd_dis of ADC1_N_B + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_DIFF_K[] = { + &RD_DIS_ADC2_DIFF_K[0], // [] rd_dis of ADC2_DIFF_K + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_DIFF_B[] = { + &RD_DIS_ADC2_DIFF_B[0], // [] rd_dis of ADC2_DIFF_B + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_P_K[] = { + &RD_DIS_ADC2_P_K[0], // [] rd_dis of ADC2_P_K + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_P_B[] = { + &RD_DIS_ADC2_P_B[0], // [] rd_dis of ADC2_P_B + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_N_K[] = { + &RD_DIS_ADC2_N_K[0], // [] rd_dis of ADC2_N_K + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_N_B[] = { + &RD_DIS_ADC2_N_B[0], // [] rd_dis of ADC2_N_B + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_USB_DEVICE_EXCHG_PINS[] = { + &RD_DIS_USB_DEVICE_EXCHG_PINS[0], // [] rd_dis of USB_DEVICE_EXCHG_PINS + NULL +}; + const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_JTAG[] = { &DIS_USB_JTAG[0], // [] Represents whether the function of usb switch to jtag is disabled or enabled. 1: disabled 0: enabled NULL @@ -1281,12 +1706,12 @@ const esp_efuse_desc_t* ESP_EFUSE_KM_RND_SWITCH_CYCLE[] = { }; const esp_efuse_desc_t* ESP_EFUSE_KM_DISABLE_DEPLOY_MODE[] = { - &KM_DISABLE_DEPLOY_MODE[0], // [] Represents whether the deploy mode of key manager is disable or not. 1: disabled 0: enabled. bit 0: ecsda; bit 1: flash & spi boot srambler; bit2: hmac & aes; bit3: ds & rma nonce; bit4: psram + &KM_DISABLE_DEPLOY_MODE[0], // [] Represents whether the deploy mode of key manager is disable or not. 1: disabled 0: enabled. bit 0: ecsda; bit 1: flash & spi boot srambler; bit2: hmac & aes; bit3: ds & SDC nonce; bit4: psram NULL }; const esp_efuse_desc_t* ESP_EFUSE_KM_DEPLOY_ONLY_ONCE[] = { - &KM_DEPLOY_ONLY_ONCE[0], // [] Represents whether corresponding key can only be deployed once. 1 is true; 0 is false. 0: ecsda 1: flash & spi boot srambler 2: hmac & aes 3: ds & rma nonce 4: psram + &KM_DEPLOY_ONLY_ONCE[0], // [] Represents whether corresponding key can only be deployed once. 1 is true; 0 is false. 0: ecsda 1: flash & spi boot srambler 2: hmac & aes 3: ds & SDC nonce 4: psram NULL }; @@ -1301,12 +1726,12 @@ const esp_efuse_desc_t* ESP_EFUSE_FORCE_DISABLE_SW_INIT_KEY[] = { }; const esp_efuse_desc_t* ESP_EFUSE_KM_XTS_KEY_LENGTH_256[] = { - &KM_XTS_KEY_LENGTH_256[0], // [] Represents whether to configure flash encryption use xts-128 key. else use xts-256 key. 0: 128-bit key 1: 256-bit key + &KM_XTS_KEY_LENGTH_256[0], // [] Represents whether to configure flash encryption use xts-128 key. else use xts-256 key. 0: 128-bit key 1: 256-bit key NULL }; const esp_efuse_desc_t* ESP_EFUSE_WDT_DELAY_SEL[] = { - &WDT_DELAY_SEL[0], // [] Represents the threshold level of the RTC watchdog STG0 timeout.0: Original threshold configuration value of STG0 *2 1: Original threshold configuration value of STG0 *4 2: Original threshold configuration value of STG0 *8 3: Original threshold configuration value of STG0 *16 + &WDT_DELAY_SEL[0], // [] Represents the threshold level of the RTC watchdog STG0 timeout. 0: Original threshold configuration value of STG0 *2 1: Original threshold configuration value of STG0 *4 2: Original threshold configuration value of STG0 *8 3: Original threshold configuration value of STG0 *16 NULL }; @@ -1316,7 +1741,7 @@ const esp_efuse_desc_t* ESP_EFUSE_DIS_SM_CRYPT[] = { }; const esp_efuse_desc_t* ESP_EFUSE_SPI_BOOT_CRYPT_CNT[] = { - &SPI_BOOT_CRYPT_CNT[0], // [] Enables flash encryption when 1 or 3 bits are set and disables otherwise {0: "Disable"; 1: "Enable"; 3: "Disable"; 7: "Enable"} + &SPI_BOOT_CRYPT_CNT[0], // [] Represents whether SPI boot encrypt/decrypt is disabled or enabled. Odd number of 1: enabled Even number of 1: disabled {0: "Disable"; 1: "Enable"; 3: "Disable"; 7: "Enable"} NULL }; @@ -1361,7 +1786,7 @@ const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_4[] = { }; const esp_efuse_desc_t* ESP_EFUSE_ECC_FORCE_CONST_TIME[] = { - &ECC_FORCE_CONST_TIME[0], // [] Represents whether permanently turn on ECC const-time mode. 1: turn on 0: turn off + &ECC_FORCE_CONST_TIME[0], // [] Represents whether permanently turn on ECC const-time mode. 1: turn on 0: turn off NULL }; @@ -1376,7 +1801,7 @@ const esp_efuse_desc_t* ESP_EFUSE_SEC_DPA_LEVEL[] = { }; const esp_efuse_desc_t* ESP_EFUSE_XTS_DPA_CLK_ENABLE[] = { - &XTS_DPA_CLK_ENABLE[0], // [] Represents whether to enable xts clock anti-dpa attack function.0: Disabled. 1: Enabled + &XTS_DPA_CLK_ENABLE[0], // [] Represents whether to enable xts clock anti-dpa attack function. 0: Disabled. 1: Enabled NULL }; @@ -1491,12 +1916,12 @@ const esp_efuse_desc_t* ESP_EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION[] = { }; const esp_efuse_desc_t* ESP_EFUSE_BOOTLOADER_ANTI_ROLLBACK_EN[] = { - &BOOTLOADER_ANTI_ROLLBACK_EN[0], // [] Represents whether the ani-rollback check for the 2nd stage bootloader is enabled.1: Enabled0: Disabled + &BOOTLOADER_ANTI_ROLLBACK_EN[0], // [] Represents whether the ani-rollback check for the 2nd stage bootloader is enabled. 1: Enabled 0: Disabled NULL }; const esp_efuse_desc_t* ESP_EFUSE_BOOTLOADER_ANTI_ROLLBACK_UPDATE_IN_ROM[] = { - &BOOTLOADER_ANTI_ROLLBACK_UPDATE_IN_ROM[0], // [] Represents whether the ani-rollback SECURE_VERSION will be updated from the ROM bootloader.1: Enable0: Disable + &BOOTLOADER_ANTI_ROLLBACK_UPDATE_IN_ROM[0], // [] Represents whether the ani-rollback SECURE_VERSION will be updated from the ROM bootloader. 1: Enable 0: Disable NULL }; @@ -1505,33 +1930,33 @@ const esp_efuse_desc_t* ESP_EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR[] = { NULL }; -const esp_efuse_desc_t* ESP_EFUSE_RMA_ENA[] = { - &RMA_ENA[0], // [] Represents whether rma function is supported in download mode. 2'b01/2'b10: enabled2'b00/2'b11: disabled +const esp_efuse_desc_t* ESP_EFUSE_SDC_ENA[] = { + &SDC_ENA[0], // [] Represents whether SDC function is supported in download mode. 2'b01/2'b10: enabled 2'b00/2'b11: disabled NULL }; -const esp_efuse_desc_t* ESP_EFUSE_RMA_SESSION_COUNTER[] = { - &RMA_SESSION_COUNTER[0], // [] Represents the number of times the RMA session has been entered +const esp_efuse_desc_t* ESP_EFUSE_SDC_SESSION_COUNTER[] = { + &SDC_SESSION_COUNTER[0], // [] Represents the number of times the SDC session has been entered NULL }; -const esp_efuse_desc_t* ESP_EFUSE_RMA_NONCE_ENA[] = { - &RMA_NONCE_ENA[0], // [] Represents whether random number NONCE is used in RMA and whether the KM module is used to generate the NONCE. 2'bx0: No NONCE 2'b1x: Use KM generate NONCE. +const esp_efuse_desc_t* ESP_EFUSE_SDC_NONCE_ENA[] = { + &SDC_NONCE_ENA[0], // [] Represents whether random number NONCE is used in SDC and whether the KM module is used to generate the NONCE . 2'bx0: No NONCE 2'b1x: Use KM generate NONCE NULL }; -const esp_efuse_desc_t* ESP_EFUSE_RMA_CHIP_INFO_SOURCE[] = { - &RMA_CHIP_INFO_SOURCE[0], // [] Represents whether HUK_info is selected as the source for calculating CHIP_info in RMA.1: use HUK_info 0: use UNIQ_id +const esp_efuse_desc_t* ESP_EFUSE_SDC_CHIP_INFO_SOURCE[] = { + &SDC_CHIP_INFO_SOURCE[0], // [] Represents whether HUK_info is selected as the source for calculating CHIP_info in SDC. 1: use HUK_info 0: use UNIQ_id NULL }; -const esp_efuse_desc_t* ESP_EFUSE_RMA_DISABLE_FAST_VEF[] = { - &RMA_DISABLE_FAST_VEF[0], // [] Represents whether disable FAST_VEF in RMA session.1: disable0: enable +const esp_efuse_desc_t* ESP_EFUSE_SDC_DISABLE_FAST_VEF[] = { + &SDC_DISABLE_FAST_VEF[0], // [] Represents whether disable FAST_VEF in SDC session. 1: disable 0: enable NULL }; const esp_efuse_desc_t* ESP_EFUSE_PVT_0_GLITCH_EN[] = { - &PVT_0_GLITCH_EN[0], // [] Represents whether to enable PVT power glitch monitor function.1:Enable. 0:Disable + &PVT_0_GLITCH_EN[0], // [] Represents whether to enable PVT power glitch monitor function. 1:Enable. 0:Disable NULL }; @@ -1541,7 +1966,7 @@ const esp_efuse_desc_t* ESP_EFUSE_PVT_0_GLITCH_MODE[] = { }; const esp_efuse_desc_t* ESP_EFUSE_PVT_1_GLITCH_EN[] = { - &PVT_1_GLITCH_EN[0], // [] Represents whether to enable PVT power glitch monitor function.1:Enable. 0:Disable + &PVT_1_GLITCH_EN[0], // [] Represents whether to enable PVT power glitch monitor function. 1:Enable. 0:Disable NULL }; @@ -1551,7 +1976,7 @@ const esp_efuse_desc_t* ESP_EFUSE_PVT_1_GLITCH_MODE[] = { }; const esp_efuse_desc_t* ESP_EFUSE_PMU_FLASH_POWER_SEL[] = { - &PMU_FLASH_POWER_SEL[0], // [] FLASH power select. 1'b1: use 3.3V1'b0: use 1.8V + &PMU_FLASH_POWER_SEL[0], // [] FLASH power select. 1'b1: use 3.3V 1'b0: use 1.8V NULL }; @@ -1566,17 +1991,17 @@ const esp_efuse_desc_t* ESP_EFUSE_POWER_GLITCH_EN[] = { }; const esp_efuse_desc_t* ESP_EFUSE_ENA_XTS_SHADOW[] = { - &ENA_XTS_SHADOW[0], // [] Represents whether to enable XTS-AES shadow core countermeasure against fault injection attacks. 0: Disabled 1: Enabled + &ENA_XTS_SHADOW[0], // [] Represents whether to enable XTS-AES shadow core countermeasure against fault injection attacks. 0: Disabled 1: Enabled NULL }; const esp_efuse_desc_t* ESP_EFUSE_ENA_SPI_BOOT_CRYPT_SCRAMBLER[] = { - &ENA_SPI_BOOT_CRYPT_SCRAMBLER[0], // [] Represents whether to enable ciphertext scrambler for external memory . 0: Disabled 1: Enabled + &ENA_SPI_BOOT_CRYPT_SCRAMBLER[0], // [] Represents whether to enable ciphertext scrambler for external memory . 0: Disabled 1: Enabled NULL }; const esp_efuse_desc_t* ESP_EFUSE_RE_ENABLE_JTAG_SOURCE[] = { - &RE_ENABLE_JTAG_SOURCE[0], // [] Represents which Crypto peripheral is selected for re-enabling JTAG. 0: RMA 1: HMAC + &RE_ENABLE_JTAG_SOURCE[0], // [] Represents which Crypto peripheral is selected for re-enabling JTAG. 0: SDC 1: HMAC NULL }; @@ -1591,8 +2016,8 @@ const esp_efuse_desc_t* ESP_EFUSE_MAC[] = { }; const esp_efuse_desc_t* ESP_EFUSE_MAC_EXT[] = { - &MAC_EXT[0], // [] Stores the extended bits of MAC address - &MAC_EXT[1], // [] Stores the extended bits of MAC address + &MAC_EXT[0], // [] Represents the extended bits of MAC address + &MAC_EXT[1], // [] Represents the extended bits of MAC address NULL }; @@ -1646,11 +2071,71 @@ const esp_efuse_desc_t* ESP_EFUSE_PKG_VERSION[] = { NULL }; +const esp_efuse_desc_t* ESP_EFUSE_OCODE[] = { + &OCODE[0], // [] OCode calibration + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_ACTIVE_HP_DBIAS[] = { + &ACTIVE_HP_DBIAS[0], // [] Active HP DBIAS of fixed voltage + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_ACTIVE_LP_DBIAS[] = { + &ACTIVE_LP_DBIAS[0], // [] Active LP DBIAS of fixed voltage + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_LSLP_HP_DBG[] = { + &LSLP_HP_DBG[0], // [] LSLP HP DBG of fixed voltage + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_LSLP_HP_DBIAS[] = { + &LSLP_HP_DBIAS[0], // [] LSLP HP DBIAS of fixed voltage + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_DSLP_LP_DBG[] = { + &DSLP_LP_DBG[0], // [] DSLP LP DBG of fixed voltage + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_DSLP_LP_DBIAS[] = { + &DSLP_LP_DBIAS[0], // [] DSLP LP DBIAS of fixed voltage + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_LP_HP_DBIAS_VOL_GAP[] = { + &LP_HP_DBIAS_VOL_GAP[0], // [] DBIAS gap between LP and HP + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_PVT_DBIAS[] = { + &PVT_DBIAS[0], // [] PVT DBIAS + NULL +}; + const esp_efuse_desc_t* ESP_EFUSE_OPTIONAL_UNIQUE_ID[] = { &OPTIONAL_UNIQUE_ID[0], // [] Optional unique 128-bit ID NULL }; +const esp_efuse_desc_t* ESP_EFUSE_TEMP_CALIBRATION[] = { + &TEMP_CALIBRATION[0], // [] Temperature calibration + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_SPI_LDO_1V8_DREF[] = { + &SPI_LDO_1V8_DREF[0], // [] SPI LDO 1.8 V DREF + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_SPI_LDO_1V8_MUL[] = { + &SPI_LDO_1V8_MUL[0], // [] SPI LDO 1.8 V multiplier + NULL +}; + const esp_efuse_desc_t* ESP_EFUSE_USER_DATA[] = { &USER_DATA[0], // [BLOCK_USR_DATA] User data NULL @@ -1686,12 +2171,67 @@ const esp_efuse_desc_t* ESP_EFUSE_KEY4[] = { NULL }; -const esp_efuse_desc_t* ESP_EFUSE_SYS_DATA_PART2[] = { - &SYS_DATA_PART2[0], // [BLOCK_SYS_DATA2] System data part 2 (reserved) +const esp_efuse_desc_t* ESP_EFUSE_ADC1_DIFF_K[] = { + &ADC1_DIFF_K[0], // [] Fitted slope (K) of ADC1 in differential mode + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_ADC1_DIFF_B[] = { + &ADC1_DIFF_B[0], // [] Intercept (B) of ADC1 in differential mode + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_ADC1_P_K[] = { + &ADC1_P_K[0], // [] Fitted slope (K) of ADC1 in P mode + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_ADC1_P_B[] = { + &ADC1_P_B[0], // [] Intercept (B) of ADC1 in P mode + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_ADC1_N_K[] = { + &ADC1_N_K[0], // [] Fitted slope (K) of ADC1 in N mode + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_ADC1_N_B[] = { + &ADC1_N_B[0], // [] Intercept (B) of ADC1 in N mode + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_ADC2_DIFF_K[] = { + &ADC2_DIFF_K[0], // [] Fitted slope (K) of ADC2 in differential mode + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_ADC2_DIFF_B[] = { + &ADC2_DIFF_B[0], // [] Intercept (B) of ADC2 in differential mode + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_ADC2_P_K[] = { + &ADC2_P_K[0], // [] Fitted slope (K) of ADC2 in P mode + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_ADC2_P_B[] = { + &ADC2_P_B[0], // [] Intercept (B) of ADC2 in P mode + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_ADC2_N_K[] = { + &ADC2_N_K[0], // [] Fitted slope (K) of ADC2 in N mode + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_ADC2_N_B[] = { + &ADC2_N_B[0], // [] Intercept (B) of ADC2 in N mode NULL }; const esp_efuse_desc_t* ESP_EFUSE_USB_DEVICE_EXCHG_PINS[] = { - &USB_DEVICE_EXCHG_PINS[0], // [] Represents whether enable usb device exchange pins of D+ and D- or not. 1: enabled 0: disabled + &USB_DEVICE_EXCHG_PINS[0], // [] Represents whether enable usb device exchange pins of D+ and D- or not. 1: enabled 0: disabled NULL }; diff --git a/components/efuse/esp32s31/esp_efuse_table.csv b/components/efuse/esp32s31/esp_efuse_table.csv index e762eeaa89d..a1ca4f802b2 100644 --- a/components/efuse/esp32s31/esp_efuse_table.csv +++ b/components/efuse/esp32s31/esp_efuse_table.csv @@ -9,7 +9,7 @@ # this will generate new source files, next rebuild all the sources. # !!!!!!!!!!! # -# This file was generated by regtools.py based on the efuses.yaml file with the version: 2ec5c3c5bd07b0b4e073b91d75592d8f +# This file was generated by regtools.py based on the efuses.yaml file with the version: 110663d2f1ee8db2a1864a227b304e57 WR_DIS, EFUSE_BLK0, 0, 32, [] Disable programming of individual eFuses WR_DIS.RD_DIS, EFUSE_BLK0, 0, 1, [] wr_dis of RD_DIS @@ -53,9 +53,9 @@ WR_DIS.ECDSA_DISABLE_SOFT_K, EFUSE_BLK0, 14, 1, [] wr_dis WR_DIS.SEC_DPA_LEVEL, EFUSE_BLK0, 14, 1, [] wr_dis of SEC_DPA_LEVEL WR_DIS.XTS_DPA_CLK_ENABLE, EFUSE_BLK0, 14, 1, [] wr_dis of XTS_DPA_CLK_ENABLE WR_DIS.XTS_DPA_PSEUDO_LEVEL, EFUSE_BLK0, 14, 1, [] wr_dis of XTS_DPA_PSEUDO_LEVEL -WR_DIS.RMA_NONCE_ENA, EFUSE_BLK0, 14, 1, [] wr_dis of RMA_NONCE_ENA -WR_DIS.RMA_CHIP_INFO_SOURCE, EFUSE_BLK0, 14, 1, [] wr_dis of RMA_CHIP_INFO_SOURCE -WR_DIS.RMA_DISABLE_FAST_VEF, EFUSE_BLK0, 14, 1, [] wr_dis of RMA_DISABLE_FAST_VEF +WR_DIS.SDC_NONCE_ENA, EFUSE_BLK0, 14, 1, [] wr_dis of SDC_NONCE_ENA +WR_DIS.SDC_CHIP_INFO_SOURCE, EFUSE_BLK0, 14, 1, [] wr_dis of SDC_CHIP_INFO_SOURCE +WR_DIS.SDC_DISABLE_FAST_VEF, EFUSE_BLK0, 14, 1, [] wr_dis of SDC_DISABLE_FAST_VEF WR_DIS.ENA_XTS_SHADOW, EFUSE_BLK0, 14, 1, [] wr_dis of ENA_XTS_SHADOW WR_DIS.ENA_SPI_BOOT_CRYPT_SCRAMBLER, EFUSE_BLK0, 14, 1, [] wr_dis of ENA_SPI_BOOT_CRYPT_SCRAMBLER WR_DIS.RE_ENABLE_JTAG_SOURCE, EFUSE_BLK0, 14, 1, [] wr_dis of RE_ENABLE_JTAG_SOURCE @@ -86,8 +86,20 @@ WR_DIS.PSRAM_CAP, EFUSE_BLK0, 20, 1, [] wr_dis WR_DIS.TEMP, EFUSE_BLK0, 20, 1, [] wr_dis of TEMP WR_DIS.PSRAM_VENDOR, EFUSE_BLK0, 20, 1, [] wr_dis of PSRAM_VENDOR WR_DIS.PKG_VERSION, EFUSE_BLK0, 20, 1, [] wr_dis of PKG_VERSION +WR_DIS.OCODE, EFUSE_BLK0, 20, 1, [] wr_dis of OCODE +WR_DIS.ACTIVE_HP_DBIAS, EFUSE_BLK0, 20, 1, [] wr_dis of ACTIVE_HP_DBIAS +WR_DIS.ACTIVE_LP_DBIAS, EFUSE_BLK0, 20, 1, [] wr_dis of ACTIVE_LP_DBIAS +WR_DIS.LSLP_HP_DBG, EFUSE_BLK0, 20, 1, [] wr_dis of LSLP_HP_DBG +WR_DIS.LSLP_HP_DBIAS, EFUSE_BLK0, 20, 1, [] wr_dis of LSLP_HP_DBIAS +WR_DIS.DSLP_LP_DBG, EFUSE_BLK0, 20, 1, [] wr_dis of DSLP_LP_DBG +WR_DIS.DSLP_LP_DBIAS, EFUSE_BLK0, 20, 1, [] wr_dis of DSLP_LP_DBIAS +WR_DIS.LP_HP_DBIAS_VOL_GAP, EFUSE_BLK0, 20, 1, [] wr_dis of LP_HP_DBIAS_VOL_GAP +WR_DIS.PVT_DBIAS, EFUSE_BLK0, 20, 1, [] wr_dis of PVT_DBIAS WR_DIS.SYS_DATA_PART1, EFUSE_BLK0, 21, 1, [] wr_dis of BLOCK2 WR_DIS.OPTIONAL_UNIQUE_ID, EFUSE_BLK0, 21, 1, [] wr_dis of OPTIONAL_UNIQUE_ID +WR_DIS.TEMP_CALIBRATION, EFUSE_BLK0, 21, 1, [] wr_dis of TEMP_CALIBRATION +WR_DIS.SPI_LDO_1V8_DREF, EFUSE_BLK0, 21, 1, [] wr_dis of SPI_LDO_1V8_DREF +WR_DIS.SPI_LDO_1V8_MUL, EFUSE_BLK0, 21, 1, [] wr_dis of SPI_LDO_1V8_MUL WR_DIS.BLOCK_USR_DATA, EFUSE_BLK0, 22, 1, [WR_DIS.USER_DATA] wr_dis of BLOCK_USR_DATA WR_DIS.CUSTOM_MAC, EFUSE_BLK0, 22, 1, [WR_DIS.MAC_CUSTOM WR_DIS.USER_DATA_MAC_CUSTOM] wr_dis of CUSTOM_MAC WR_DIS.BLOCK_KEY0, EFUSE_BLK0, 23, 1, [WR_DIS.KEY0] wr_dis of BLOCK_KEY0 @@ -96,14 +108,39 @@ WR_DIS.BLOCK_KEY2, EFUSE_BLK0, 25, 1, [WR_DIS.K WR_DIS.BLOCK_KEY3, EFUSE_BLK0, 26, 1, [WR_DIS.KEY3] wr_dis of BLOCK_KEY3 WR_DIS.BLOCK_KEY4, EFUSE_BLK0, 27, 1, [WR_DIS.KEY4] wr_dis of BLOCK_KEY4 WR_DIS.BLOCK_SYS_DATA2, EFUSE_BLK0, 28, 1, [WR_DIS.SYS_DATA_PART2] wr_dis of BLOCK_SYS_DATA2 +WR_DIS.ADC1_DIFF_K, EFUSE_BLK0, 28, 1, [] wr_dis of ADC1_DIFF_K +WR_DIS.ADC1_DIFF_B, EFUSE_BLK0, 28, 1, [] wr_dis of ADC1_DIFF_B +WR_DIS.ADC1_P_K, EFUSE_BLK0, 28, 1, [] wr_dis of ADC1_P_K +WR_DIS.ADC1_P_B, EFUSE_BLK0, 28, 1, [] wr_dis of ADC1_P_B +WR_DIS.ADC1_N_K, EFUSE_BLK0, 28, 1, [] wr_dis of ADC1_N_K +WR_DIS.ADC1_N_B, EFUSE_BLK0, 28, 1, [] wr_dis of ADC1_N_B +WR_DIS.ADC2_DIFF_K, EFUSE_BLK0, 28, 1, [] wr_dis of ADC2_DIFF_K +WR_DIS.ADC2_DIFF_B, EFUSE_BLK0, 28, 1, [] wr_dis of ADC2_DIFF_B +WR_DIS.ADC2_P_K, EFUSE_BLK0, 28, 1, [] wr_dis of ADC2_P_K +WR_DIS.ADC2_P_B, EFUSE_BLK0, 28, 1, [] wr_dis of ADC2_P_B +WR_DIS.ADC2_N_K, EFUSE_BLK0, 28, 1, [] wr_dis of ADC2_N_K +WR_DIS.ADC2_N_B, EFUSE_BLK0, 28, 1, [] wr_dis of ADC2_N_B WR_DIS.USB_DEVICE_EXCHG_PINS, EFUSE_BLK0, 28, 1, [] wr_dis of USB_DEVICE_EXCHG_PINS WR_DIS.SOFT_DIS_JTAG, EFUSE_BLK0, 31, 1, [] wr_dis of SOFT_DIS_JTAG -RD_DIS, EFUSE_BLK0, 32, 7, [] Disable reading from BlOCK4-9 +RD_DIS, EFUSE_BLK0, 32, 7, [] Disable reading from BLOCK4-9 RD_DIS.BLOCK_KEY0, EFUSE_BLK0, 32, 1, [RD_DIS.KEY0] rd_dis of BLOCK_KEY0 RD_DIS.BLOCK_KEY1, EFUSE_BLK0, 33, 1, [RD_DIS.KEY1] rd_dis of BLOCK_KEY1 RD_DIS.BLOCK_KEY2, EFUSE_BLK0, 34, 1, [RD_DIS.KEY2] rd_dis of BLOCK_KEY2 RD_DIS.BLOCK_KEY3, EFUSE_BLK0, 35, 1, [RD_DIS.KEY3] rd_dis of BLOCK_KEY3 RD_DIS.BLOCK_KEY4, EFUSE_BLK0, 36, 1, [RD_DIS.KEY4] rd_dis of BLOCK_KEY4 +RD_DIS.ADC1_DIFF_K, EFUSE_BLK0, 37, 1, [] rd_dis of ADC1_DIFF_K +RD_DIS.ADC1_DIFF_B, EFUSE_BLK0, 37, 1, [] rd_dis of ADC1_DIFF_B +RD_DIS.ADC1_P_K, EFUSE_BLK0, 37, 1, [] rd_dis of ADC1_P_K +RD_DIS.ADC1_P_B, EFUSE_BLK0, 37, 1, [] rd_dis of ADC1_P_B +RD_DIS.ADC1_N_K, EFUSE_BLK0, 37, 1, [] rd_dis of ADC1_N_K +RD_DIS.ADC1_N_B, EFUSE_BLK0, 37, 1, [] rd_dis of ADC1_N_B +RD_DIS.ADC2_DIFF_K, EFUSE_BLK0, 37, 1, [] rd_dis of ADC2_DIFF_K +RD_DIS.ADC2_DIFF_B, EFUSE_BLK0, 37, 1, [] rd_dis of ADC2_DIFF_B +RD_DIS.ADC2_P_K, EFUSE_BLK0, 37, 1, [] rd_dis of ADC2_P_K +RD_DIS.ADC2_P_B, EFUSE_BLK0, 37, 1, [] rd_dis of ADC2_P_B +RD_DIS.ADC2_N_K, EFUSE_BLK0, 37, 1, [] rd_dis of ADC2_N_K +RD_DIS.ADC2_N_B, EFUSE_BLK0, 37, 1, [] rd_dis of ADC2_N_B +RD_DIS.USB_DEVICE_EXCHG_PINS, EFUSE_BLK0, 37, 1, [] rd_dis of USB_DEVICE_EXCHG_PINS DIS_USB_JTAG, EFUSE_BLK0, 42, 1, [] Represents whether the function of usb switch to jtag is disabled or enabled. 1: disabled 0: enabled DIS_FORCE_DOWNLOAD, EFUSE_BLK0, 44, 1, [] Represents whether the function that forces chip into download mode is disabled or enabled. 1: disabled 0: enabled SPI_DOWNLOAD_MSPI_DIS, EFUSE_BLK0, 45, 1, [] Represents whether SPI0 controller during boot_mode_download is disabled or enabled. 1: disabled 0: enabled @@ -114,14 +151,14 @@ DIS_PAD_JTAG, EFUSE_BLK0, 51, 1, [] Repres DIS_DOWNLOAD_MANUAL_ENCRYPT, EFUSE_BLK0, 52, 1, [] Represents whether flash encrypt function is disabled or enabled(except in SPI boot mode). 1: disabled 0: enabled HUK_GEN_STATE, EFUSE_BLK0, 55, 5, [] Represents the control of validation of HUK generate mode. Odd of 1 is invalid; even of 1 is valid KM_RND_SWITCH_CYCLE, EFUSE_BLK0, 64, 1, [] Represents the control of key manager random number switch cycle. 0: control by register. 1: 8 km clk cycles. 2: 16 km cycles. 3: 32 km cycles -KM_DISABLE_DEPLOY_MODE, EFUSE_BLK0, 66, 5, [] Represents whether the deploy mode of key manager is disable or not. 1: disabled 0: enabled. bit 0: ecsda; bit 1: flash & spi boot srambler; bit2: hmac & aes; bit3: ds & rma nonce; bit4: psram -KM_DEPLOY_ONLY_ONCE, EFUSE_BLK0, 71, 5, [] Represents whether corresponding key can only be deployed once. 1 is true; 0 is false. 0: ecsda 1: flash & spi boot srambler 2: hmac & aes 3: ds & rma nonce 4: psram +KM_DISABLE_DEPLOY_MODE, EFUSE_BLK0, 66, 5, [] Represents whether the deploy mode of key manager is disable or not. 1: disabled 0: enabled. bit 0: ecsda; bit 1: flash & spi boot srambler; bit2: hmac & aes; bit3: ds & SDC nonce; bit4: psram +KM_DEPLOY_ONLY_ONCE, EFUSE_BLK0, 71, 5, [] Represents whether corresponding key can only be deployed once. 1 is true; 0 is false. 0: ecsda 1: flash & spi boot srambler 2: hmac & aes 3: ds & SDC nonce 4: psram FORCE_USE_KEY_MANAGER_KEY, EFUSE_BLK0, 76, 5, [] Represents whether corresponding key must come from key manager. 1 is true; 0 is false. 0: ecsda 1: flash 2: reserved 3: reserved 4: psram FORCE_DISABLE_SW_INIT_KEY, EFUSE_BLK0, 81, 1, [] Represents whether to disable software written init key; and force use efuse_init_key -KM_XTS_KEY_LENGTH_256, EFUSE_BLK0, 82, 1, [] Represents whether to configure flash encryption use xts-128 key. else use xts-256 key. 0: 128-bit key 1: 256-bit key -WDT_DELAY_SEL, EFUSE_BLK0, 83, 1, [] Represents the threshold level of the RTC watchdog STG0 timeout.0: Original threshold configuration value of STG0 *2 1: Original threshold configuration value of STG0 *4 2: Original threshold configuration value of STG0 *8 3: Original threshold configuration value of STG0 *16 +KM_XTS_KEY_LENGTH_256, EFUSE_BLK0, 82, 1, [] Represents whether to configure flash encryption use xts-128 key. else use xts-256 key. 0: 128-bit key 1: 256-bit key +WDT_DELAY_SEL, EFUSE_BLK0, 83, 1, [] Represents the threshold level of the RTC watchdog STG0 timeout. 0: Original threshold configuration value of STG0 *2 1: Original threshold configuration value of STG0 *4 2: Original threshold configuration value of STG0 *8 3: Original threshold configuration value of STG0 *16 DIS_SM_CRYPT, EFUSE_BLK0, 84, 1, [] Represents whether to disable all the SM crypto functions; including SM2; SM3. 1: disabled 0: enabled -SPI_BOOT_CRYPT_CNT, EFUSE_BLK0, 85, 3, [] Enables flash encryption when 1 or 3 bits are set and disables otherwise {0: "Disable"; 1: "Enable"; 3: "Disable"; 7: "Enable"} +SPI_BOOT_CRYPT_CNT, EFUSE_BLK0, 85, 3, [] Represents whether SPI boot encrypt/decrypt is disabled or enabled. Odd number of 1: enabled Even number of 1: disabled {0: "Disable"; 1: "Enable"; 3: "Disable"; 7: "Enable"} SECURE_BOOT_KEY_REVOKE0, EFUSE_BLK0, 88, 1, [] Revoke 1st secure boot key SECURE_BOOT_KEY_REVOKE1, EFUSE_BLK0, 89, 1, [] Revoke 2nd secure boot key SECURE_BOOT_KEY_REVOKE2, EFUSE_BLK0, 90, 1, [] Revoke 3rd secure boot key @@ -130,10 +167,10 @@ KEY_PURPOSE_1, EFUSE_BLK0, 101, 5, [KEY1_PUR KEY_PURPOSE_2, EFUSE_BLK0, 106, 5, [KEY2_PURPOSE] Represents the purpose of Key2 KEY_PURPOSE_3, EFUSE_BLK0, 111, 5, [KEY3_PURPOSE] Represents the purpose of Key3 KEY_PURPOSE_4, EFUSE_BLK0, 116, 5, [KEY4_PURPOSE] Represents the purpose of Key4 -ECC_FORCE_CONST_TIME, EFUSE_BLK0, 121, 1, [] Represents whether permanently turn on ECC const-time mode. 1: turn on 0: turn off +ECC_FORCE_CONST_TIME, EFUSE_BLK0, 121, 1, [] Represents whether permanently turn on ECC const-time mode. 1: turn on 0: turn off ECDSA_DISABLE_SOFT_K, EFUSE_BLK0, 122, 1, [] Represents whether permanently turn off ECDSA software set KEY. 1: turn off 0: turn on SEC_DPA_LEVEL, EFUSE_BLK0, 123, 2, [] Represents the spa secure level by configuring the clock random divide mode -XTS_DPA_CLK_ENABLE, EFUSE_BLK0, 125, 1, [] Represents whether to enable xts clock anti-dpa attack function.0: Disabled. 1: Enabled +XTS_DPA_CLK_ENABLE, EFUSE_BLK0, 125, 1, [] Represents whether to enable xts clock anti-dpa attack function. 0: Disabled. 1: Enabled XTS_DPA_PSEUDO_LEVEL, EFUSE_BLK0, 128, 2, [] Represents the control of the xts pseudo-round anti-dpa attack function. 0: controlled by register. 1-3: the higher the value is; the more pseudo-rounds are inserted to the xts-aes calculation SECURE_BOOT_EN, EFUSE_BLK0, 130, 1, [] Represents whether secure boot is enabled or disabled. 1: enabled 0: disabled SECURE_BOOT_AGGRESSIVE_REVOKE, EFUSE_BLK0, 131, 1, [] Represents whether revoking aggressive secure boot is enabled or disabled. 1: enabled. 0: disabled @@ -156,32 +193,32 @@ DIS_WDT, EFUSE_BLK0, 195, 1, [] Set th DIS_SWD, EFUSE_BLK0, 196, 1, [] Set this bit to disable super-watchdog SECURE_BOOT_SHA384_EN, EFUSE_BLK0, 203, 1, [] Represents whether secure boot using SHA-384 is enabled. 0: Disable 1: Enable BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION, EFUSE_BLK0, 204, 4, [] Represents the anti-rollback secure version of the 2nd stage bootloader used by the ROM bootloader -BOOTLOADER_ANTI_ROLLBACK_EN, EFUSE_BLK0, 208, 1, [] Represents whether the ani-rollback check for the 2nd stage bootloader is enabled.1: Enabled0: Disabled -BOOTLOADER_ANTI_ROLLBACK_UPDATE_IN_ROM, EFUSE_BLK0, 209, 1, [] Represents whether the ani-rollback SECURE_VERSION will be updated from the ROM bootloader.1: Enable0: Disable +BOOTLOADER_ANTI_ROLLBACK_EN, EFUSE_BLK0, 208, 1, [] Represents whether the ani-rollback check for the 2nd stage bootloader is enabled. 1: Enabled 0: Disabled +BOOTLOADER_ANTI_ROLLBACK_UPDATE_IN_ROM, EFUSE_BLK0, 209, 1, [] Represents whether the ani-rollback SECURE_VERSION will be updated from the ROM bootloader. 1: Enable 0: Disable RECOVERY_BOOTLOADER_FLASH_SECTOR, EFUSE_BLK0, 210, 12, [] Represents the starting flash sector (flash sector size is 0x1000) of the recovery bootloader used by the ROM bootloader If the primary bootloader fails. 0 and 0xFFF - this feature is disabled -RMA_ENA, EFUSE_BLK0, 222, 2, [] Represents whether rma function is supported in download mode. 2'b01/2'b10: enabled2'b00/2'b11: disabled -RMA_SESSION_COUNTER, EFUSE_BLK0, 224, 3, [] Represents the number of times the RMA session has been entered -RMA_NONCE_ENA, EFUSE_BLK0, 227, 2, [] Represents whether random number NONCE is used in RMA and whether the KM module is used to generate the NONCE. 2'bx0: No NONCE 2'b1x: Use KM generate NONCE. -RMA_CHIP_INFO_SOURCE, EFUSE_BLK0, 229, 1, [] Represents whether HUK_info is selected as the source for calculating CHIP_info in RMA.1: use HUK_info 0: use UNIQ_id -RMA_DISABLE_FAST_VEF, EFUSE_BLK0, 230, 1, [] Represents whether disable FAST_VEF in RMA session.1: disable0: enable -PVT_0_GLITCH_EN, EFUSE_BLK0, 231, 1, [] Represents whether to enable PVT power glitch monitor function.1:Enable. 0:Disable +SDC_ENA, EFUSE_BLK0, 222, 2, [] Represents whether SDC function is supported in download mode. 2'b01/2'b10: enabled 2'b00/2'b11: disabled +SDC_SESSION_COUNTER, EFUSE_BLK0, 224, 3, [] Represents the number of times the SDC session has been entered +SDC_NONCE_ENA, EFUSE_BLK0, 227, 2, [] Represents whether random number NONCE is used in SDC and whether the KM module is used to generate the NONCE . 2'bx0: No NONCE 2'b1x: Use KM generate NONCE +SDC_CHIP_INFO_SOURCE, EFUSE_BLK0, 229, 1, [] Represents whether HUK_info is selected as the source for calculating CHIP_info in SDC. 1: use HUK_info 0: use UNIQ_id +SDC_DISABLE_FAST_VEF, EFUSE_BLK0, 230, 1, [] Represents whether disable FAST_VEF in SDC session. 1: disable 0: enable +PVT_0_GLITCH_EN, EFUSE_BLK0, 231, 1, [] Represents whether to enable PVT power glitch monitor function. 1:Enable. 0:Disable PVT_0_GLITCH_MODE, EFUSE_BLK0, 232, 2, [] Use to configure glitch mode -PVT_1_GLITCH_EN, EFUSE_BLK0, 234, 1, [] Represents whether to enable PVT power glitch monitor function.1:Enable. 0:Disable +PVT_1_GLITCH_EN, EFUSE_BLK0, 234, 1, [] Represents whether to enable PVT power glitch monitor function. 1:Enable. 0:Disable PVT_1_GLITCH_MODE, EFUSE_BLK0, 235, 2, [] Use to configure glitch mode -PMU_FLASH_POWER_SEL, EFUSE_BLK0, 237, 1, [] FLASH power select. 1'b1: use 3.3V1'b0: use 1.8V +PMU_FLASH_POWER_SEL, EFUSE_BLK0, 237, 1, [] FLASH power select. 1'b1: use 3.3V 1'b0: use 1.8V PMU_FLASH_POWER_SEL_EN, EFUSE_BLK0, 238, 1, [] FLASH power select enable signal. 1'b1 : validates EFUSE_PMU_FLASH_POWER_SEL 1'b0: invalidates EFUSE_PMU_FLASH_POWER_SEL POWER_GLITCH_EN, EFUSE_BLK0, 239, 4, [] set these bit enable power glitch enable -ENA_XTS_SHADOW, EFUSE_BLK0, 243, 1, [] Represents whether to enable XTS-AES shadow core countermeasure against fault injection attacks. 0: Disabled 1: Enabled -ENA_SPI_BOOT_CRYPT_SCRAMBLER, EFUSE_BLK0, 244, 1, [] Represents whether to enable ciphertext scrambler for external memory . 0: Disabled 1: Enabled -RE_ENABLE_JTAG_SOURCE, EFUSE_BLK0, 245, 1, [] Represents which Crypto peripheral is selected for re-enabling JTAG. 0: RMA 1: HMAC +ENA_XTS_SHADOW, EFUSE_BLK0, 243, 1, [] Represents whether to enable XTS-AES shadow core countermeasure against fault injection attacks. 0: Disabled 1: Enabled +ENA_SPI_BOOT_CRYPT_SCRAMBLER, EFUSE_BLK0, 244, 1, [] Represents whether to enable ciphertext scrambler for external memory . 0: Disabled 1: Enabled +RE_ENABLE_JTAG_SOURCE, EFUSE_BLK0, 245, 1, [] Represents which Crypto peripheral is selected for re-enabling JTAG. 0: SDC 1: HMAC MAC, EFUSE_BLK1, 40, 8, [MAC_FACTORY] MAC address , EFUSE_BLK1, 32, 8, [MAC_FACTORY] MAC address , EFUSE_BLK1, 24, 8, [MAC_FACTORY] MAC address , EFUSE_BLK1, 16, 8, [MAC_FACTORY] MAC address , EFUSE_BLK1, 8, 8, [MAC_FACTORY] MAC address , EFUSE_BLK1, 0, 8, [MAC_FACTORY] MAC address -MAC_EXT, EFUSE_BLK1, 56, 8, [] Stores the extended bits of MAC address -, EFUSE_BLK1, 48, 8, [] Stores the extended bits of MAC address +MAC_EXT, EFUSE_BLK1, 56, 8, [] Represents the extended bits of MAC address +, EFUSE_BLK1, 48, 8, [] Represents the extended bits of MAC address WAFER_VERSION_MINOR, EFUSE_BLK1, 114, 4, [] Minor chip version WAFER_VERSION_MAJOR, EFUSE_BLK1, 118, 2, [] Major chip version DISABLE_WAFER_VERSION_MAJOR, EFUSE_BLK1, 120, 1, [] Disables check of wafer version major @@ -192,7 +229,19 @@ PSRAM_CAP, EFUSE_BLK1, 127, 3, [] Psram TEMP, EFUSE_BLK1, 130, 2, [] Maximum ambient temperature that ESP Chip can work properly PSRAM_VENDOR, EFUSE_BLK1, 132, 2, [] Psram vendor PKG_VERSION, EFUSE_BLK1, 134, 2, [] Package version +OCODE, EFUSE_BLK1, 136, 8, [] OCode calibration +ACTIVE_HP_DBIAS, EFUSE_BLK1, 144, 4, [] Active HP DBIAS of fixed voltage +ACTIVE_LP_DBIAS, EFUSE_BLK1, 148, 4, [] Active LP DBIAS of fixed voltage +LSLP_HP_DBG, EFUSE_BLK1, 152, 2, [] LSLP HP DBG of fixed voltage +LSLP_HP_DBIAS, EFUSE_BLK1, 154, 4, [] LSLP HP DBIAS of fixed voltage +DSLP_LP_DBG, EFUSE_BLK1, 158, 4, [] DSLP LP DBG of fixed voltage +DSLP_LP_DBIAS, EFUSE_BLK1, 162, 5, [] DSLP LP DBIAS of fixed voltage +LP_HP_DBIAS_VOL_GAP, EFUSE_BLK1, 167, 5, [] DBIAS gap between LP and HP +PVT_DBIAS, EFUSE_BLK1, 172, 4, [] PVT DBIAS OPTIONAL_UNIQUE_ID, EFUSE_BLK2, 0, 128, [] Optional unique 128-bit ID +TEMP_CALIBRATION, EFUSE_BLK2, 128, 10, [] Temperature calibration +SPI_LDO_1V8_DREF, EFUSE_BLK2, 138, 4, [] SPI LDO 1.8 V DREF +SPI_LDO_1V8_MUL, EFUSE_BLK2, 142, 3, [] SPI LDO 1.8 V multiplier USER_DATA, EFUSE_BLK3, 0, 256, [BLOCK_USR_DATA] User data USER_DATA.MAC_CUSTOM, EFUSE_BLK3, 200, 48, [MAC_CUSTOM CUSTOM_MAC] Custom MAC KEY0, EFUSE_BLK4, 0, 256, [BLOCK_KEY0] Key0 or user data @@ -200,5 +249,16 @@ KEY1, EFUSE_BLK5, 0, 256, [BLOCK_KE KEY2, EFUSE_BLK6, 0, 256, [BLOCK_KEY2] Key2 or user data KEY3, EFUSE_BLK7, 0, 256, [BLOCK_KEY3] Key3 or user data KEY4, EFUSE_BLK8, 0, 256, [BLOCK_KEY4] Key4 or user data -SYS_DATA_PART2, EFUSE_BLK9, 0, 32, [BLOCK_SYS_DATA2] System data part 2 (reserved) -USB_DEVICE_EXCHG_PINS, EFUSE_BLK9, 192, 1, [] Represents whether enable usb device exchange pins of D+ and D- or not. 1: enabled 0: disabled +ADC1_DIFF_K, EFUSE_BLK9, 0, 11, [] Fitted slope (K) of ADC1 in differential mode +ADC1_DIFF_B, EFUSE_BLK9, 11, 10, [] Intercept (B) of ADC1 in differential mode +ADC1_P_K, EFUSE_BLK9, 21, 11, [] Fitted slope (K) of ADC1 in P mode +ADC1_P_B, EFUSE_BLK9, 32, 10, [] Intercept (B) of ADC1 in P mode +ADC1_N_K, EFUSE_BLK9, 42, 11, [] Fitted slope (K) of ADC1 in N mode +ADC1_N_B, EFUSE_BLK9, 53, 10, [] Intercept (B) of ADC1 in N mode +ADC2_DIFF_K, EFUSE_BLK9, 63, 11, [] Fitted slope (K) of ADC2 in differential mode +ADC2_DIFF_B, EFUSE_BLK9, 74, 10, [] Intercept (B) of ADC2 in differential mode +ADC2_P_K, EFUSE_BLK9, 84, 11, [] Fitted slope (K) of ADC2 in P mode +ADC2_P_B, EFUSE_BLK9, 95, 10, [] Intercept (B) of ADC2 in P mode +ADC2_N_K, EFUSE_BLK9, 105, 11, [] Fitted slope (K) of ADC2 in N mode +ADC2_N_B, EFUSE_BLK9, 116, 10, [] Intercept (B) of ADC2 in N mode +USB_DEVICE_EXCHG_PINS, EFUSE_BLK9, 192, 1, [] Represents whether enable usb device exchange pins of D+ and D- or not. 1: enabled 0: disabled diff --git a/components/efuse/esp32s31/include/esp_efuse_table.h b/components/efuse/esp32s31/include/esp_efuse_table.h index ca5e96f2082..20de43b93fb 100644 --- a/components/efuse/esp32s31/include/esp_efuse_table.h +++ b/components/efuse/esp32s31/include/esp_efuse_table.h @@ -10,7 +10,7 @@ extern "C" { #include "esp_efuse.h" -// md5_digest_table 1cdb8731d5e8193ceb48139f9db95994 +// md5_digest_table d75d0e39a18319b5287c3790c42a8d06 // This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY. // If you want to change some fields, you need to change esp_efuse_table.csv file // then run `efuse_common_table` or `efuse_custom_table` command it will generate this file. @@ -64,9 +64,9 @@ extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ECDSA_DISABLE_SOFT_K[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SEC_DPA_LEVEL[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_XTS_DPA_CLK_ENABLE[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_XTS_DPA_PSEUDO_LEVEL[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RMA_NONCE_ENA[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RMA_CHIP_INFO_SOURCE[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RMA_DISABLE_FAST_VEF[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SDC_NONCE_ENA[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SDC_CHIP_INFO_SOURCE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SDC_DISABLE_FAST_VEF[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ENA_XTS_SHADOW[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ENA_SPI_BOOT_CRYPT_SCRAMBLER[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RE_ENABLE_JTAG_SOURCE[]; @@ -98,8 +98,20 @@ extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PSRAM_CAP[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_TEMP[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PSRAM_VENDOR[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PKG_VERSION[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_OCODE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ACTIVE_HP_DBIAS[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ACTIVE_LP_DBIAS[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LSLP_HP_DBG[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LSLP_HP_DBIAS[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DSLP_LP_DBG[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DSLP_LP_DBIAS[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LP_HP_DBIAS_VOL_GAP[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PVT_DBIAS[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SYS_DATA_PART1[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_OPTIONAL_UNIQUE_ID[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_TEMP_CALIBRATION[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_LDO_1V8_DREF[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_LDO_1V8_MUL[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_USR_DATA[]; #define ESP_EFUSE_WR_DIS_USER_DATA ESP_EFUSE_WR_DIS_BLOCK_USR_DATA extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_CUSTOM_MAC[]; @@ -117,6 +129,18 @@ extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY4[]; #define ESP_EFUSE_WR_DIS_KEY4 ESP_EFUSE_WR_DIS_BLOCK_KEY4 extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_SYS_DATA2[]; #define ESP_EFUSE_WR_DIS_SYS_DATA_PART2 ESP_EFUSE_WR_DIS_BLOCK_SYS_DATA2 +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_DIFF_K[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_DIFF_B[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_P_K[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_P_B[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_N_K[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_N_B[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_DIFF_K[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_DIFF_B[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_P_K[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_P_B[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_N_K[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_N_B[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USB_DEVICE_EXCHG_PINS[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SOFT_DIS_JTAG[]; extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS[]; @@ -130,6 +154,19 @@ extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY3[]; #define ESP_EFUSE_RD_DIS_KEY3 ESP_EFUSE_RD_DIS_BLOCK_KEY3 extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY4[]; #define ESP_EFUSE_RD_DIS_KEY4 ESP_EFUSE_RD_DIS_BLOCK_KEY4 +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC1_DIFF_K[]; +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC1_DIFF_B[]; +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC1_P_K[]; +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC1_P_B[]; +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC1_N_K[]; +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC1_N_B[]; +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_DIFF_K[]; +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_DIFF_B[]; +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_P_K[]; +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_P_B[]; +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_N_K[]; +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_N_B[]; +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_USB_DEVICE_EXCHG_PINS[]; extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_JTAG[]; extern const esp_efuse_desc_t* ESP_EFUSE_DIS_FORCE_DOWNLOAD[]; extern const esp_efuse_desc_t* ESP_EFUSE_SPI_DOWNLOAD_MSPI_DIS[]; @@ -190,11 +227,11 @@ extern const esp_efuse_desc_t* ESP_EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION extern const esp_efuse_desc_t* ESP_EFUSE_BOOTLOADER_ANTI_ROLLBACK_EN[]; extern const esp_efuse_desc_t* ESP_EFUSE_BOOTLOADER_ANTI_ROLLBACK_UPDATE_IN_ROM[]; extern const esp_efuse_desc_t* ESP_EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR[]; -extern const esp_efuse_desc_t* ESP_EFUSE_RMA_ENA[]; -extern const esp_efuse_desc_t* ESP_EFUSE_RMA_SESSION_COUNTER[]; -extern const esp_efuse_desc_t* ESP_EFUSE_RMA_NONCE_ENA[]; -extern const esp_efuse_desc_t* ESP_EFUSE_RMA_CHIP_INFO_SOURCE[]; -extern const esp_efuse_desc_t* ESP_EFUSE_RMA_DISABLE_FAST_VEF[]; +extern const esp_efuse_desc_t* ESP_EFUSE_SDC_ENA[]; +extern const esp_efuse_desc_t* ESP_EFUSE_SDC_SESSION_COUNTER[]; +extern const esp_efuse_desc_t* ESP_EFUSE_SDC_NONCE_ENA[]; +extern const esp_efuse_desc_t* ESP_EFUSE_SDC_CHIP_INFO_SOURCE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_SDC_DISABLE_FAST_VEF[]; extern const esp_efuse_desc_t* ESP_EFUSE_PVT_0_GLITCH_EN[]; extern const esp_efuse_desc_t* ESP_EFUSE_PVT_0_GLITCH_MODE[]; extern const esp_efuse_desc_t* ESP_EFUSE_PVT_1_GLITCH_EN[]; @@ -218,7 +255,19 @@ extern const esp_efuse_desc_t* ESP_EFUSE_PSRAM_CAP[]; extern const esp_efuse_desc_t* ESP_EFUSE_TEMP[]; extern const esp_efuse_desc_t* ESP_EFUSE_PSRAM_VENDOR[]; extern const esp_efuse_desc_t* ESP_EFUSE_PKG_VERSION[]; +extern const esp_efuse_desc_t* ESP_EFUSE_OCODE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_ACTIVE_HP_DBIAS[]; +extern const esp_efuse_desc_t* ESP_EFUSE_ACTIVE_LP_DBIAS[]; +extern const esp_efuse_desc_t* ESP_EFUSE_LSLP_HP_DBG[]; +extern const esp_efuse_desc_t* ESP_EFUSE_LSLP_HP_DBIAS[]; +extern const esp_efuse_desc_t* ESP_EFUSE_DSLP_LP_DBG[]; +extern const esp_efuse_desc_t* ESP_EFUSE_DSLP_LP_DBIAS[]; +extern const esp_efuse_desc_t* ESP_EFUSE_LP_HP_DBIAS_VOL_GAP[]; +extern const esp_efuse_desc_t* ESP_EFUSE_PVT_DBIAS[]; extern const esp_efuse_desc_t* ESP_EFUSE_OPTIONAL_UNIQUE_ID[]; +extern const esp_efuse_desc_t* ESP_EFUSE_TEMP_CALIBRATION[]; +extern const esp_efuse_desc_t* ESP_EFUSE_SPI_LDO_1V8_DREF[]; +extern const esp_efuse_desc_t* ESP_EFUSE_SPI_LDO_1V8_MUL[]; extern const esp_efuse_desc_t* ESP_EFUSE_USER_DATA[]; #define ESP_EFUSE_BLOCK_USR_DATA ESP_EFUSE_USER_DATA extern const esp_efuse_desc_t* ESP_EFUSE_USER_DATA_MAC_CUSTOM[]; @@ -234,8 +283,18 @@ extern const esp_efuse_desc_t* ESP_EFUSE_KEY3[]; #define ESP_EFUSE_BLOCK_KEY3 ESP_EFUSE_KEY3 extern const esp_efuse_desc_t* ESP_EFUSE_KEY4[]; #define ESP_EFUSE_BLOCK_KEY4 ESP_EFUSE_KEY4 -extern const esp_efuse_desc_t* ESP_EFUSE_SYS_DATA_PART2[]; -#define ESP_EFUSE_BLOCK_SYS_DATA2 ESP_EFUSE_SYS_DATA_PART2 +extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_DIFF_K[]; +extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_DIFF_B[]; +extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_P_K[]; +extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_P_B[]; +extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_N_K[]; +extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_N_B[]; +extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_DIFF_K[]; +extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_DIFF_B[]; +extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_P_K[]; +extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_P_B[]; +extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_N_K[]; +extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_N_B[]; extern const esp_efuse_desc_t* ESP_EFUSE_USB_DEVICE_EXCHG_PINS[]; #ifdef __cplusplus diff --git a/components/soc/esp32s31/register/soc/efuse_reg.h b/components/soc/esp32s31/register/soc/efuse_reg.h index 2c8e727f22b..450bbd04fa6 100644 --- a/components/soc/esp32s31/register/soc/efuse_reg.h +++ b/components/soc/esp32s31/register/soc/efuse_reg.h @@ -3,9 +3,12 @@ * * SPDX-License-Identifier: Apache-2.0 OR MIT */ + #pragma once +#include "soc/reg_base.h" #include "soc/soc.h" + #ifdef __cplusplus extern "C" { #endif @@ -146,47 +149,323 @@ extern "C" { * Represents rd_wr_dis */ #define EFUSE_RD_WR_DIS_REG (DR_REG_EFUSE_BASE + 0x2c) -/** EFUSE_WR_DIS : RO; bitpos: [31:0]; default: 0; - * Represents whether programming of individual eFuse memory bit is disabled. For - * mapping between the bits of this field and the eFuse memory bits, please refer to - * Table \ref{tab:efuse-block0-para} and Table \ref{tab:efuse-block-1-10-para}.\\1: - * Disabled\\0: Enabled\\ +/** EFUSE_WR_DIS_RD_DIS : RO; bitpos: [0]; default: 0; + * Write disable bit 0 for EFUSE_RD_DIS */ -#define EFUSE_WR_DIS 0xFFFFFFFFU -#define EFUSE_WR_DIS_M (EFUSE_WR_DIS_V << EFUSE_WR_DIS_S) -#define EFUSE_WR_DIS_V 0xFFFFFFFFU -#define EFUSE_WR_DIS_S 0 +#define EFUSE_WR_DIS_RD_DIS (BIT(0)) +#define EFUSE_WR_DIS_RD_DIS_M (EFUSE_WR_DIS_RD_DIS_V << EFUSE_WR_DIS_RD_DIS_S) +#define EFUSE_WR_DIS_RD_DIS_V 0x00000001U +#define EFUSE_WR_DIS_RD_DIS_S 0 +/** EFUSE_WR_DIS_1 : RO; bitpos: [1]; default: 0; + * Write disable bit 1 for EFUSE_KM_RND_SWITCH_CYCLE, EFUSE_KM_DISABLE_DEPLOY_MODE, + * EFUSE_KM_DEPLOY_ONLY_ONCE, EFUSE_FORCE_USE_KEY_MANAGER_KEY, + * EFUSE_FORCE_DISABLE_SW_INIT_KEY, EFUSE_KM_XTS_KEY_LENGTH_256, EFUSE_LOCK_KM_KEY + */ +#define EFUSE_WR_DIS_1 (BIT(1)) +#define EFUSE_WR_DIS_1_M (EFUSE_WR_DIS_1_V << EFUSE_WR_DIS_1_S) +#define EFUSE_WR_DIS_1_V 0x00000001U +#define EFUSE_WR_DIS_1_S 1 +/** EFUSE_WR_DIS_2 : RO; bitpos: [2]; default: 0; + * Write disable bit 2 for EFUSE_DIS_USB_JTAG, EFUSE_DIS_USB_SERIAL_JTAG, + * EFUSE_DIS_FORCE_DOWNLOAD, EFUSE_SPI_DOWNLOAD_MSPI_DIS, EFUSE_DIS_TWAI, + * EFUSE_JTAG_SEL_ENABLE, EFUSE_DIS_PAD_JTAG, EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT, + * EFUSE_DIS_WIFI6, EFUSE_WDT_DELAY_SEL, EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE, + * EFUSE_DIS_WDT, EFUSE_DIS_SWD, EFUSE_PMU_FLASH_POWER_SEL, + * EFUSE_PMU_FLASH_POWER_SEL_EN, EFUSE_POWER_GLITCH_EN + */ +#define EFUSE_WR_DIS_2 (BIT(2)) +#define EFUSE_WR_DIS_2_M (EFUSE_WR_DIS_2_V << EFUSE_WR_DIS_2_S) +#define EFUSE_WR_DIS_2_V 0x00000001U +#define EFUSE_WR_DIS_2_S 2 +/** EFUSE_WR_DIS_3 : RO; bitpos: [3]; default: 0; + * Write disable bit 3 for EFUSE_PVT_0_GLITCH_EN, EFUSE_PVT_0_GLITCH_MODE, + * EFUSE_PVT_1_GLITCH_EN, EFUSE_PVT_1_GLITCH_MODE + */ +#define EFUSE_WR_DIS_3 (BIT(3)) +#define EFUSE_WR_DIS_3_M (EFUSE_WR_DIS_3_V << EFUSE_WR_DIS_3_S) +#define EFUSE_WR_DIS_3_V 0x00000001U +#define EFUSE_WR_DIS_3_S 3 +/** EFUSE_WR_DIS_SPI_BOOT_CRYPT_CNT : RO; bitpos: [4]; default: 0; + * Write disable bit 4 for EFUSE_SPI_BOOT_CRYPT_CNT + */ +#define EFUSE_WR_DIS_SPI_BOOT_CRYPT_CNT (BIT(4)) +#define EFUSE_WR_DIS_SPI_BOOT_CRYPT_CNT_M (EFUSE_WR_DIS_SPI_BOOT_CRYPT_CNT_V << EFUSE_WR_DIS_SPI_BOOT_CRYPT_CNT_S) +#define EFUSE_WR_DIS_SPI_BOOT_CRYPT_CNT_V 0x00000001U +#define EFUSE_WR_DIS_SPI_BOOT_CRYPT_CNT_S 4 +/** EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE0 : RO; bitpos: [5]; default: 0; + * Write disable bit 5 for EFUSE_SECURE_BOOT_KEY_REVOKE0 + */ +#define EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE0 (BIT(5)) +#define EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE0_M (EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE0_V << EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE0_S) +#define EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE0_V 0x00000001U +#define EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE0_S 5 +/** EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE1 : RO; bitpos: [6]; default: 0; + * Write disable bit 6 for EFUSE_SECURE_BOOT_KEY_REVOKE1 + */ +#define EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE1 (BIT(6)) +#define EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE1_M (EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE1_V << EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE1_S) +#define EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE1_V 0x00000001U +#define EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE1_S 6 +/** EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE2 : RO; bitpos: [7]; default: 0; + * Write disable bit 7 for EFUSE_SECURE_BOOT_KEY_REVOKE2 + */ +#define EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE2 (BIT(7)) +#define EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE2_M (EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE2_V << EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE2_S) +#define EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE2_V 0x00000001U +#define EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE2_S 7 +/** EFUSE_WR_DIS_KEY_PURPOSE_0 : RO; bitpos: [8]; default: 0; + * Write disable bit 8 for EFUSE_KEY_PURPOSE_0 + */ +#define EFUSE_WR_DIS_KEY_PURPOSE_0 (BIT(8)) +#define EFUSE_WR_DIS_KEY_PURPOSE_0_M (EFUSE_WR_DIS_KEY_PURPOSE_0_V << EFUSE_WR_DIS_KEY_PURPOSE_0_S) +#define EFUSE_WR_DIS_KEY_PURPOSE_0_V 0x00000001U +#define EFUSE_WR_DIS_KEY_PURPOSE_0_S 8 +/** EFUSE_WR_DIS_KEY_PURPOSE_1 : RO; bitpos: [9]; default: 0; + * Write disable bit 9 for EFUSE_KEY_PURPOSE_1 + */ +#define EFUSE_WR_DIS_KEY_PURPOSE_1 (BIT(9)) +#define EFUSE_WR_DIS_KEY_PURPOSE_1_M (EFUSE_WR_DIS_KEY_PURPOSE_1_V << EFUSE_WR_DIS_KEY_PURPOSE_1_S) +#define EFUSE_WR_DIS_KEY_PURPOSE_1_V 0x00000001U +#define EFUSE_WR_DIS_KEY_PURPOSE_1_S 9 +/** EFUSE_WR_DIS_KEY_PURPOSE_2 : RO; bitpos: [10]; default: 0; + * Write disable bit 10 for EFUSE_KEY_PURPOSE_2 + */ +#define EFUSE_WR_DIS_KEY_PURPOSE_2 (BIT(10)) +#define EFUSE_WR_DIS_KEY_PURPOSE_2_M (EFUSE_WR_DIS_KEY_PURPOSE_2_V << EFUSE_WR_DIS_KEY_PURPOSE_2_S) +#define EFUSE_WR_DIS_KEY_PURPOSE_2_V 0x00000001U +#define EFUSE_WR_DIS_KEY_PURPOSE_2_S 10 +/** EFUSE_WR_DIS_KEY_PURPOSE_3 : RO; bitpos: [11]; default: 0; + * Write disable bit 11 for EFUSE_KEY_PURPOSE_3 + */ +#define EFUSE_WR_DIS_KEY_PURPOSE_3 (BIT(11)) +#define EFUSE_WR_DIS_KEY_PURPOSE_3_M (EFUSE_WR_DIS_KEY_PURPOSE_3_V << EFUSE_WR_DIS_KEY_PURPOSE_3_S) +#define EFUSE_WR_DIS_KEY_PURPOSE_3_V 0x00000001U +#define EFUSE_WR_DIS_KEY_PURPOSE_3_S 11 +/** EFUSE_WR_DIS_KEY_PURPOSE_4 : RO; bitpos: [12]; default: 0; + * Write disable bit 12 for EFUSE_KEY_PURPOSE_4 + */ +#define EFUSE_WR_DIS_KEY_PURPOSE_4 (BIT(12)) +#define EFUSE_WR_DIS_KEY_PURPOSE_4_M (EFUSE_WR_DIS_KEY_PURPOSE_4_V << EFUSE_WR_DIS_KEY_PURPOSE_4_S) +#define EFUSE_WR_DIS_KEY_PURPOSE_4_V 0x00000001U +#define EFUSE_WR_DIS_KEY_PURPOSE_4_S 12 +/** EFUSE_WR_DIS_13 : RO; bitpos: [13]; default: 0; + * reserved + */ +#define EFUSE_WR_DIS_13 (BIT(13)) +#define EFUSE_WR_DIS_13_M (EFUSE_WR_DIS_13_V << EFUSE_WR_DIS_13_S) +#define EFUSE_WR_DIS_13_V 0x00000001U +#define EFUSE_WR_DIS_13_S 13 +/** EFUSE_WR_DIS_14 : RO; bitpos: [14]; default: 0; + * Write disable bit 14 for EFUSE_DIS_SM_CRYPT, EFUSE_ECC_FORCE_CONST_TIME, + * EFUSE_ECDSA_DISABLE_SOFT_K, EFUSE_SEC_DPA_LEVEL, EFUSE_XTS_DPA_CLK_ENABLE, + * EFUSE_XTS_DPA_PSEUDO_LEVEL, EFUSE_SDC_NONCE_ENA, EFUSE_SDC_CHIP_INFO_SOURCE, + * EFUSE_SDC_DISABLE_FAST_VEF, EFUSE_ENA_XTS_SHADOW, + * EFUSE_ENA_SPI_BOOT_CRYPT_SCRAMBLER, EFUSE_RE_ENABLE_JTAG_SOURCE + */ +#define EFUSE_WR_DIS_14 (BIT(14)) +#define EFUSE_WR_DIS_14_M (EFUSE_WR_DIS_14_V << EFUSE_WR_DIS_14_S) +#define EFUSE_WR_DIS_14_V 0x00000001U +#define EFUSE_WR_DIS_14_S 14 +/** EFUSE_WR_DIS_SECURE_BOOT_EN : RO; bitpos: [15]; default: 0; + * Write disable bit 15 for EFUSE_SECURE_BOOT_EN + */ +#define EFUSE_WR_DIS_SECURE_BOOT_EN (BIT(15)) +#define EFUSE_WR_DIS_SECURE_BOOT_EN_M (EFUSE_WR_DIS_SECURE_BOOT_EN_V << EFUSE_WR_DIS_SECURE_BOOT_EN_S) +#define EFUSE_WR_DIS_SECURE_BOOT_EN_V 0x00000001U +#define EFUSE_WR_DIS_SECURE_BOOT_EN_S 15 +/** EFUSE_WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE : RO; bitpos: [16]; default: 0; + * Write disable bit 16 for EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE + */ +#define EFUSE_WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE (BIT(16)) +#define EFUSE_WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE_M (EFUSE_WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE_V << EFUSE_WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE_S) +#define EFUSE_WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE_V 0x00000001U +#define EFUSE_WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE_S 16 +/** EFUSE_WR_DIS_17 : RO; bitpos: [17]; default: 0; + * reserved + */ +#define EFUSE_WR_DIS_17 (BIT(17)) +#define EFUSE_WR_DIS_17_M (EFUSE_WR_DIS_17_V << EFUSE_WR_DIS_17_S) +#define EFUSE_WR_DIS_17_V 0x00000001U +#define EFUSE_WR_DIS_17_S 17 +/** EFUSE_WR_DIS_18 : RO; bitpos: [18]; default: 0; + * Write disable bit 18 for EFUSE_FLASH_TYPE, EFUSE_DIS_USB_OTG_DOWNLOAD_MODE, + * EFUSE_FLASH_TPUW, EFUSE_DIS_DOWNLOAD_MODE, EFUSE_DIS_DIRECT_BOOT, + * EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT, EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE, + * EFUSE_ENABLE_SECURITY_DOWNLOAD, EFUSE_UART_PRINT_CONTROL, EFUSE_FORCE_SEND_RESUME, + * EFUSE_SECURE_VERSION + */ +#define EFUSE_WR_DIS_18 (BIT(18)) +#define EFUSE_WR_DIS_18_M (EFUSE_WR_DIS_18_V << EFUSE_WR_DIS_18_S) +#define EFUSE_WR_DIS_18_V 0x00000001U +#define EFUSE_WR_DIS_18_S 18 +/** EFUSE_WR_DIS_HUK_GEN_STATE : RO; bitpos: [19]; default: 0; + * Write disable bit 19 for EFUSE_HUK_GEN_STATE + */ +#define EFUSE_WR_DIS_HUK_GEN_STATE (BIT(19)) +#define EFUSE_WR_DIS_HUK_GEN_STATE_M (EFUSE_WR_DIS_HUK_GEN_STATE_V << EFUSE_WR_DIS_HUK_GEN_STATE_S) +#define EFUSE_WR_DIS_HUK_GEN_STATE_V 0x00000001U +#define EFUSE_WR_DIS_HUK_GEN_STATE_S 19 +/** EFUSE_WR_DIS_BLOCK1 : RO; bitpos: [20]; default: 0; + * Write disable bit 20 for BLOCK1 + */ +#define EFUSE_WR_DIS_BLOCK1 (BIT(20)) +#define EFUSE_WR_DIS_BLOCK1_M (EFUSE_WR_DIS_BLOCK1_V << EFUSE_WR_DIS_BLOCK1_S) +#define EFUSE_WR_DIS_BLOCK1_V 0x00000001U +#define EFUSE_WR_DIS_BLOCK1_S 20 +/** EFUSE_WR_DIS_BLOCK2 : RO; bitpos: [21]; default: 0; + * Write disable bit 21 for BLOCK2 + */ +#define EFUSE_WR_DIS_BLOCK2 (BIT(21)) +#define EFUSE_WR_DIS_BLOCK2_M (EFUSE_WR_DIS_BLOCK2_V << EFUSE_WR_DIS_BLOCK2_S) +#define EFUSE_WR_DIS_BLOCK2_V 0x00000001U +#define EFUSE_WR_DIS_BLOCK2_S 21 +/** EFUSE_WR_DIS_BLOCK3 : RO; bitpos: [22]; default: 0; + * Write disable bit 22 for BLOCK3 + */ +#define EFUSE_WR_DIS_BLOCK3 (BIT(22)) +#define EFUSE_WR_DIS_BLOCK3_M (EFUSE_WR_DIS_BLOCK3_V << EFUSE_WR_DIS_BLOCK3_S) +#define EFUSE_WR_DIS_BLOCK3_V 0x00000001U +#define EFUSE_WR_DIS_BLOCK3_S 22 +/** EFUSE_WR_DIS_BLOCK4 : RO; bitpos: [23]; default: 0; + * Write disable bit 23 for BLOCK4 + */ +#define EFUSE_WR_DIS_BLOCK4 (BIT(23)) +#define EFUSE_WR_DIS_BLOCK4_M (EFUSE_WR_DIS_BLOCK4_V << EFUSE_WR_DIS_BLOCK4_S) +#define EFUSE_WR_DIS_BLOCK4_V 0x00000001U +#define EFUSE_WR_DIS_BLOCK4_S 23 +/** EFUSE_WR_DIS_BLOCK5 : RO; bitpos: [24]; default: 0; + * Write disable bit 24 for BLOCK5 + */ +#define EFUSE_WR_DIS_BLOCK5 (BIT(24)) +#define EFUSE_WR_DIS_BLOCK5_M (EFUSE_WR_DIS_BLOCK5_V << EFUSE_WR_DIS_BLOCK5_S) +#define EFUSE_WR_DIS_BLOCK5_V 0x00000001U +#define EFUSE_WR_DIS_BLOCK5_S 24 +/** EFUSE_WR_DIS_BLOCK6 : RO; bitpos: [25]; default: 0; + * Write disable bit 25 for BLOCK6 + */ +#define EFUSE_WR_DIS_BLOCK6 (BIT(25)) +#define EFUSE_WR_DIS_BLOCK6_M (EFUSE_WR_DIS_BLOCK6_V << EFUSE_WR_DIS_BLOCK6_S) +#define EFUSE_WR_DIS_BLOCK6_V 0x00000001U +#define EFUSE_WR_DIS_BLOCK6_S 25 +/** EFUSE_WR_DIS_BLOCK7 : RO; bitpos: [26]; default: 0; + * Write disable bit 26 for BLOCK7 + */ +#define EFUSE_WR_DIS_BLOCK7 (BIT(26)) +#define EFUSE_WR_DIS_BLOCK7_M (EFUSE_WR_DIS_BLOCK7_V << EFUSE_WR_DIS_BLOCK7_S) +#define EFUSE_WR_DIS_BLOCK7_V 0x00000001U +#define EFUSE_WR_DIS_BLOCK7_S 26 +/** EFUSE_WR_DIS_BLOCK8 : RO; bitpos: [27]; default: 0; + * Write disable bit 27 for BLOCK8 + */ +#define EFUSE_WR_DIS_BLOCK8 (BIT(27)) +#define EFUSE_WR_DIS_BLOCK8_M (EFUSE_WR_DIS_BLOCK8_V << EFUSE_WR_DIS_BLOCK8_S) +#define EFUSE_WR_DIS_BLOCK8_V 0x00000001U +#define EFUSE_WR_DIS_BLOCK8_S 27 +/** EFUSE_WR_DIS_BLOCK9 : RO; bitpos: [28]; default: 0; + * Write disable bit 28 for BLOCK9 + */ +#define EFUSE_WR_DIS_BLOCK9 (BIT(28)) +#define EFUSE_WR_DIS_BLOCK9_M (EFUSE_WR_DIS_BLOCK9_V << EFUSE_WR_DIS_BLOCK9_S) +#define EFUSE_WR_DIS_BLOCK9_V 0x00000001U +#define EFUSE_WR_DIS_BLOCK9_S 28 +/** EFUSE_WR_DIS_29 : RO; bitpos: [29]; default: 0; + * reserved + */ +#define EFUSE_WR_DIS_29 (BIT(29)) +#define EFUSE_WR_DIS_29_M (EFUSE_WR_DIS_29_V << EFUSE_WR_DIS_29_S) +#define EFUSE_WR_DIS_29_V 0x00000001U +#define EFUSE_WR_DIS_29_S 29 +/** EFUSE_WR_DIS_30 : RO; bitpos: [30]; default: 0; + * reserved + */ +#define EFUSE_WR_DIS_30 (BIT(30)) +#define EFUSE_WR_DIS_30_M (EFUSE_WR_DIS_30_V << EFUSE_WR_DIS_30_S) +#define EFUSE_WR_DIS_30_V 0x00000001U +#define EFUSE_WR_DIS_30_S 30 +/** EFUSE_WR_DIS_SOFT_DIS_JTAG : RO; bitpos: [31]; default: 0; + * Write disable bit 31 for EFUSE_SOFT_DIS_JTAG + */ +#define EFUSE_WR_DIS_SOFT_DIS_JTAG (BIT(31)) +#define EFUSE_WR_DIS_SOFT_DIS_JTAG_M (EFUSE_WR_DIS_SOFT_DIS_JTAG_V << EFUSE_WR_DIS_SOFT_DIS_JTAG_S) +#define EFUSE_WR_DIS_SOFT_DIS_JTAG_V 0x00000001U +#define EFUSE_WR_DIS_SOFT_DIS_JTAG_S 31 /** EFUSE_RD_REPEAT_DATA0_REG register * Represents rd_repeat_data */ #define EFUSE_RD_REPEAT_DATA0_REG (DR_REG_EFUSE_BASE + 0x30) -/** EFUSE_RD_DIS : RO; bitpos: [6:0]; default: 0; - * Represents whether reading of individual eFuse block(block4~block9) is disabled or - * enabled.\\ 1: disabled\\ 0: enabled\\ +/** EFUSE_RD_DIS_BLOCK4 : RO; bitpos: [0]; default: 0; + * Read disable bit 0 for BLOCK4 */ -#define EFUSE_RD_DIS 0x0000007FU -#define EFUSE_RD_DIS_M (EFUSE_RD_DIS_V << EFUSE_RD_DIS_S) -#define EFUSE_RD_DIS_V 0x0000007FU -#define EFUSE_RD_DIS_S 0 -/** EFUSE_RD_RESERVE_0_39 : RW; bitpos: [9:7]; default: 0; - * Reserved, it was created by set_missed_fields_in_regs func +#define EFUSE_RD_DIS_BLOCK4 (BIT(0)) +#define EFUSE_RD_DIS_BLOCK4_M (EFUSE_RD_DIS_BLOCK4_V << EFUSE_RD_DIS_BLOCK4_S) +#define EFUSE_RD_DIS_BLOCK4_V 0x00000001U +#define EFUSE_RD_DIS_BLOCK4_S 0 +/** EFUSE_RD_DIS_BLOCK5 : RO; bitpos: [1]; default: 0; + * Read disable bit 1 for BLOCK5 */ -#define EFUSE_RD_RESERVE_0_39 0x00000007U -#define EFUSE_RD_RESERVE_0_39_M (EFUSE_RD_RESERVE_0_39_V << EFUSE_RD_RESERVE_0_39_S) -#define EFUSE_RD_RESERVE_0_39_V 0x00000007U -#define EFUSE_RD_RESERVE_0_39_S 7 +#define EFUSE_RD_DIS_BLOCK5 (BIT(1)) +#define EFUSE_RD_DIS_BLOCK5_M (EFUSE_RD_DIS_BLOCK5_V << EFUSE_RD_DIS_BLOCK5_S) +#define EFUSE_RD_DIS_BLOCK5_V 0x00000001U +#define EFUSE_RD_DIS_BLOCK5_S 1 +/** EFUSE_RD_DIS_BLOCK6 : RO; bitpos: [2]; default: 0; + * Read disable bit 2 for BLOCK6 + */ +#define EFUSE_RD_DIS_BLOCK6 (BIT(2)) +#define EFUSE_RD_DIS_BLOCK6_M (EFUSE_RD_DIS_BLOCK6_V << EFUSE_RD_DIS_BLOCK6_S) +#define EFUSE_RD_DIS_BLOCK6_V 0x00000001U +#define EFUSE_RD_DIS_BLOCK6_S 2 +/** EFUSE_RD_DIS_BLOCK7 : RO; bitpos: [3]; default: 0; + * Read disable bit 3 for BLOCK7 + */ +#define EFUSE_RD_DIS_BLOCK7 (BIT(3)) +#define EFUSE_RD_DIS_BLOCK7_M (EFUSE_RD_DIS_BLOCK7_V << EFUSE_RD_DIS_BLOCK7_S) +#define EFUSE_RD_DIS_BLOCK7_V 0x00000001U +#define EFUSE_RD_DIS_BLOCK7_S 3 +/** EFUSE_RD_DIS_BLOCK8 : RO; bitpos: [4]; default: 0; + * Read disable bit 4 for BLOCK8 + */ +#define EFUSE_RD_DIS_BLOCK8 (BIT(4)) +#define EFUSE_RD_DIS_BLOCK8_M (EFUSE_RD_DIS_BLOCK8_V << EFUSE_RD_DIS_BLOCK8_S) +#define EFUSE_RD_DIS_BLOCK8_V 0x00000001U +#define EFUSE_RD_DIS_BLOCK8_S 4 +/** EFUSE_RD_DIS_BLOCK9 : RO; bitpos: [5]; default: 0; + * Read disable bit 5 for BLOCK9 + */ +#define EFUSE_RD_DIS_BLOCK9 (BIT(5)) +#define EFUSE_RD_DIS_BLOCK9_M (EFUSE_RD_DIS_BLOCK9_V << EFUSE_RD_DIS_BLOCK9_S) +#define EFUSE_RD_DIS_BLOCK9_V 0x00000001U +#define EFUSE_RD_DIS_BLOCK9_S 5 +/** EFUSE_RD_DIS_6 : RO; bitpos: [6]; default: 0; + * reserved + */ +#define EFUSE_RD_DIS_6 (BIT(6)) +#define EFUSE_RD_DIS_6_M (EFUSE_RD_DIS_6_V << EFUSE_RD_DIS_6_S) +#define EFUSE_RD_DIS_6_V 0x00000001U +#define EFUSE_RD_DIS_6_S 6 +/** EFUSE_RESERVED_0_39 : R; bitpos: [9:7]; default: 0; + * reserved + * This field is only for internal debugging purposes. Do not use it in applications. + */ +#define EFUSE_RESERVED_0_39 0x00000007U +#define EFUSE_RESERVED_0_39_M (EFUSE_RESERVED_0_39_V << EFUSE_RESERVED_0_39_S) +#define EFUSE_RESERVED_0_39_V 0x00000007U +#define EFUSE_RESERVED_0_39_S 7 /** EFUSE_DIS_USB_JTAG : RO; bitpos: [10]; default: 0; - * Represents whether the function of usb switch to jtag is disabled or enabled.\\ 1: - * disabled\\ 0: enabled\\ + * Represents whether the function of usb switch to jtag is disabled or enabled. + * 1: disabled + * 0: enabled */ #define EFUSE_DIS_USB_JTAG (BIT(10)) #define EFUSE_DIS_USB_JTAG_M (EFUSE_DIS_USB_JTAG_V << EFUSE_DIS_USB_JTAG_S) #define EFUSE_DIS_USB_JTAG_V 0x00000001U #define EFUSE_DIS_USB_JTAG_S 10 /** EFUSE_DIS_USB_SERIAL_JTAG : RO; bitpos: [11]; default: 0; - * Represents whether USB-Serial-JTAG is disabled or enabled.\\ 1: disabled\\ 0: - * enabled\\ + * Represents whether USB-Serial-JTAG is disabled or enabled. + * 1: disabled + * 0: enabled + * + * This field is only for internal debugging purposes. Do not use it in applications. */ #define EFUSE_DIS_USB_SERIAL_JTAG (BIT(11)) #define EFUSE_DIS_USB_SERIAL_JTAG_M (EFUSE_DIS_USB_SERIAL_JTAG_V << EFUSE_DIS_USB_SERIAL_JTAG_S) @@ -194,23 +473,27 @@ extern "C" { #define EFUSE_DIS_USB_SERIAL_JTAG_S 11 /** EFUSE_DIS_FORCE_DOWNLOAD : RO; bitpos: [12]; default: 0; * Represents whether the function that forces chip into download mode is disabled or - * enabled.\\ 1: disabled\\ 0: enabled\\ + * enabled. + * 1: disabled + * 0: enabled */ #define EFUSE_DIS_FORCE_DOWNLOAD (BIT(12)) #define EFUSE_DIS_FORCE_DOWNLOAD_M (EFUSE_DIS_FORCE_DOWNLOAD_V << EFUSE_DIS_FORCE_DOWNLOAD_S) #define EFUSE_DIS_FORCE_DOWNLOAD_V 0x00000001U #define EFUSE_DIS_FORCE_DOWNLOAD_S 12 /** EFUSE_SPI_DOWNLOAD_MSPI_DIS : RO; bitpos: [13]; default: 0; - * Represents whether SPI0 controller during boot_mode_download is disabled or - * enabled.\\ 1: disabled\\ 0: enabled\\ + * Represents whether SPI0 controller during boot_mode_download is disabled or enabled. + * 1: disabled + * 0: enabled */ #define EFUSE_SPI_DOWNLOAD_MSPI_DIS (BIT(13)) #define EFUSE_SPI_DOWNLOAD_MSPI_DIS_M (EFUSE_SPI_DOWNLOAD_MSPI_DIS_V << EFUSE_SPI_DOWNLOAD_MSPI_DIS_S) #define EFUSE_SPI_DOWNLOAD_MSPI_DIS_V 0x00000001U #define EFUSE_SPI_DOWNLOAD_MSPI_DIS_S 13 /** EFUSE_DIS_TWAI : RO; bitpos: [14]; default: 0; - * Represents whether TWAI function is disabled or enabled.\\ 1: disabled\\ 0: - * enabled\\ + * Represents whether TWAI function is disabled or enabled. + * 1: disabled + * 0: enabled */ #define EFUSE_DIS_TWAI (BIT(14)) #define EFUSE_DIS_TWAI_M (EFUSE_DIS_TWAI_V << EFUSE_DIS_TWAI_S) @@ -219,23 +502,27 @@ extern "C" { /** EFUSE_JTAG_SEL_ENABLE : RO; bitpos: [15]; default: 0; * Represents whether the selection between usb_to_jtag and pad_to_jtag through * strapping gpio15 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0 - * is enabled or disabled.\\ 1: enabled\\ 0: disabled\\ + * is enabled or disabled. + * 1: enabled + * 0: disabled */ #define EFUSE_JTAG_SEL_ENABLE (BIT(15)) #define EFUSE_JTAG_SEL_ENABLE_M (EFUSE_JTAG_SEL_ENABLE_V << EFUSE_JTAG_SEL_ENABLE_S) #define EFUSE_JTAG_SEL_ENABLE_V 0x00000001U #define EFUSE_JTAG_SEL_ENABLE_S 15 /** EFUSE_SOFT_DIS_JTAG : RO; bitpos: [18:16]; default: 0; - * Represents whether JTAG is disabled in soft way.\\ Odd number: disabled\\ Even - * number: enabled\\ + * Represents whether JTAG is disabled in soft way. + * Odd number: disabled + * Even number: enabled */ #define EFUSE_SOFT_DIS_JTAG 0x00000007U #define EFUSE_SOFT_DIS_JTAG_M (EFUSE_SOFT_DIS_JTAG_V << EFUSE_SOFT_DIS_JTAG_S) #define EFUSE_SOFT_DIS_JTAG_V 0x00000007U #define EFUSE_SOFT_DIS_JTAG_S 16 /** EFUSE_DIS_PAD_JTAG : RO; bitpos: [19]; default: 0; - * Represents whether JTAG is disabled in the hard way(permanently).\\ 1: disabled\\ - * 0: enabled\\ + * Represents whether JTAG is disabled in the hard way(permanently). + * 1: disabled + * 0: enabled */ #define EFUSE_DIS_PAD_JTAG (BIT(19)) #define EFUSE_DIS_PAD_JTAG_M (EFUSE_DIS_PAD_JTAG_V << EFUSE_DIS_PAD_JTAG_S) @@ -243,22 +530,26 @@ extern "C" { #define EFUSE_DIS_PAD_JTAG_S 19 /** EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT : RO; bitpos: [20]; default: 0; * Represents whether flash encrypt function is disabled or enabled(except in SPI boot - * mode).\\ 1: disabled\\ 0: enabled\\ + * mode). + * 1: disabled + * 0: enabled */ #define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT (BIT(20)) #define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_M (EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V << EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S) #define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V 0x00000001U #define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S 20 -/** EFUSE_RD_RESERVE_0_53 : RW; bitpos: [21]; default: 0; - * Reserved, it was created by set_missed_fields_in_regs func +/** EFUSE_RESERVED_0_53 : R; bitpos: [21]; default: 0; + * reserved + * This field is only for internal debugging purposes. Do not use it in applications. */ -#define EFUSE_RD_RESERVE_0_53 (BIT(21)) -#define EFUSE_RD_RESERVE_0_53_M (EFUSE_RD_RESERVE_0_53_V << EFUSE_RD_RESERVE_0_53_S) -#define EFUSE_RD_RESERVE_0_53_V 0x00000001U -#define EFUSE_RD_RESERVE_0_53_S 21 +#define EFUSE_RESERVED_0_53 (BIT(21)) +#define EFUSE_RESERVED_0_53_M (EFUSE_RESERVED_0_53_V << EFUSE_RESERVED_0_53_S) +#define EFUSE_RESERVED_0_53_V 0x00000001U +#define EFUSE_RESERVED_0_53_S 21 /** EFUSE_DIS_WIFI6 : RO; bitpos: [22]; default: 0; - * Represents whether the WIFI6 feature is enabled or disabled. 1: WIFI6 is disabled, 0: - * WIFI6 is enabled. + * Represents whether the WIFI6 feature is enabled or disabled. 1: WIFI6 is disabled; + * 0: WIFI6 is enabled + * This field is only for internal debugging purposes. Do not use it in applications. */ #define EFUSE_DIS_WIFI6 (BIT(22)) #define EFUSE_DIS_WIFI6_M (EFUSE_DIS_WIFI6_V << EFUSE_DIS_WIFI6_S) @@ -272,13 +563,14 @@ extern "C" { #define EFUSE_HUK_GEN_STATE_M (EFUSE_HUK_GEN_STATE_V << EFUSE_HUK_GEN_STATE_S) #define EFUSE_HUK_GEN_STATE_V 0x0000001FU #define EFUSE_HUK_GEN_STATE_S 23 -/** EFUSE_RD_RESERVE_0_60 : RW; bitpos: [31:28]; default: 0; - * Reserved, it was created by set_missed_fields_in_regs func +/** EFUSE_RESERVED_0_60 : R; bitpos: [31:28]; default: 0; + * reserved + * This field is only for internal debugging purposes. Do not use it in applications. */ -#define EFUSE_RD_RESERVE_0_60 0x0000000FU -#define EFUSE_RD_RESERVE_0_60_M (EFUSE_RD_RESERVE_0_60_V << EFUSE_RD_RESERVE_0_60_S) -#define EFUSE_RD_RESERVE_0_60_V 0x0000000FU -#define EFUSE_RD_RESERVE_0_60_S 28 +#define EFUSE_RESERVED_0_60 0x0000000FU +#define EFUSE_RESERVED_0_60_M (EFUSE_RESERVED_0_60_V << EFUSE_RESERVED_0_60_S) +#define EFUSE_RESERVED_0_60_V 0x0000000FU +#define EFUSE_RESERVED_0_60_S 28 /** EFUSE_RD_REPEAT_DATA1_REG register * Represents rd_repeat_data @@ -292,17 +584,20 @@ extern "C" { #define EFUSE_KM_RND_SWITCH_CYCLE_M (EFUSE_KM_RND_SWITCH_CYCLE_V << EFUSE_KM_RND_SWITCH_CYCLE_S) #define EFUSE_KM_RND_SWITCH_CYCLE_V 0x00000001U #define EFUSE_KM_RND_SWITCH_CYCLE_S 0 -/** EFUSE_RD_RESERVE_0_65 : RW; bitpos: [1]; default: 0; - * Reserved, it was created by set_missed_fields_in_regs func +/** EFUSE_RESERVED_0_65 : R; bitpos: [1]; default: 0; + * reserved + * This field is only for internal debugging purposes. Do not use it in applications. */ -#define EFUSE_RD_RESERVE_0_65 (BIT(1)) -#define EFUSE_RD_RESERVE_0_65_M (EFUSE_RD_RESERVE_0_65_V << EFUSE_RD_RESERVE_0_65_S) -#define EFUSE_RD_RESERVE_0_65_V 0x00000001U -#define EFUSE_RD_RESERVE_0_65_S 1 +#define EFUSE_RESERVED_0_65 (BIT(1)) +#define EFUSE_RESERVED_0_65_M (EFUSE_RESERVED_0_65_V << EFUSE_RESERVED_0_65_S) +#define EFUSE_RESERVED_0_65_V 0x00000001U +#define EFUSE_RESERVED_0_65_S 1 /** EFUSE_KM_DISABLE_DEPLOY_MODE : RO; bitpos: [6:2]; default: 0; - * Represents whether the deploy mode of key manager is disable or not. \\ 1: disabled - * \\ 0: enabled.\\ bit 0: ecsda, bit 1: flash & spi boot srambler, bit2: hmac & aes, - * bit3: ds & rma nonce, bit4: psram + * Represents whether the deploy mode of key manager is disable or not. + * 1: disabled + * 0: enabled. + * bit 0: ecsda, bit 1: flash & spi boot srambler, bit2: hmac & aes, bit3: ds & SDC + * nonce, bit4: psram */ #define EFUSE_KM_DISABLE_DEPLOY_MODE 0x0000001FU #define EFUSE_KM_DISABLE_DEPLOY_MODE_M (EFUSE_KM_DISABLE_DEPLOY_MODE_V << EFUSE_KM_DISABLE_DEPLOY_MODE_S) @@ -310,8 +605,12 @@ extern "C" { #define EFUSE_KM_DISABLE_DEPLOY_MODE_S 2 /** EFUSE_KM_DEPLOY_ONLY_ONCE : RO; bitpos: [11:7]; default: 0; * Represents whether corresponding key can only be deployed once. 1 is true, 0 is - * false. \\ 0: ecsda\\ 1: flash & spi boot srambler\\ 2: hmac & aes\\ 3: ds & rma - * nonce\\ 4: psram\\ + * false. + * 0: ecsda + * 1: flash & spi boot srambler + * 2: hmac & aes + * 3: ds & SDC nonce + * 4: psram */ #define EFUSE_KM_DEPLOY_ONLY_ONCE 0x0000001FU #define EFUSE_KM_DEPLOY_ONLY_ONCE_M (EFUSE_KM_DEPLOY_ONLY_ONCE_V << EFUSE_KM_DEPLOY_ONLY_ONCE_S) @@ -319,7 +618,12 @@ extern "C" { #define EFUSE_KM_DEPLOY_ONLY_ONCE_S 7 /** EFUSE_FORCE_USE_KEY_MANAGER_KEY : RO; bitpos: [16:12]; default: 0; * Represents whether corresponding key must come from key manager. 1 is true, 0 is - * false.\\ 0: ecsda\\ 1: flash\\ 2: reserved\\ 3: reserved\\ 4: psram\\ + * false. + * 0: ecsda + * 1: flash + * 2: reserved + * 3: reserved + * 4: psram */ #define EFUSE_FORCE_USE_KEY_MANAGER_KEY 0x0000001FU #define EFUSE_FORCE_USE_KEY_MANAGER_KEY_M (EFUSE_FORCE_USE_KEY_MANAGER_KEY_V << EFUSE_FORCE_USE_KEY_MANAGER_KEY_S) @@ -335,69 +639,72 @@ extern "C" { #define EFUSE_FORCE_DISABLE_SW_INIT_KEY_S 17 /** EFUSE_KM_XTS_KEY_LENGTH_256 : RO; bitpos: [18]; default: 0; * Represents whether to configure flash encryption use xts-128 key. else use xts-256 - * key. \\ 0: 128-bit key \\ 1: 256-bit key\\ + * key. + * 0: 128-bit key + * 1: 256-bit key */ #define EFUSE_KM_XTS_KEY_LENGTH_256 (BIT(18)) #define EFUSE_KM_XTS_KEY_LENGTH_256_M (EFUSE_KM_XTS_KEY_LENGTH_256_V << EFUSE_KM_XTS_KEY_LENGTH_256_S) #define EFUSE_KM_XTS_KEY_LENGTH_256_V 0x00000001U #define EFUSE_KM_XTS_KEY_LENGTH_256_S 18 /** EFUSE_WDT_DELAY_SEL : RO; bitpos: [19]; default: 0; - * Represents the threshold level of the RTC watchdog STG0 timeout.\\0: Original - * threshold configuration value of STG0 *2 \\1: Original threshold configuration - * value of STG0 *4 \\2: Original threshold configuration value of STG0 *8 \\3: - * Original threshold configuration value of STG0 *16 \\ + * Represents the threshold level of the RTC watchdog STG0 timeout. + * 0: Original threshold configuration value of STG0 *2 + * 1: Original threshold configuration value of STG0 *4 + * 2: Original threshold configuration value of STG0 *8 + * 3: Original threshold configuration value of STG0 *16 */ #define EFUSE_WDT_DELAY_SEL (BIT(19)) #define EFUSE_WDT_DELAY_SEL_M (EFUSE_WDT_DELAY_SEL_V << EFUSE_WDT_DELAY_SEL_S) #define EFUSE_WDT_DELAY_SEL_V 0x00000001U #define EFUSE_WDT_DELAY_SEL_S 19 /** EFUSE_DIS_SM_CRYPT : RO; bitpos: [20]; default: 0; - * Represents whether to disable all the SM crypto functions, including SM2, SM3.\\ 1: - * disabled\\ 0: enabled\\ + * Represents whether to disable all the SM crypto functions, including SM2, SM3. + * 1: disabled + * 0: enabled */ #define EFUSE_DIS_SM_CRYPT (BIT(20)) #define EFUSE_DIS_SM_CRYPT_M (EFUSE_DIS_SM_CRYPT_V << EFUSE_DIS_SM_CRYPT_S) #define EFUSE_DIS_SM_CRYPT_V 0x00000001U #define EFUSE_DIS_SM_CRYPT_S 20 /** EFUSE_SPI_BOOT_CRYPT_CNT : RO; bitpos: [23:21]; default: 0; - * Represents whether SPI boot encrypt/decrypt is disabled or enabled.\\ Odd number of - * 1: enabled\\ Even number of 1: disabled\\ + * Represents whether SPI boot encrypt/decrypt is disabled or enabled. + * Odd number of 1: enabled + * Even number of 1: disabled */ #define EFUSE_SPI_BOOT_CRYPT_CNT 0x00000007U #define EFUSE_SPI_BOOT_CRYPT_CNT_M (EFUSE_SPI_BOOT_CRYPT_CNT_V << EFUSE_SPI_BOOT_CRYPT_CNT_S) #define EFUSE_SPI_BOOT_CRYPT_CNT_V 0x00000007U #define EFUSE_SPI_BOOT_CRYPT_CNT_S 21 /** EFUSE_SECURE_BOOT_KEY_REVOKE0 : RO; bitpos: [24]; default: 0; - * Represents whether revoking first secure boot key is enabled or disabled.\\ 1: - * enabled\\ 0: disabled\\ + * Revoke 1st secure boot key */ #define EFUSE_SECURE_BOOT_KEY_REVOKE0 (BIT(24)) #define EFUSE_SECURE_BOOT_KEY_REVOKE0_M (EFUSE_SECURE_BOOT_KEY_REVOKE0_V << EFUSE_SECURE_BOOT_KEY_REVOKE0_S) #define EFUSE_SECURE_BOOT_KEY_REVOKE0_V 0x00000001U #define EFUSE_SECURE_BOOT_KEY_REVOKE0_S 24 /** EFUSE_SECURE_BOOT_KEY_REVOKE1 : RO; bitpos: [25]; default: 0; - * Represents whether revoking second secure boot key is enabled or disabled.\\ 1: - * enabled\\ 0: disabled\\ + * Revoke 2nd secure boot key */ #define EFUSE_SECURE_BOOT_KEY_REVOKE1 (BIT(25)) #define EFUSE_SECURE_BOOT_KEY_REVOKE1_M (EFUSE_SECURE_BOOT_KEY_REVOKE1_V << EFUSE_SECURE_BOOT_KEY_REVOKE1_S) #define EFUSE_SECURE_BOOT_KEY_REVOKE1_V 0x00000001U #define EFUSE_SECURE_BOOT_KEY_REVOKE1_S 25 /** EFUSE_SECURE_BOOT_KEY_REVOKE2 : RO; bitpos: [26]; default: 0; - * Represents whether revoking third secure boot key is enabled or disabled.\\ 1: - * enabled\\ 0: disabled\\ + * Revoke 3rd secure boot key */ #define EFUSE_SECURE_BOOT_KEY_REVOKE2 (BIT(26)) #define EFUSE_SECURE_BOOT_KEY_REVOKE2_M (EFUSE_SECURE_BOOT_KEY_REVOKE2_V << EFUSE_SECURE_BOOT_KEY_REVOKE2_S) #define EFUSE_SECURE_BOOT_KEY_REVOKE2_V 0x00000001U #define EFUSE_SECURE_BOOT_KEY_REVOKE2_S 26 -/** EFUSE_RD_RESERVE_0_91 : RW; bitpos: [31:27]; default: 0; - * Reserved, it was created by set_missed_fields_in_regs func +/** EFUSE_RESERVED_0_91 : R; bitpos: [31:27]; default: 0; + * reserved + * This field is only for internal debugging purposes. Do not use it in applications. */ -#define EFUSE_RD_RESERVE_0_91 0x0000001FU -#define EFUSE_RD_RESERVE_0_91_M (EFUSE_RD_RESERVE_0_91_V << EFUSE_RD_RESERVE_0_91_S) -#define EFUSE_RD_RESERVE_0_91_V 0x0000001FU -#define EFUSE_RD_RESERVE_0_91_S 27 +#define EFUSE_RESERVED_0_91 0x0000001FU +#define EFUSE_RESERVED_0_91_M (EFUSE_RESERVED_0_91_V << EFUSE_RESERVED_0_91_S) +#define EFUSE_RESERVED_0_91_V 0x0000001FU +#define EFUSE_RESERVED_0_91_S 27 /** EFUSE_RD_REPEAT_DATA2_REG register * Represents rd_repeat_data @@ -439,16 +746,18 @@ extern "C" { #define EFUSE_KEY_PURPOSE_4_V 0x0000001FU #define EFUSE_KEY_PURPOSE_4_S 20 /** EFUSE_ECC_FORCE_CONST_TIME : RO; bitpos: [25]; default: 0; - * Represents whether permanently turn on ECC const-time mode. \\ 1: turn on\\ 0: turn - * off\\ + * Represents whether permanently turn on ECC const-time mode. + * 1: turn on + * 0: turn off */ #define EFUSE_ECC_FORCE_CONST_TIME (BIT(25)) #define EFUSE_ECC_FORCE_CONST_TIME_M (EFUSE_ECC_FORCE_CONST_TIME_V << EFUSE_ECC_FORCE_CONST_TIME_S) #define EFUSE_ECC_FORCE_CONST_TIME_V 0x00000001U #define EFUSE_ECC_FORCE_CONST_TIME_S 25 /** EFUSE_ECDSA_DISABLE_SOFT_K : RO; bitpos: [26]; default: 0; - * Represents whether permanently turn off ECDSA software set KEY.\\ 1: turn off\\ 0: - * turn on\\ + * Represents whether permanently turn off ECDSA software set KEY. + * 1: turn off + * 0: turn on */ #define EFUSE_ECDSA_DISABLE_SOFT_K (BIT(26)) #define EFUSE_ECDSA_DISABLE_SOFT_K_M (EFUSE_ECDSA_DISABLE_SOFT_K_V << EFUSE_ECDSA_DISABLE_SOFT_K_S) @@ -462,56 +771,62 @@ extern "C" { #define EFUSE_SEC_DPA_LEVEL_V 0x00000003U #define EFUSE_SEC_DPA_LEVEL_S 27 /** EFUSE_XTS_DPA_CLK_ENABLE : RO; bitpos: [29]; default: 0; - * Represents whether to enable xts clock anti-dpa attack function.\\0: Disabled. \\1: - * Enabled\\ + * Represents whether to enable xts clock anti-dpa attack function. + * 0: Disabled. + * 1: Enabled */ #define EFUSE_XTS_DPA_CLK_ENABLE (BIT(29)) #define EFUSE_XTS_DPA_CLK_ENABLE_M (EFUSE_XTS_DPA_CLK_ENABLE_V << EFUSE_XTS_DPA_CLK_ENABLE_S) #define EFUSE_XTS_DPA_CLK_ENABLE_V 0x00000001U #define EFUSE_XTS_DPA_CLK_ENABLE_S 29 -/** EFUSE_RD_RESERVE_0_126 : RW; bitpos: [31:30]; default: 0; - * Reserved, it was created by set_missed_fields_in_regs func +/** EFUSE_RESERVED_0_126 : R; bitpos: [31:30]; default: 0; + * reserved + * This field is only for internal debugging purposes. Do not use it in applications. */ -#define EFUSE_RD_RESERVE_0_126 0x00000003U -#define EFUSE_RD_RESERVE_0_126_M (EFUSE_RD_RESERVE_0_126_V << EFUSE_RD_RESERVE_0_126_S) -#define EFUSE_RD_RESERVE_0_126_V 0x00000003U -#define EFUSE_RD_RESERVE_0_126_S 30 +#define EFUSE_RESERVED_0_126 0x00000003U +#define EFUSE_RESERVED_0_126_M (EFUSE_RESERVED_0_126_V << EFUSE_RESERVED_0_126_S) +#define EFUSE_RESERVED_0_126_V 0x00000003U +#define EFUSE_RESERVED_0_126_S 30 /** EFUSE_RD_REPEAT_DATA3_REG register * Represents rd_repeat_data */ #define EFUSE_RD_REPEAT_DATA3_REG (DR_REG_EFUSE_BASE + 0x3c) /** EFUSE_XTS_DPA_PSEUDO_LEVEL : RO; bitpos: [1:0]; default: 0; - * Represents the control of the xts pseudo-round anti-dpa attack function.\\ 0: - * controlled by register.\\ 1-3: the higher the value is, the more pseudo-rounds are - * inserted to the xts-aes calculation\\ + * Represents the control of the xts pseudo-round anti-dpa attack function. 0: + * controlled by register. 1-3: the higher the value is; the more pseudo-rounds are + * inserted to the xts-aes calculation */ #define EFUSE_XTS_DPA_PSEUDO_LEVEL 0x00000003U #define EFUSE_XTS_DPA_PSEUDO_LEVEL_M (EFUSE_XTS_DPA_PSEUDO_LEVEL_V << EFUSE_XTS_DPA_PSEUDO_LEVEL_S) #define EFUSE_XTS_DPA_PSEUDO_LEVEL_V 0x00000003U #define EFUSE_XTS_DPA_PSEUDO_LEVEL_S 0 /** EFUSE_SECURE_BOOT_EN : RO; bitpos: [2]; default: 0; - * Represents whether secure boot is enabled or disabled.\\ 1: enabled\\ 0: disabled\\ + * Represents whether secure boot is enabled or disabled. + * 1: enabled + * 0: disabled */ #define EFUSE_SECURE_BOOT_EN (BIT(2)) #define EFUSE_SECURE_BOOT_EN_M (EFUSE_SECURE_BOOT_EN_V << EFUSE_SECURE_BOOT_EN_S) #define EFUSE_SECURE_BOOT_EN_V 0x00000001U #define EFUSE_SECURE_BOOT_EN_S 2 /** EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE : RO; bitpos: [3]; default: 0; - * Represents whether revoking aggressive secure boot is enabled or disabled.\\ 1: - * enabled.\\ 0: disabled\\ + * Represents whether revoking aggressive secure boot is enabled or disabled. + * 1: enabled. + * 0: disabled */ #define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE (BIT(3)) #define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_M (EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_V << EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_S) #define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_V 0x00000001U #define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_S 3 -/** EFUSE_RD_RESERVE_0_132 : RW; bitpos: [4]; default: 0; - * Reserved, it was created by set_missed_fields_in_regs func +/** EFUSE_RESERVED_0_132 : R; bitpos: [4]; default: 0; + * reserved + * This field is only for internal debugging purposes. Do not use it in applications. */ -#define EFUSE_RD_RESERVE_0_132 (BIT(4)) -#define EFUSE_RD_RESERVE_0_132_M (EFUSE_RD_RESERVE_0_132_V << EFUSE_RD_RESERVE_0_132_S) -#define EFUSE_RD_RESERVE_0_132_V 0x00000001U -#define EFUSE_RD_RESERVE_0_132_S 4 +#define EFUSE_RESERVED_0_132 (BIT(4)) +#define EFUSE_RESERVED_0_132_M (EFUSE_RESERVED_0_132_V << EFUSE_RESERVED_0_132_S) +#define EFUSE_RESERVED_0_132_V 0x00000001U +#define EFUSE_RESERVED_0_132_S 4 /** EFUSE_FLASH_TYPE : RO; bitpos: [5]; default: 0; * flash type: 0: nor flash, 1: nand flash */ @@ -519,13 +834,14 @@ extern "C" { #define EFUSE_FLASH_TYPE_M (EFUSE_FLASH_TYPE_V << EFUSE_FLASH_TYPE_S) #define EFUSE_FLASH_TYPE_V 0x00000001U #define EFUSE_FLASH_TYPE_S 5 -/** EFUSE_RD_RESERVE_0_134 : RW; bitpos: [8:6]; default: 0; - * Reserved, it was created by set_missed_fields_in_regs func +/** EFUSE_RESERVED_0_134 : R; bitpos: [8:6]; default: 0; + * reserved + * This field is only for internal debugging purposes. Do not use it in applications. */ -#define EFUSE_RD_RESERVE_0_134 0x00000007U -#define EFUSE_RD_RESERVE_0_134_M (EFUSE_RD_RESERVE_0_134_V << EFUSE_RD_RESERVE_0_134_S) -#define EFUSE_RD_RESERVE_0_134_V 0x00000007U -#define EFUSE_RD_RESERVE_0_134_S 6 +#define EFUSE_RESERVED_0_134 0x00000007U +#define EFUSE_RESERVED_0_134_M (EFUSE_RESERVED_0_134_V << EFUSE_RESERVED_0_134_S) +#define EFUSE_RESERVED_0_134_V 0x00000007U +#define EFUSE_RESERVED_0_134_S 6 /** EFUSE_DIS_USB_OTG_DOWNLOAD_MODE : RO; bitpos: [9]; default: 0; * Set this bit to disable download via USB-OTG. */ @@ -533,13 +849,14 @@ extern "C" { #define EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_M (EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_V << EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_S) #define EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_V 0x00000001U #define EFUSE_DIS_USB_OTG_DOWNLOAD_MODE_S 9 -/** EFUSE_RD_RESERVE_0_138 : RW; bitpos: [11:10]; default: 0; - * Reserved, it was created by set_missed_fields_in_regs func +/** EFUSE_RESERVED_0_138 : R; bitpos: [11:10]; default: 0; + * reserved + * This field is only for internal debugging purposes. Do not use it in applications. */ -#define EFUSE_RD_RESERVE_0_138 0x00000003U -#define EFUSE_RD_RESERVE_0_138_M (EFUSE_RD_RESERVE_0_138_V << EFUSE_RD_RESERVE_0_138_S) -#define EFUSE_RD_RESERVE_0_138_V 0x00000003U -#define EFUSE_RD_RESERVE_0_138_S 10 +#define EFUSE_RESERVED_0_138 0x00000003U +#define EFUSE_RESERVED_0_138_M (EFUSE_RESERVED_0_138_V << EFUSE_RESERVED_0_138_S) +#define EFUSE_RESERVED_0_138_V 0x00000003U +#define EFUSE_RESERVED_0_138_S 10 /** EFUSE_FLASH_TPUW : RO; bitpos: [15:12]; default: 0; * Represents the flash waiting time after power-up, in unit of ms. When the value * less than 15, the waiting time is the programmed value. Otherwise, the waiting time @@ -550,76 +867,87 @@ extern "C" { #define EFUSE_FLASH_TPUW_V 0x0000000FU #define EFUSE_FLASH_TPUW_S 12 /** EFUSE_DIS_DOWNLOAD_MODE : RO; bitpos: [16]; default: 0; - * Represents whether Download mode is disabled or enabled.\\ 1: disabled\\ 0: - * enabled\\ + * Represents whether Download mode is disabled or enabled. + * 1: disabled + * 0: enabled */ #define EFUSE_DIS_DOWNLOAD_MODE (BIT(16)) #define EFUSE_DIS_DOWNLOAD_MODE_M (EFUSE_DIS_DOWNLOAD_MODE_V << EFUSE_DIS_DOWNLOAD_MODE_S) #define EFUSE_DIS_DOWNLOAD_MODE_V 0x00000001U #define EFUSE_DIS_DOWNLOAD_MODE_S 16 /** EFUSE_DIS_DIRECT_BOOT : RO; bitpos: [17]; default: 0; - * Represents whether direct boot mode is disabled or enabled.\\ 1: disabled\\ 0: - * enabled\\ + * Represents whether direct boot mode is disabled or enabled. + * 1: disabled + * 0: enabled */ #define EFUSE_DIS_DIRECT_BOOT (BIT(17)) #define EFUSE_DIS_DIRECT_BOOT_M (EFUSE_DIS_DIRECT_BOOT_V << EFUSE_DIS_DIRECT_BOOT_S) #define EFUSE_DIS_DIRECT_BOOT_V 0x00000001U #define EFUSE_DIS_DIRECT_BOOT_S 17 /** EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT : RO; bitpos: [18]; default: 0; - * Represents whether print from USB-Serial-JTAG is disabled or enabled.\\ 1: - * disabled\\ 0: enabled\\ + * Represents whether print from USB-Serial-JTAG is disabled or enabled. + * 1: disabled + * 0: enabled */ #define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT (BIT(18)) #define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_M (EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_V << EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_S) #define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_V 0x00000001U #define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_S 18 /** EFUSE_LOCK_KM_KEY : RO; bitpos: [19]; default: 0; - * Represetns whether to lock the efuse xts key.\\ 1. Lock\\ 0: Unlock\\ + * Represetns whether to lock the efuse xts key. + * 1. Lock + * 0: Unlock */ #define EFUSE_LOCK_KM_KEY (BIT(19)) #define EFUSE_LOCK_KM_KEY_M (EFUSE_LOCK_KM_KEY_V << EFUSE_LOCK_KM_KEY_S) #define EFUSE_LOCK_KM_KEY_V 0x00000001U #define EFUSE_LOCK_KM_KEY_S 19 /** EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE : RO; bitpos: [20]; default: 0; - * Represents whether the USB-Serial-JTAG download function is disabled or enabled.\\ - * 1: Disable\\ 0: Enable\\ + * Represents whether the USB-Serial-JTAG download function is disabled or enabled. + * 1: Disable + * 0: Enable */ #define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE (BIT(20)) #define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_M (EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_V << EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_S) #define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_V 0x00000001U #define EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE_S 20 /** EFUSE_ENABLE_SECURITY_DOWNLOAD : RO; bitpos: [21]; default: 0; - * Represents whether security download is enabled or disabled.\\ 1: enabled\\ 0: - * disabled\\ + * Represents whether security download is enabled or disabled. + * 1: enabled + * 0: disabled */ #define EFUSE_ENABLE_SECURITY_DOWNLOAD (BIT(21)) #define EFUSE_ENABLE_SECURITY_DOWNLOAD_M (EFUSE_ENABLE_SECURITY_DOWNLOAD_V << EFUSE_ENABLE_SECURITY_DOWNLOAD_S) #define EFUSE_ENABLE_SECURITY_DOWNLOAD_V 0x00000001U #define EFUSE_ENABLE_SECURITY_DOWNLOAD_S 21 /** EFUSE_UART_PRINT_CONTROL : RO; bitpos: [23:22]; default: 0; - * Represents the type of UART printing.\\ 00: force enable printing\\ 01: enable - * printing when GPIO8 is reset at low level\\ 10: enable printing when GPIO8 is reset - * at high level\\ 11: force disable printing\\ + * Represents the type of UART printing. + * 00: force enable printing + * 01: enable printing when GPIO8 is reset at low level + * 10: enable printing when GPIO8 is reset at high level + * 11: force disable printing */ #define EFUSE_UART_PRINT_CONTROL 0x00000003U #define EFUSE_UART_PRINT_CONTROL_M (EFUSE_UART_PRINT_CONTROL_V << EFUSE_UART_PRINT_CONTROL_S) #define EFUSE_UART_PRINT_CONTROL_V 0x00000003U #define EFUSE_UART_PRINT_CONTROL_S 22 /** EFUSE_FORCE_SEND_RESUME : RO; bitpos: [24]; default: 0; - * Represents whether ROM code is forced to send a resume command during SPI boot.\\ - * 1: forced\\ 0:not forced\\ + * Represents whether ROM code is forced to send a resume command during SPI boot. + * 1: forced + * 0:not forced */ #define EFUSE_FORCE_SEND_RESUME (BIT(24)) #define EFUSE_FORCE_SEND_RESUME_M (EFUSE_FORCE_SEND_RESUME_V << EFUSE_FORCE_SEND_RESUME_S) #define EFUSE_FORCE_SEND_RESUME_V 0x00000001U #define EFUSE_FORCE_SEND_RESUME_S 24 -/** EFUSE_RD_RESERVE_0_153 : RW; bitpos: [31:25]; default: 0; - * Reserved, it was created by set_missed_fields_in_regs func +/** EFUSE_RESERVED_0_153 : R; bitpos: [31:25]; default: 0; + * reserved + * This field is only for internal debugging purposes. Do not use it in applications. */ -#define EFUSE_RD_RESERVE_0_153 0x0000007FU -#define EFUSE_RD_RESERVE_0_153_M (EFUSE_RD_RESERVE_0_153_V << EFUSE_RD_RESERVE_0_153_S) -#define EFUSE_RD_RESERVE_0_153_V 0x0000007FU -#define EFUSE_RD_RESERVE_0_153_S 25 +#define EFUSE_RESERVED_0_153 0x0000007FU +#define EFUSE_RESERVED_0_153_M (EFUSE_RESERVED_0_153_V << EFUSE_RESERVED_0_153_S) +#define EFUSE_RESERVED_0_153_V 0x0000007FU +#define EFUSE_RESERVED_0_153_S 25 /** EFUSE_RD_REPEAT_DATA4_REG register * Represents rd_repeat_data @@ -634,39 +962,44 @@ extern "C" { #define EFUSE_SECURE_VERSION_S 0 /** EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE : RO; bitpos: [16]; default: 0; * Represents whether FAST VERIFY ON WAKE is disabled or enabled when Secure Boot is - * enabled.\\ 1: disabled\\ 0: enabled\\ + * enabled. + * 1: disabled + * 0: enabled */ #define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE (BIT(16)) #define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_M (EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_V << EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_S) #define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_V 0x00000001U #define EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE_S 16 /** EFUSE_HYS_EN_PAD : RO; bitpos: [17]; default: 0; - * Represents whether the hysteresis function of corresponding PAD is enabled.\\ 1: - * enabled\\ 0:disabled\\ + * Represents whether the hysteresis function of corresponding PAD is enabled. + * 1: enabled + * 0:disabled */ #define EFUSE_HYS_EN_PAD (BIT(17)) #define EFUSE_HYS_EN_PAD_M (EFUSE_HYS_EN_PAD_V << EFUSE_HYS_EN_PAD_S) #define EFUSE_HYS_EN_PAD_V 0x00000001U #define EFUSE_HYS_EN_PAD_S 17 -/** EFUSE_RD_RESERVE_0_178 : RW; bitpos: [31:18]; default: 0; - * Reserved, it was created by set_missed_fields_in_regs func +/** EFUSE_RESERVED_0_178 : R; bitpos: [31:18]; default: 0; + * reserved + * This field is only for internal debugging purposes. Do not use it in applications. */ -#define EFUSE_RD_RESERVE_0_178 0x00003FFFU -#define EFUSE_RD_RESERVE_0_178_M (EFUSE_RD_RESERVE_0_178_V << EFUSE_RD_RESERVE_0_178_S) -#define EFUSE_RD_RESERVE_0_178_V 0x00003FFFU -#define EFUSE_RD_RESERVE_0_178_S 18 +#define EFUSE_RESERVED_0_178 0x00003FFFU +#define EFUSE_RESERVED_0_178_M (EFUSE_RESERVED_0_178_V << EFUSE_RESERVED_0_178_S) +#define EFUSE_RESERVED_0_178_V 0x00003FFFU +#define EFUSE_RESERVED_0_178_S 18 /** EFUSE_RD_REPEAT_DATA5_REG register * Represents rd_repeat_data */ #define EFUSE_RD_REPEAT_DATA5_REG (DR_REG_EFUSE_BASE + 0x44) -/** EFUSE_RD_RESERVE_0_192 : RW; bitpos: [1:0]; default: 0; - * Reserved, it was created by set_missed_fields_in_regs func +/** EFUSE_RESERVED_0_192 : R; bitpos: [1:0]; default: 0; + * reserved + * This field is only for internal debugging purposes. Do not use it in applications. */ -#define EFUSE_RD_RESERVE_0_192 0x00000003U -#define EFUSE_RD_RESERVE_0_192_M (EFUSE_RD_RESERVE_0_192_V << EFUSE_RD_RESERVE_0_192_S) -#define EFUSE_RD_RESERVE_0_192_V 0x00000003U -#define EFUSE_RD_RESERVE_0_192_S 0 +#define EFUSE_RESERVED_0_192 0x00000003U +#define EFUSE_RESERVED_0_192_M (EFUSE_RESERVED_0_192_V << EFUSE_RESERVED_0_192_S) +#define EFUSE_RESERVED_0_192_V 0x00000003U +#define EFUSE_RESERVED_0_192_S 0 /** EFUSE_DCDC_VSET_EN : RO; bitpos: [2]; default: 0; * Select dcdc vset use efuse_dcdc_vset. */ @@ -688,13 +1021,14 @@ extern "C" { #define EFUSE_DIS_SWD_M (EFUSE_DIS_SWD_V << EFUSE_DIS_SWD_S) #define EFUSE_DIS_SWD_V 0x00000001U #define EFUSE_DIS_SWD_S 4 -/** EFUSE_RD_RESERVE_0_197 : RW; bitpos: [10:5]; default: 0; - * Reserved, it was created by set_missed_fields_in_regs func +/** EFUSE_RESERVED_0_197 : R; bitpos: [10:5]; default: 0; + * reserved + * This field is only for internal debugging purposes. Do not use it in applications. */ -#define EFUSE_RD_RESERVE_0_197 0x0000003FU -#define EFUSE_RD_RESERVE_0_197_M (EFUSE_RD_RESERVE_0_197_V << EFUSE_RD_RESERVE_0_197_S) -#define EFUSE_RD_RESERVE_0_197_V 0x0000003FU -#define EFUSE_RD_RESERVE_0_197_S 5 +#define EFUSE_RESERVED_0_197 0x0000003FU +#define EFUSE_RESERVED_0_197_M (EFUSE_RESERVED_0_197_V << EFUSE_RESERVED_0_197_S) +#define EFUSE_RESERVED_0_197_V 0x0000003FU +#define EFUSE_RESERVED_0_197_S 5 /** EFUSE_SECURE_BOOT_SHA384_EN : RO; bitpos: [11]; default: 0; * Represents whether secure boot using SHA-384 is enabled. 0: Disable 1: Enable */ @@ -711,8 +1045,9 @@ extern "C" { #define EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION_V 0x0000000FU #define EFUSE_BOOTLOADER_ANTI_ROLLBACK_SECURE_VERSION_S 12 /** EFUSE_BOOTLOADER_ANTI_ROLLBACK_EN : RO; bitpos: [16]; default: 0; - * Represents whether the ani-rollback check for the 2nd stage bootloader is - * enabled.\\1: Enabled\\0: Disabled\\ + * Represents whether the ani-rollback check for the 2nd stage bootloader is enabled. + * 1: Enabled + * 0: Disabled */ #define EFUSE_BOOTLOADER_ANTI_ROLLBACK_EN (BIT(16)) #define EFUSE_BOOTLOADER_ANTI_ROLLBACK_EN_M (EFUSE_BOOTLOADER_ANTI_ROLLBACK_EN_V << EFUSE_BOOTLOADER_ANTI_ROLLBACK_EN_S) @@ -720,7 +1055,9 @@ extern "C" { #define EFUSE_BOOTLOADER_ANTI_ROLLBACK_EN_S 16 /** EFUSE_BOOTLOADER_ANTI_ROLLBACK_UPDATE_IN_ROM : RO; bitpos: [17]; default: 0; * Represents whether the ani-rollback SECURE_VERSION will be updated from the ROM - * bootloader.\\1: Enable\\0: Disable\\ + * bootloader. + * 1: Enable + * 0: Disable */ #define EFUSE_BOOTLOADER_ANTI_ROLLBACK_UPDATE_IN_ROM (BIT(17)) #define EFUSE_BOOTLOADER_ANTI_ROLLBACK_UPDATE_IN_ROM_M (EFUSE_BOOTLOADER_ANTI_ROLLBACK_UPDATE_IN_ROM_V << EFUSE_BOOTLOADER_ANTI_ROLLBACK_UPDATE_IN_ROM_S) @@ -735,52 +1072,60 @@ extern "C" { #define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_M (EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_V << EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_S) #define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_V 0x00000FFFU #define EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_S 18 -/** EFUSE_RMA_ENA : RO; bitpos: [31:30]; default: 0; - * Represents whether rma function is supported in download mode.\\ 2'b01/2'b10: - * enabled\\2'b00/2'b11: disabled\\ +/** EFUSE_SDC_ENA : RO; bitpos: [31:30]; default: 0; + * Represents whether SDC function is supported in download mode. + * 2'b01/2'b10: enabled + * 2'b00/2'b11: disabled */ -#define EFUSE_RMA_ENA 0x00000003U -#define EFUSE_RMA_ENA_M (EFUSE_RMA_ENA_V << EFUSE_RMA_ENA_S) -#define EFUSE_RMA_ENA_V 0x00000003U -#define EFUSE_RMA_ENA_S 30 +#define EFUSE_SDC_ENA 0x00000003U +#define EFUSE_SDC_ENA_M (EFUSE_SDC_ENA_V << EFUSE_SDC_ENA_S) +#define EFUSE_SDC_ENA_V 0x00000003U +#define EFUSE_SDC_ENA_S 30 /** EFUSE_RD_REPEAT_DATA6_REG register * Represents rd_repeat_data */ #define EFUSE_RD_REPEAT_DATA6_REG (DR_REG_EFUSE_BASE + 0x48) -/** EFUSE_RMA_SESSION_COUNTER : RO; bitpos: [2:0]; default: 0; - * Represents the number of times the RMA session has been entered. +/** EFUSE_SDC_SESSION_COUNTER : RO; bitpos: [2:0]; default: 0; + * Represents the number of times the SDC session has been entered. */ -#define EFUSE_RMA_SESSION_COUNTER 0x00000007U -#define EFUSE_RMA_SESSION_COUNTER_M (EFUSE_RMA_SESSION_COUNTER_V << EFUSE_RMA_SESSION_COUNTER_S) -#define EFUSE_RMA_SESSION_COUNTER_V 0x00000007U -#define EFUSE_RMA_SESSION_COUNTER_S 0 -/** EFUSE_RMA_NONCE_ENA : RO; bitpos: [4:3]; default: 0; - * Represents whether random number NONCE is used in RMA and whether the KM module is - * used to generate the NONCE\\. 2'bx0: No NONCE\\ 2'b1x: Use KM generate NONCE.\\ +#define EFUSE_SDC_SESSION_COUNTER 0x00000007U +#define EFUSE_SDC_SESSION_COUNTER_M (EFUSE_SDC_SESSION_COUNTER_V << EFUSE_SDC_SESSION_COUNTER_S) +#define EFUSE_SDC_SESSION_COUNTER_V 0x00000007U +#define EFUSE_SDC_SESSION_COUNTER_S 0 +/** EFUSE_SDC_NONCE_ENA : RO; bitpos: [4:3]; default: 0; + * Represents whether random number NONCE is used in SDC and whether the KM module is + * used to generate the NONCE + * . 2'bx0: No NONCE + * 2'b1x: Use KM generate NONCE. */ -#define EFUSE_RMA_NONCE_ENA 0x00000003U -#define EFUSE_RMA_NONCE_ENA_M (EFUSE_RMA_NONCE_ENA_V << EFUSE_RMA_NONCE_ENA_S) -#define EFUSE_RMA_NONCE_ENA_V 0x00000003U -#define EFUSE_RMA_NONCE_ENA_S 3 -/** EFUSE_RMA_CHIP_INFO_SOURCE : RO; bitpos: [5]; default: 0; +#define EFUSE_SDC_NONCE_ENA 0x00000003U +#define EFUSE_SDC_NONCE_ENA_M (EFUSE_SDC_NONCE_ENA_V << EFUSE_SDC_NONCE_ENA_S) +#define EFUSE_SDC_NONCE_ENA_V 0x00000003U +#define EFUSE_SDC_NONCE_ENA_S 3 +/** EFUSE_SDC_CHIP_INFO_SOURCE : RO; bitpos: [5]; default: 0; * Represents whether HUK_info is selected as the source for calculating CHIP_info in - * RMA.\\1: use HUK_info\\ 0: use UNIQ_id\\ + * SDC. + * 1: use HUK_info + * 0: use UNIQ_id */ -#define EFUSE_RMA_CHIP_INFO_SOURCE (BIT(5)) -#define EFUSE_RMA_CHIP_INFO_SOURCE_M (EFUSE_RMA_CHIP_INFO_SOURCE_V << EFUSE_RMA_CHIP_INFO_SOURCE_S) -#define EFUSE_RMA_CHIP_INFO_SOURCE_V 0x00000001U -#define EFUSE_RMA_CHIP_INFO_SOURCE_S 5 -/** EFUSE_RMA_DISABLE_FAST_VEF : RO; bitpos: [6]; default: 0; - * Represents whether disable FAST_VEF in RMA session.\\1: disable\\0: enable\\ +#define EFUSE_SDC_CHIP_INFO_SOURCE (BIT(5)) +#define EFUSE_SDC_CHIP_INFO_SOURCE_M (EFUSE_SDC_CHIP_INFO_SOURCE_V << EFUSE_SDC_CHIP_INFO_SOURCE_S) +#define EFUSE_SDC_CHIP_INFO_SOURCE_V 0x00000001U +#define EFUSE_SDC_CHIP_INFO_SOURCE_S 5 +/** EFUSE_SDC_DISABLE_FAST_VEF : RO; bitpos: [6]; default: 0; + * Represents whether disable FAST_VEF in SDC session. + * 1: disable + * 0: enable */ -#define EFUSE_RMA_DISABLE_FAST_VEF (BIT(6)) -#define EFUSE_RMA_DISABLE_FAST_VEF_M (EFUSE_RMA_DISABLE_FAST_VEF_V << EFUSE_RMA_DISABLE_FAST_VEF_S) -#define EFUSE_RMA_DISABLE_FAST_VEF_V 0x00000001U -#define EFUSE_RMA_DISABLE_FAST_VEF_S 6 +#define EFUSE_SDC_DISABLE_FAST_VEF (BIT(6)) +#define EFUSE_SDC_DISABLE_FAST_VEF_M (EFUSE_SDC_DISABLE_FAST_VEF_V << EFUSE_SDC_DISABLE_FAST_VEF_S) +#define EFUSE_SDC_DISABLE_FAST_VEF_V 0x00000001U +#define EFUSE_SDC_DISABLE_FAST_VEF_S 6 /** EFUSE_PVT_0_GLITCH_EN : RO; bitpos: [7]; default: 0; - * Represents whether to enable PVT power glitch monitor function.\\1:Enable. - * \\0:Disable + * Represents whether to enable PVT power glitch monitor function. + * 1:Enable. + * 0:Disable */ #define EFUSE_PVT_0_GLITCH_EN (BIT(7)) #define EFUSE_PVT_0_GLITCH_EN_M (EFUSE_PVT_0_GLITCH_EN_V << EFUSE_PVT_0_GLITCH_EN_S) @@ -794,8 +1139,9 @@ extern "C" { #define EFUSE_PVT_0_GLITCH_MODE_V 0x00000003U #define EFUSE_PVT_0_GLITCH_MODE_S 8 /** EFUSE_PVT_1_GLITCH_EN : RO; bitpos: [10]; default: 0; - * Represents whether to enable PVT power glitch monitor function.\\1:Enable. - * \\0:Disable + * Represents whether to enable PVT power glitch monitor function. + * 1:Enable. + * 0:Disable */ #define EFUSE_PVT_1_GLITCH_EN (BIT(10)) #define EFUSE_PVT_1_GLITCH_EN_M (EFUSE_PVT_1_GLITCH_EN_V << EFUSE_PVT_1_GLITCH_EN_S) @@ -809,7 +1155,9 @@ extern "C" { #define EFUSE_PVT_1_GLITCH_MODE_V 0x00000003U #define EFUSE_PVT_1_GLITCH_MODE_S 11 /** EFUSE_PMU_FLASH_POWER_SEL : RO; bitpos: [13]; default: 0; - * FLASH power select.\\ 1'b1: use 3.3V\\1'b0: use 1.8V + * FLASH power select. + * 1'b1: use 3.3V + * 1'b0: use 1.8V */ #define EFUSE_PMU_FLASH_POWER_SEL (BIT(13)) #define EFUSE_PMU_FLASH_POWER_SEL_M (EFUSE_PMU_FLASH_POWER_SEL_V << EFUSE_PMU_FLASH_POWER_SEL_S) @@ -832,35 +1180,40 @@ extern "C" { #define EFUSE_POWER_GLITCH_EN_S 15 /** EFUSE_ENA_XTS_SHADOW : RO; bitpos: [19]; default: 0; * Represents whether to enable XTS-AES shadow core countermeasure against fault - * injection attacks. \\ 0: Disabled\\ 1: Enabled\\ + * injection attacks. + * 0: Disabled + * 1: Enabled */ #define EFUSE_ENA_XTS_SHADOW (BIT(19)) #define EFUSE_ENA_XTS_SHADOW_M (EFUSE_ENA_XTS_SHADOW_V << EFUSE_ENA_XTS_SHADOW_S) #define EFUSE_ENA_XTS_SHADOW_V 0x00000001U #define EFUSE_ENA_XTS_SHADOW_S 19 /** EFUSE_ENA_SPI_BOOT_CRYPT_SCRAMBLER : RO; bitpos: [20]; default: 0; - * Represents whether to enable ciphertext scrambler for external memory . \\ 0: - * Disabled\\ 1: Enabled\\ + * Represents whether to enable ciphertext scrambler for external memory . + * 0: Disabled + * 1: Enabled */ #define EFUSE_ENA_SPI_BOOT_CRYPT_SCRAMBLER (BIT(20)) #define EFUSE_ENA_SPI_BOOT_CRYPT_SCRAMBLER_M (EFUSE_ENA_SPI_BOOT_CRYPT_SCRAMBLER_V << EFUSE_ENA_SPI_BOOT_CRYPT_SCRAMBLER_S) #define EFUSE_ENA_SPI_BOOT_CRYPT_SCRAMBLER_V 0x00000001U #define EFUSE_ENA_SPI_BOOT_CRYPT_SCRAMBLER_S 20 /** EFUSE_RE_ENABLE_JTAG_SOURCE : RO; bitpos: [21]; default: 0; - * Represents which Crypto peripheral is selected for re-enabling JTAG. \\ 0: RMA\\ 1: - * HMAC\\ + * Represents which Crypto peripheral is selected for re-enabling JTAG. + * 0: SDC + * 1: HMAC */ #define EFUSE_RE_ENABLE_JTAG_SOURCE (BIT(21)) #define EFUSE_RE_ENABLE_JTAG_SOURCE_M (EFUSE_RE_ENABLE_JTAG_SOURCE_V << EFUSE_RE_ENABLE_JTAG_SOURCE_S) #define EFUSE_RE_ENABLE_JTAG_SOURCE_V 0x00000001U #define EFUSE_RE_ENABLE_JTAG_SOURCE_S 21 -/** EFUSE_RD_RESERVE_0_246 : RW; bitpos: [31:22]; default: 0; - * Reserved, it was created by set_missed_fields_in_regs func +/** EFUSE_RESERVED_0_246 : R; bitpos: [31:22]; default: 0; + * reserved + * This field is only for internal debugging purposes. Do not use it in applications. */ -#define EFUSE_RD_RESERVE_0_246 0x000003FFU -#define EFUSE_RD_RESERVE_0_246_M (EFUSE_RD_RESERVE_0_246_V << EFUSE_RD_RESERVE_0_246_S) -#define EFUSE_RD_RESERVE_0_246_V 0x000003FFU -#define EFUSE_RD_RESERVE_0_246_S 22 +#define EFUSE_RESERVED_0_246 0x000003FFU +#define EFUSE_RESERVED_0_246_M (EFUSE_RESERVED_0_246_V << EFUSE_RESERVED_0_246_S) +#define EFUSE_RESERVED_0_246_V 0x000003FFU +#define EFUSE_RESERVED_0_246_S 22 /** EFUSE_RD_REPEAT_DATA7_REG register * Represents rd_repeat_data @@ -868,18 +1221,20 @@ extern "C" { #define EFUSE_RD_REPEAT_DATA7_REG (DR_REG_EFUSE_BASE + 0x4c) /** EFUSE_REPEAT7_RSVD : RO; bitpos: [15:0]; default: 0; * Reserved. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define EFUSE_REPEAT7_RSVD 0x0000FFFFU #define EFUSE_REPEAT7_RSVD_M (EFUSE_REPEAT7_RSVD_V << EFUSE_REPEAT7_RSVD_S) #define EFUSE_REPEAT7_RSVD_V 0x0000FFFFU #define EFUSE_REPEAT7_RSVD_S 0 -/** EFUSE_RD_RESERVE_0_272 : RW; bitpos: [31:16]; default: 0; - * Reserved, it was created by set_missed_fields_in_regs func +/** EFUSE_RESERVED_0_272 : R; bitpos: [31:16]; default: 0; + * reserved + * This field is only for internal debugging purposes. Do not use it in applications. */ -#define EFUSE_RD_RESERVE_0_272 0x0000FFFFU -#define EFUSE_RD_RESERVE_0_272_M (EFUSE_RD_RESERVE_0_272_V << EFUSE_RD_RESERVE_0_272_S) -#define EFUSE_RD_RESERVE_0_272_V 0x0000FFFFU -#define EFUSE_RD_RESERVE_0_272_S 16 +#define EFUSE_RESERVED_0_272 0x0000FFFFU +#define EFUSE_RESERVED_0_272_M (EFUSE_RESERVED_0_272_V << EFUSE_RESERVED_0_272_S) +#define EFUSE_RESERVED_0_272_V 0x0000FFFFU +#define EFUSE_RESERVED_0_272_S 16 /** EFUSE_RD_MAC_SYS0_REG register * Represents rd_mac_sys @@ -914,10 +1269,13 @@ extern "C" { /** EFUSE_RD_MAC_SYS2_REG register * Represents rd_mac_sys + * This register is only for internal debugging purposes. Do not use it in + * applications. */ #define EFUSE_RD_MAC_SYS2_REG (DR_REG_EFUSE_BASE + 0x58) /** EFUSE_MAC_RESERVED_0 : RO; bitpos: [13:0]; default: 0; * Reserved. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define EFUSE_MAC_RESERVED_0 0x00003FFFU #define EFUSE_MAC_RESERVED_0_M (EFUSE_MAC_RESERVED_0_V << EFUSE_MAC_RESERVED_0_S) @@ -925,6 +1283,7 @@ extern "C" { #define EFUSE_MAC_RESERVED_0_S 0 /** EFUSE_MAC_RESERVED_1 : RO; bitpos: [31:14]; default: 0; * Reserved. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define EFUSE_MAC_RESERVED_1 0x0003FFFFU #define EFUSE_MAC_RESERVED_1_M (EFUSE_MAC_RESERVED_1_V << EFUSE_MAC_RESERVED_1_S) @@ -937,6 +1296,7 @@ extern "C" { #define EFUSE_RD_MAC_SYS3_REG (DR_REG_EFUSE_BASE + 0x5c) /** EFUSE_MAC_RESERVED_2 : RO; bitpos: [17:0]; default: 0; * Reserved. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define EFUSE_MAC_RESERVED_2 0x0003FFFFU #define EFUSE_MAC_RESERVED_2_M (EFUSE_MAC_RESERVED_2_V << EFUSE_MAC_RESERVED_2_S) @@ -1024,25 +1384,89 @@ extern "C" { #define EFUSE_PKG_VERSION_M (EFUSE_PKG_VERSION_V << EFUSE_PKG_VERSION_S) #define EFUSE_PKG_VERSION_V 0x00000003U #define EFUSE_PKG_VERSION_S 6 -/** EFUSE_RESERVED_1_136 : R; bitpos: [31:8]; default: 0; - * reserved +/** EFUSE_OCODE : R; bitpos: [15:8]; default: 0; + * OCode calibration */ -#define EFUSE_RESERVED_1_136 0x00FFFFFFU -#define EFUSE_RESERVED_1_136_M (EFUSE_RESERVED_1_136_V << EFUSE_RESERVED_1_136_S) -#define EFUSE_RESERVED_1_136_V 0x00FFFFFFU -#define EFUSE_RESERVED_1_136_S 8 +#define EFUSE_OCODE 0x000000FFU +#define EFUSE_OCODE_M (EFUSE_OCODE_V << EFUSE_OCODE_S) +#define EFUSE_OCODE_V 0x000000FFU +#define EFUSE_OCODE_S 8 +/** EFUSE_ACTIVE_HP_DBIAS : R; bitpos: [19:16]; default: 0; + * Active HP DBIAS of fixed voltage + */ +#define EFUSE_ACTIVE_HP_DBIAS 0x0000000FU +#define EFUSE_ACTIVE_HP_DBIAS_M (EFUSE_ACTIVE_HP_DBIAS_V << EFUSE_ACTIVE_HP_DBIAS_S) +#define EFUSE_ACTIVE_HP_DBIAS_V 0x0000000FU +#define EFUSE_ACTIVE_HP_DBIAS_S 16 +/** EFUSE_ACTIVE_LP_DBIAS : R; bitpos: [23:20]; default: 0; + * Active LP DBIAS of fixed voltage + */ +#define EFUSE_ACTIVE_LP_DBIAS 0x0000000FU +#define EFUSE_ACTIVE_LP_DBIAS_M (EFUSE_ACTIVE_LP_DBIAS_V << EFUSE_ACTIVE_LP_DBIAS_S) +#define EFUSE_ACTIVE_LP_DBIAS_V 0x0000000FU +#define EFUSE_ACTIVE_LP_DBIAS_S 20 +/** EFUSE_LSLP_HP_DBG : R; bitpos: [25:24]; default: 0; + * LSLP HP DBG of fixed voltage + */ +#define EFUSE_LSLP_HP_DBG 0x00000003U +#define EFUSE_LSLP_HP_DBG_M (EFUSE_LSLP_HP_DBG_V << EFUSE_LSLP_HP_DBG_S) +#define EFUSE_LSLP_HP_DBG_V 0x00000003U +#define EFUSE_LSLP_HP_DBG_S 24 +/** EFUSE_LSLP_HP_DBIAS : R; bitpos: [29:26]; default: 0; + * LSLP HP DBIAS of fixed voltage + */ +#define EFUSE_LSLP_HP_DBIAS 0x0000000FU +#define EFUSE_LSLP_HP_DBIAS_M (EFUSE_LSLP_HP_DBIAS_V << EFUSE_LSLP_HP_DBIAS_S) +#define EFUSE_LSLP_HP_DBIAS_V 0x0000000FU +#define EFUSE_LSLP_HP_DBIAS_S 26 +/** EFUSE_DSLP_LP_DBG : R; bitpos: [31:30]; default: 0; + * DSLP LP DBG of fixed voltage + */ +#define EFUSE_DSLP_LP_DBG 0x00000003U +#define EFUSE_DSLP_LP_DBG_M (EFUSE_DSLP_LP_DBG_V << EFUSE_DSLP_LP_DBG_S) +#define EFUSE_DSLP_LP_DBG_V 0x00000003U +#define EFUSE_DSLP_LP_DBG_S 30 /** EFUSE_RD_MAC_SYS5_REG register * Represents rd_mac_sys */ #define EFUSE_RD_MAC_SYS5_REG (DR_REG_EFUSE_BASE + 0x64) -/** EFUSE_SYS_DATA_PART0_2 : RO; bitpos: [31:0]; default: 0; - * Represents the third 32-bit of zeroth part of system data. +/** EFUSE_DSLP_LP_DBG_1 : R; bitpos: [1:0]; default: 0; + * DSLP LP DBG of fixed voltage */ -#define EFUSE_SYS_DATA_PART0_2 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART0_2_M (EFUSE_SYS_DATA_PART0_2_V << EFUSE_SYS_DATA_PART0_2_S) -#define EFUSE_SYS_DATA_PART0_2_V 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART0_2_S 0 +#define EFUSE_DSLP_LP_DBG_1 0x00000003U +#define EFUSE_DSLP_LP_DBG_1_M (EFUSE_DSLP_LP_DBG_1_V << EFUSE_DSLP_LP_DBG_1_S) +#define EFUSE_DSLP_LP_DBG_1_V 0x00000003U +#define EFUSE_DSLP_LP_DBG_1_S 0 +/** EFUSE_DSLP_LP_DBIAS : R; bitpos: [6:2]; default: 0; + * DSLP LP DBIAS of fixed voltage + */ +#define EFUSE_DSLP_LP_DBIAS 0x0000001FU +#define EFUSE_DSLP_LP_DBIAS_M (EFUSE_DSLP_LP_DBIAS_V << EFUSE_DSLP_LP_DBIAS_S) +#define EFUSE_DSLP_LP_DBIAS_V 0x0000001FU +#define EFUSE_DSLP_LP_DBIAS_S 2 +/** EFUSE_LP_HP_DBIAS_VOL_GAP : R; bitpos: [11:7]; default: 0; + * DBIAS gap between LP and HP + */ +#define EFUSE_LP_HP_DBIAS_VOL_GAP 0x0000001FU +#define EFUSE_LP_HP_DBIAS_VOL_GAP_M (EFUSE_LP_HP_DBIAS_VOL_GAP_V << EFUSE_LP_HP_DBIAS_VOL_GAP_S) +#define EFUSE_LP_HP_DBIAS_VOL_GAP_V 0x0000001FU +#define EFUSE_LP_HP_DBIAS_VOL_GAP_S 7 +/** EFUSE_PVT_DBIAS : R; bitpos: [15:12]; default: 0; + * PVT DBIAS + */ +#define EFUSE_PVT_DBIAS 0x0000000FU +#define EFUSE_PVT_DBIAS_M (EFUSE_PVT_DBIAS_V << EFUSE_PVT_DBIAS_S) +#define EFUSE_PVT_DBIAS_V 0x0000000FU +#define EFUSE_PVT_DBIAS_S 12 +/** EFUSE_RESERVED_1_176 : R; bitpos: [31:16]; default: 0; + * reserved + * This field is only for internal debugging purposes. Do not use it in applications. + */ +#define EFUSE_RESERVED_1_176 0x0000FFFFU +#define EFUSE_RESERVED_1_176_M (EFUSE_RESERVED_1_176_V << EFUSE_RESERVED_1_176_S) +#define EFUSE_RESERVED_1_176_V 0x0000FFFFU +#define EFUSE_RESERVED_1_176_S 16 /** EFUSE_RD_SYS_PART1_DATA0_REG register * Represents rd_sys_part1_data0 @@ -1096,13 +1520,35 @@ extern "C" { * Represents rd_sys_part1_data4 */ #define EFUSE_RD_SYS_PART1_DATA4_REG (DR_REG_EFUSE_BASE + 0x78) -/** EFUSE_SYS_DATA_PART1_4 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of first part of system data. +/** EFUSE_TEMP_CALIBRATION : R; bitpos: [9:0]; default: 0; + * Temperature calibration */ -#define EFUSE_SYS_DATA_PART1_4 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART1_4_M (EFUSE_SYS_DATA_PART1_4_V << EFUSE_SYS_DATA_PART1_4_S) -#define EFUSE_SYS_DATA_PART1_4_V 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART1_4_S 0 +#define EFUSE_TEMP_CALIBRATION 0x000003FFU +#define EFUSE_TEMP_CALIBRATION_M (EFUSE_TEMP_CALIBRATION_V << EFUSE_TEMP_CALIBRATION_S) +#define EFUSE_TEMP_CALIBRATION_V 0x000003FFU +#define EFUSE_TEMP_CALIBRATION_S 0 +/** EFUSE_SPI_LDO_1V8_DREF : R; bitpos: [13:10]; default: 0; + * SPI LDO 1.8 V DREF + */ +#define EFUSE_SPI_LDO_1V8_DREF 0x0000000FU +#define EFUSE_SPI_LDO_1V8_DREF_M (EFUSE_SPI_LDO_1V8_DREF_V << EFUSE_SPI_LDO_1V8_DREF_S) +#define EFUSE_SPI_LDO_1V8_DREF_V 0x0000000FU +#define EFUSE_SPI_LDO_1V8_DREF_S 10 +/** EFUSE_SPI_LDO_1V8_MUL : R; bitpos: [16:14]; default: 0; + * SPI LDO 1.8 V multiplier + */ +#define EFUSE_SPI_LDO_1V8_MUL 0x00000007U +#define EFUSE_SPI_LDO_1V8_MUL_M (EFUSE_SPI_LDO_1V8_MUL_V << EFUSE_SPI_LDO_1V8_MUL_S) +#define EFUSE_SPI_LDO_1V8_MUL_V 0x00000007U +#define EFUSE_SPI_LDO_1V8_MUL_S 14 +/** EFUSE_RESERVED_2_145 : R; bitpos: [31:17]; default: 0; + * reserved + * This field is only for internal debugging purposes. Do not use it in applications. + */ +#define EFUSE_RESERVED_2_145 0x00007FFFU +#define EFUSE_RESERVED_2_145_M (EFUSE_RESERVED_2_145_V << EFUSE_RESERVED_2_145_S) +#define EFUSE_RESERVED_2_145_V 0x00007FFFU +#define EFUSE_RESERVED_2_145_S 17 /** EFUSE_RD_SYS_PART1_DATA5_REG register * Represents rd_sys_part1_data5 @@ -1110,6 +1556,7 @@ extern "C" { #define EFUSE_RD_SYS_PART1_DATA5_REG (DR_REG_EFUSE_BASE + 0x7c) /** EFUSE_SYS_DATA_PART1_5 : RO; bitpos: [31:0]; default: 0; * Represents the zeroth 32-bit of first part of system data. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define EFUSE_SYS_DATA_PART1_5 0xFFFFFFFFU #define EFUSE_SYS_DATA_PART1_5_M (EFUSE_SYS_DATA_PART1_5_V << EFUSE_SYS_DATA_PART1_5_S) @@ -1122,6 +1569,7 @@ extern "C" { #define EFUSE_RD_SYS_PART1_DATA6_REG (DR_REG_EFUSE_BASE + 0x80) /** EFUSE_SYS_DATA_PART1_6 : RO; bitpos: [31:0]; default: 0; * Represents the zeroth 32-bit of first part of system data. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define EFUSE_SYS_DATA_PART1_6 0xFFFFFFFFU #define EFUSE_SYS_DATA_PART1_6_M (EFUSE_SYS_DATA_PART1_6_V << EFUSE_SYS_DATA_PART1_6_S) @@ -1134,6 +1582,7 @@ extern "C" { #define EFUSE_RD_SYS_PART1_DATA7_REG (DR_REG_EFUSE_BASE + 0x84) /** EFUSE_SYS_DATA_PART1_7 : RO; bitpos: [31:0]; default: 0; * Represents the zeroth 32-bit of first part of system data. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define EFUSE_SYS_DATA_PART1_7 0xFFFFFFFFU #define EFUSE_SYS_DATA_PART1_7_M (EFUSE_SYS_DATA_PART1_7_V << EFUSE_SYS_DATA_PART1_7_S) @@ -1218,6 +1667,7 @@ extern "C" { #define EFUSE_RD_USR_DATA6_REG (DR_REG_EFUSE_BASE + 0xa0) /** EFUSE_RESERVED_3_192 : R; bitpos: [7:0]; default: 0; * reserved + * This field is only for internal debugging purposes. Do not use it in applications. */ #define EFUSE_RESERVED_3_192 0x000000FFU #define EFUSE_RESERVED_3_192_M (EFUSE_RESERVED_3_192_V << EFUSE_RESERVED_3_192_S) @@ -1244,6 +1694,7 @@ extern "C" { #define EFUSE_CUSTOM_MAC_1_S 0 /** EFUSE_RESERVED_3_248 : R; bitpos: [31:24]; default: 0; * reserved + * This field is only for internal debugging purposes. Do not use it in applications. */ #define EFUSE_RESERVED_3_248 0x000000FFU #define EFUSE_RESERVED_3_248_M (EFUSE_RESERVED_3_248_V << EFUSE_RESERVED_3_248_S) @@ -1734,49 +2185,127 @@ extern "C" { * Represents rd_sys_part2_data */ #define EFUSE_RD_SYS_PART2_DATA0_REG (DR_REG_EFUSE_BASE + 0x148) -/** EFUSE_SYS_DATA_PART2_0 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of second part of system data. +/** EFUSE_ADC1_DIFF_K : R; bitpos: [10:0]; default: 0; + * Fitted slope (K) of ADC1 in differential mode */ -#define EFUSE_SYS_DATA_PART2_0 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART2_0_M (EFUSE_SYS_DATA_PART2_0_V << EFUSE_SYS_DATA_PART2_0_S) -#define EFUSE_SYS_DATA_PART2_0_V 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART2_0_S 0 +#define EFUSE_ADC1_DIFF_K 0x000007FFU +#define EFUSE_ADC1_DIFF_K_M (EFUSE_ADC1_DIFF_K_V << EFUSE_ADC1_DIFF_K_S) +#define EFUSE_ADC1_DIFF_K_V 0x000007FFU +#define EFUSE_ADC1_DIFF_K_S 0 +/** EFUSE_ADC1_DIFF_B : R; bitpos: [20:11]; default: 0; + * Intercept (B) of ADC1 in differential mode + */ +#define EFUSE_ADC1_DIFF_B 0x000003FFU +#define EFUSE_ADC1_DIFF_B_M (EFUSE_ADC1_DIFF_B_V << EFUSE_ADC1_DIFF_B_S) +#define EFUSE_ADC1_DIFF_B_V 0x000003FFU +#define EFUSE_ADC1_DIFF_B_S 11 +/** EFUSE_ADC1_P_K : R; bitpos: [31:21]; default: 0; + * Fitted slope (K) of ADC1 in P mode + */ +#define EFUSE_ADC1_P_K 0x000007FFU +#define EFUSE_ADC1_P_K_M (EFUSE_ADC1_P_K_V << EFUSE_ADC1_P_K_S) +#define EFUSE_ADC1_P_K_V 0x000007FFU +#define EFUSE_ADC1_P_K_S 21 /** EFUSE_RD_SYS_PART2_DATA1_REG register * Represents rd_sys_part2_data */ #define EFUSE_RD_SYS_PART2_DATA1_REG (DR_REG_EFUSE_BASE + 0x14c) -/** EFUSE_SYS_DATA_PART2_1 : RO; bitpos: [31:0]; default: 0; - * Represents the first 32-bit of second part of system data. +/** EFUSE_ADC1_P_B : R; bitpos: [9:0]; default: 0; + * Intercept (B) of ADC1 in P mode */ -#define EFUSE_SYS_DATA_PART2_1 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART2_1_M (EFUSE_SYS_DATA_PART2_1_V << EFUSE_SYS_DATA_PART2_1_S) -#define EFUSE_SYS_DATA_PART2_1_V 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART2_1_S 0 +#define EFUSE_ADC1_P_B 0x000003FFU +#define EFUSE_ADC1_P_B_M (EFUSE_ADC1_P_B_V << EFUSE_ADC1_P_B_S) +#define EFUSE_ADC1_P_B_V 0x000003FFU +#define EFUSE_ADC1_P_B_S 0 +/** EFUSE_ADC1_N_K : R; bitpos: [20:10]; default: 0; + * Fitted slope (K) of ADC1 in N mode + */ +#define EFUSE_ADC1_N_K 0x000007FFU +#define EFUSE_ADC1_N_K_M (EFUSE_ADC1_N_K_V << EFUSE_ADC1_N_K_S) +#define EFUSE_ADC1_N_K_V 0x000007FFU +#define EFUSE_ADC1_N_K_S 10 +/** EFUSE_ADC1_N_B : R; bitpos: [30:21]; default: 0; + * Intercept (B) of ADC1 in N mode + */ +#define EFUSE_ADC1_N_B 0x000003FFU +#define EFUSE_ADC1_N_B_M (EFUSE_ADC1_N_B_V << EFUSE_ADC1_N_B_S) +#define EFUSE_ADC1_N_B_V 0x000003FFU +#define EFUSE_ADC1_N_B_S 21 +/** EFUSE_ADC2_DIFF_K : R; bitpos: [31]; default: 0; + * Fitted slope (K) of ADC2 in differential mode + */ +#define EFUSE_ADC2_DIFF_K (BIT(31)) +#define EFUSE_ADC2_DIFF_K_M (EFUSE_ADC2_DIFF_K_V << EFUSE_ADC2_DIFF_K_S) +#define EFUSE_ADC2_DIFF_K_V 0x00000001U +#define EFUSE_ADC2_DIFF_K_S 31 /** EFUSE_RD_SYS_PART2_DATA2_REG register * Represents rd_sys_part2_data */ #define EFUSE_RD_SYS_PART2_DATA2_REG (DR_REG_EFUSE_BASE + 0x150) -/** EFUSE_SYS_DATA_PART2_2 : RO; bitpos: [31:0]; default: 0; - * Represents the second 32-bit of second part of system data. +/** EFUSE_ADC2_DIFF_K_1 : R; bitpos: [9:0]; default: 0; + * Fitted slope (K) of ADC2 in differential mode */ -#define EFUSE_SYS_DATA_PART2_2 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART2_2_M (EFUSE_SYS_DATA_PART2_2_V << EFUSE_SYS_DATA_PART2_2_S) -#define EFUSE_SYS_DATA_PART2_2_V 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART2_2_S 0 +#define EFUSE_ADC2_DIFF_K_1 0x000003FFU +#define EFUSE_ADC2_DIFF_K_1_M (EFUSE_ADC2_DIFF_K_1_V << EFUSE_ADC2_DIFF_K_1_S) +#define EFUSE_ADC2_DIFF_K_1_V 0x000003FFU +#define EFUSE_ADC2_DIFF_K_1_S 0 +/** EFUSE_ADC2_DIFF_B : R; bitpos: [19:10]; default: 0; + * Intercept (B) of ADC2 in differential mode + */ +#define EFUSE_ADC2_DIFF_B 0x000003FFU +#define EFUSE_ADC2_DIFF_B_M (EFUSE_ADC2_DIFF_B_V << EFUSE_ADC2_DIFF_B_S) +#define EFUSE_ADC2_DIFF_B_V 0x000003FFU +#define EFUSE_ADC2_DIFF_B_S 10 +/** EFUSE_ADC2_P_K : R; bitpos: [30:20]; default: 0; + * Fitted slope (K) of ADC2 in P mode + */ +#define EFUSE_ADC2_P_K 0x000007FFU +#define EFUSE_ADC2_P_K_M (EFUSE_ADC2_P_K_V << EFUSE_ADC2_P_K_S) +#define EFUSE_ADC2_P_K_V 0x000007FFU +#define EFUSE_ADC2_P_K_S 20 +/** EFUSE_ADC2_P_B : R; bitpos: [31]; default: 0; + * Intercept (B) of ADC2 in P mode + */ +#define EFUSE_ADC2_P_B (BIT(31)) +#define EFUSE_ADC2_P_B_M (EFUSE_ADC2_P_B_V << EFUSE_ADC2_P_B_S) +#define EFUSE_ADC2_P_B_V 0x00000001U +#define EFUSE_ADC2_P_B_S 31 /** EFUSE_RD_SYS_PART2_DATA3_REG register * Represents rd_sys_part2_data */ #define EFUSE_RD_SYS_PART2_DATA3_REG (DR_REG_EFUSE_BASE + 0x154) -/** EFUSE_SYS_DATA_PART2_3 : RO; bitpos: [31:0]; default: 0; - * Represents the third 32-bit of second part of system data. +/** EFUSE_ADC2_P_B_1 : R; bitpos: [8:0]; default: 0; + * Intercept (B) of ADC2 in P mode */ -#define EFUSE_SYS_DATA_PART2_3 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART2_3_M (EFUSE_SYS_DATA_PART2_3_V << EFUSE_SYS_DATA_PART2_3_S) -#define EFUSE_SYS_DATA_PART2_3_V 0xFFFFFFFFU -#define EFUSE_SYS_DATA_PART2_3_S 0 +#define EFUSE_ADC2_P_B_1 0x000001FFU +#define EFUSE_ADC2_P_B_1_M (EFUSE_ADC2_P_B_1_V << EFUSE_ADC2_P_B_1_S) +#define EFUSE_ADC2_P_B_1_V 0x000001FFU +#define EFUSE_ADC2_P_B_1_S 0 +/** EFUSE_ADC2_N_K : R; bitpos: [19:9]; default: 0; + * Fitted slope (K) of ADC2 in N mode + */ +#define EFUSE_ADC2_N_K 0x000007FFU +#define EFUSE_ADC2_N_K_M (EFUSE_ADC2_N_K_V << EFUSE_ADC2_N_K_S) +#define EFUSE_ADC2_N_K_V 0x000007FFU +#define EFUSE_ADC2_N_K_S 9 +/** EFUSE_ADC2_N_B : R; bitpos: [29:20]; default: 0; + * Intercept (B) of ADC2 in N mode + */ +#define EFUSE_ADC2_N_B 0x000003FFU +#define EFUSE_ADC2_N_B_M (EFUSE_ADC2_N_B_V << EFUSE_ADC2_N_B_S) +#define EFUSE_ADC2_N_B_V 0x000003FFU +#define EFUSE_ADC2_N_B_S 20 +/** EFUSE_RESERVED_9_126 : R; bitpos: [31:30]; default: 0; + * reserved + * This field is only for internal debugging purposes. Do not use it in applications. + */ +#define EFUSE_RESERVED_9_126 0x00000003U +#define EFUSE_RESERVED_9_126_M (EFUSE_RESERVED_9_126_V << EFUSE_RESERVED_9_126_S) +#define EFUSE_RESERVED_9_126_V 0x00000003U +#define EFUSE_RESERVED_9_126_S 30 /** EFUSE_RD_SYS_PART2_DATA4_REG register * Represents rd_sys_part2_data @@ -1784,6 +2313,7 @@ extern "C" { #define EFUSE_RD_SYS_PART2_DATA4_REG (DR_REG_EFUSE_BASE + 0x158) /** EFUSE_SYS_DATA_PART2_4 : RO; bitpos: [31:0]; default: 0; * Represents the fourth 32-bit of second part of system data. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define EFUSE_SYS_DATA_PART2_4 0xFFFFFFFFU #define EFUSE_SYS_DATA_PART2_4_M (EFUSE_SYS_DATA_PART2_4_V << EFUSE_SYS_DATA_PART2_4_S) @@ -1796,6 +2326,7 @@ extern "C" { #define EFUSE_RD_SYS_PART2_DATA5_REG (DR_REG_EFUSE_BASE + 0x15c) /** EFUSE_SYS_DATA_PART2_5 : RO; bitpos: [31:0]; default: 0; * Represents the fifth 32-bit of second part of system data. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define EFUSE_SYS_DATA_PART2_5 0xFFFFFFFFU #define EFUSE_SYS_DATA_PART2_5_M (EFUSE_SYS_DATA_PART2_5_V << EFUSE_SYS_DATA_PART2_5_S) @@ -1807,8 +2338,9 @@ extern "C" { */ #define EFUSE_RD_SYS_PART2_DATA6_REG (DR_REG_EFUSE_BASE + 0x160) /** EFUSE_USB_DEVICE_EXCHG_PINS : RO; bitpos: [0]; default: 0; - * Represents whether enable usb device exchange pins of D+ and D- or not. \\ 1: - * enabled\\ 0: disabled\\ + * Represents whether enable usb device exchange pins of D+ and D- or not. + * 1: enabled + * 0: disabled */ #define EFUSE_USB_DEVICE_EXCHG_PINS (BIT(0)) #define EFUSE_USB_DEVICE_EXCHG_PINS_M (EFUSE_USB_DEVICE_EXCHG_PINS_V << EFUSE_USB_DEVICE_EXCHG_PINS_S) @@ -1816,6 +2348,7 @@ extern "C" { #define EFUSE_USB_DEVICE_EXCHG_PINS_S 0 /** EFUSE_USB_DEVICE_DREFH : RO; bitpos: [2:1]; default: 0; * Represents the single-end input threshold vrefh, 1.76 V to 2 V with step of 80 mV. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define EFUSE_USB_DEVICE_DREFH 0x00000003U #define EFUSE_USB_DEVICE_DREFH_M (EFUSE_USB_DEVICE_DREFH_V << EFUSE_USB_DEVICE_DREFH_S) @@ -1824,20 +2357,23 @@ extern "C" { /** EFUSE_USB_DEVICE_DREFL : RO; bitpos: [4:3]; default: 0; * Represents the usb device single-end input low threshold, 0.8 V to 1.04 V with step * of 80 mV. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define EFUSE_USB_DEVICE_DREFL 0x00000003U #define EFUSE_USB_DEVICE_DREFL_M (EFUSE_USB_DEVICE_DREFL_V << EFUSE_USB_DEVICE_DREFL_S) #define EFUSE_USB_DEVICE_DREFL_V 0x00000003U #define EFUSE_USB_DEVICE_DREFL_S 3 -/** EFUSE_RD_RESERVE_9_197 : RW; bitpos: [16:5]; default: 0; - * Reserved, it was created by set_missed_fields_in_regs func +/** EFUSE_RESERVED_9_197 : R; bitpos: [16:5]; default: 0; + * reserved + * This field is only for internal debugging purposes. Do not use it in applications. */ -#define EFUSE_RD_RESERVE_9_197 0x00000FFFU -#define EFUSE_RD_RESERVE_9_197_M (EFUSE_RD_RESERVE_9_197_V << EFUSE_RD_RESERVE_9_197_S) -#define EFUSE_RD_RESERVE_9_197_V 0x00000FFFU -#define EFUSE_RD_RESERVE_9_197_S 5 +#define EFUSE_RESERVED_9_197 0x00000FFFU +#define EFUSE_RESERVED_9_197_M (EFUSE_RESERVED_9_197_V << EFUSE_RESERVED_9_197_S) +#define EFUSE_RESERVED_9_197_V 0x00000FFFU +#define EFUSE_RESERVED_9_197_S 5 /** EFUSE_PVT_0_CELL_SELECT : RO; bitpos: [23:17]; default: 0; * Power glitch monitor PVT cell select. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define EFUSE_PVT_0_CELL_SELECT 0x0000007FU #define EFUSE_PVT_0_CELL_SELECT_M (EFUSE_PVT_0_CELL_SELECT_V << EFUSE_PVT_0_CELL_SELECT_S) @@ -1845,25 +2381,30 @@ extern "C" { #define EFUSE_PVT_0_CELL_SELECT_S 17 /** EFUSE_PVT_1_CELL_SELECT : RO; bitpos: [30:24]; default: 0; * Power glitch monitor PVT cell select. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define EFUSE_PVT_1_CELL_SELECT 0x0000007FU #define EFUSE_PVT_1_CELL_SELECT_M (EFUSE_PVT_1_CELL_SELECT_V << EFUSE_PVT_1_CELL_SELECT_S) #define EFUSE_PVT_1_CELL_SELECT_V 0x0000007FU #define EFUSE_PVT_1_CELL_SELECT_S 24 -/** EFUSE_RD_RESERVE_9_223 : RW; bitpos: [31]; default: 0; - * Reserved, it was created by set_missed_fields_in_regs func +/** EFUSE_RESERVED_9_223 : R; bitpos: [31]; default: 0; + * reserved + * This field is only for internal debugging purposes. Do not use it in applications. */ -#define EFUSE_RD_RESERVE_9_223 (BIT(31)) -#define EFUSE_RD_RESERVE_9_223_M (EFUSE_RD_RESERVE_9_223_V << EFUSE_RD_RESERVE_9_223_S) -#define EFUSE_RD_RESERVE_9_223_V 0x00000001U -#define EFUSE_RD_RESERVE_9_223_S 31 +#define EFUSE_RESERVED_9_223 (BIT(31)) +#define EFUSE_RESERVED_9_223_M (EFUSE_RESERVED_9_223_V << EFUSE_RESERVED_9_223_S) +#define EFUSE_RESERVED_9_223_V 0x00000001U +#define EFUSE_RESERVED_9_223_S 31 /** EFUSE_RD_SYS_PART2_DATA7_REG register * Represents rd_sys_part2_data + * This register is only for internal debugging purposes. Do not use it in + * applications. */ #define EFUSE_RD_SYS_PART2_DATA7_REG (DR_REG_EFUSE_BASE + 0x164) /** EFUSE_PVT_0_LIMIT : RO; bitpos: [15:0]; default: 0; * Power glitch monitor threthold. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define EFUSE_PVT_0_LIMIT 0x0000FFFFU #define EFUSE_PVT_0_LIMIT_M (EFUSE_PVT_0_LIMIT_V << EFUSE_PVT_0_LIMIT_S) @@ -1871,6 +2412,7 @@ extern "C" { #define EFUSE_PVT_0_LIMIT_S 0 /** EFUSE_PVT_1_LIMIT : RO; bitpos: [31:16]; default: 0; * Power glitch monitor threthold. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define EFUSE_PVT_1_LIMIT 0x0000FFFFU #define EFUSE_PVT_1_LIMIT_M (EFUSE_PVT_1_LIMIT_V << EFUSE_PVT_1_LIMIT_S) @@ -1897,6 +2439,7 @@ extern "C" { #define EFUSE_DIS_USB_JTAG_ERR_S 10 /** EFUSE_DIS_USB_SERIAL_JTAG_ERR : RO; bitpos: [11]; default: 0; * Represents the programming error of EFUSE_DIS_USB_SERIAL_JTAG + * This field is only for internal debugging purposes. Do not use it in applications. */ #define EFUSE_DIS_USB_SERIAL_JTAG_ERR (BIT(11)) #define EFUSE_DIS_USB_SERIAL_JTAG_ERR_M (EFUSE_DIS_USB_SERIAL_JTAG_ERR_V << EFUSE_DIS_USB_SERIAL_JTAG_ERR_S) @@ -1953,6 +2496,7 @@ extern "C" { #define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_S 20 /** EFUSE_DIS_WIFI6_ERR : RO; bitpos: [22]; default: 0; * Represents the programming error of EFUSE_DIS_WIFI6 + * This field is only for internal debugging purposes. Do not use it in applications. */ #define EFUSE_DIS_WIFI6_ERR (BIT(22)) #define EFUSE_DIS_WIFI6_ERR_M (EFUSE_DIS_WIFI6_ERR_V << EFUSE_DIS_WIFI6_ERR_S) @@ -2440,136 +2984,143 @@ extern "C" { */ #define EFUSE_RD_RS_DATA_ERR0_REG (DR_REG_EFUSE_BASE + 0x188) /** EFUSE_RD_MAC_SYS_ERR_NUM : RO; bitpos: [2:0]; default: 0; - * Represents the error number of registers.\\The value of this signal means the - * number of error bytes in rd_mac_sys + * Represents the error number of registers. + * The value of this signal means the number of error bytes in rd_mac_sys */ #define EFUSE_RD_MAC_SYS_ERR_NUM 0x00000007U #define EFUSE_RD_MAC_SYS_ERR_NUM_M (EFUSE_RD_MAC_SYS_ERR_NUM_V << EFUSE_RD_MAC_SYS_ERR_NUM_S) #define EFUSE_RD_MAC_SYS_ERR_NUM_V 0x00000007U #define EFUSE_RD_MAC_SYS_ERR_NUM_S 0 /** EFUSE_RD_MAC_SYS_FAIL : RO; bitpos: [3]; default: 0; - * Represents error status of register.\\0: Means no failure and that the data of - * rd_mac_sys is reliable\\ 1: Means that programming rd_mac_sys failed and the number - * of error bytes is over 6. + * Represents error status of register. + * 0: Means no failure and that the data of rd_mac_sys is reliable + * 1: Means that programming rd_mac_sys failed and the number of error bytes is over 6. */ #define EFUSE_RD_MAC_SYS_FAIL (BIT(3)) #define EFUSE_RD_MAC_SYS_FAIL_M (EFUSE_RD_MAC_SYS_FAIL_V << EFUSE_RD_MAC_SYS_FAIL_S) #define EFUSE_RD_MAC_SYS_FAIL_V 0x00000001U #define EFUSE_RD_MAC_SYS_FAIL_S 3 /** EFUSE_RD_SYS_PART1_DATA_ERR_NUM : RO; bitpos: [6:4]; default: 0; - * Represents the error number of registers.\\The value of this signal means the - * number of error bytes in rd_sys_part1_data + * Represents the error number of registers. + * The value of this signal means the number of error bytes in rd_sys_part1_data */ #define EFUSE_RD_SYS_PART1_DATA_ERR_NUM 0x00000007U #define EFUSE_RD_SYS_PART1_DATA_ERR_NUM_M (EFUSE_RD_SYS_PART1_DATA_ERR_NUM_V << EFUSE_RD_SYS_PART1_DATA_ERR_NUM_S) #define EFUSE_RD_SYS_PART1_DATA_ERR_NUM_V 0x00000007U #define EFUSE_RD_SYS_PART1_DATA_ERR_NUM_S 4 /** EFUSE_RD_SYS_PART1_DATA_FAIL : RO; bitpos: [7]; default: 0; - * Represents error status of register.\\0: Means no failure and that the data of - * rd_sys_part1_data is reliable\\ 1: Means that programming rd_sys_part1_data failed - * and the number of error bytes is over 6. + * Represents error status of register. + * 0: Means no failure and that the data of rd_sys_part1_data is reliable + * 1: Means that programming rd_sys_part1_data failed and the number of error bytes is + * over 6. */ #define EFUSE_RD_SYS_PART1_DATA_FAIL (BIT(7)) #define EFUSE_RD_SYS_PART1_DATA_FAIL_M (EFUSE_RD_SYS_PART1_DATA_FAIL_V << EFUSE_RD_SYS_PART1_DATA_FAIL_S) #define EFUSE_RD_SYS_PART1_DATA_FAIL_V 0x00000001U #define EFUSE_RD_SYS_PART1_DATA_FAIL_S 7 /** EFUSE_RD_USR_DATA_ERR_NUM : RO; bitpos: [10:8]; default: 0; - * Represents the error number of registers.\\The value of this signal means the - * number of error bytes in rd_usr_data + * Represents the error number of registers. + * The value of this signal means the number of error bytes in rd_usr_data */ #define EFUSE_RD_USR_DATA_ERR_NUM 0x00000007U #define EFUSE_RD_USR_DATA_ERR_NUM_M (EFUSE_RD_USR_DATA_ERR_NUM_V << EFUSE_RD_USR_DATA_ERR_NUM_S) #define EFUSE_RD_USR_DATA_ERR_NUM_V 0x00000007U #define EFUSE_RD_USR_DATA_ERR_NUM_S 8 /** EFUSE_RD_USR_DATA_FAIL : RO; bitpos: [11]; default: 0; - * Represents error status of register.\\0: Means no failure and that the data of - * rd_usr_data is reliable\\ 1: Means that programming rd_usr_data failed and the - * number of error bytes is over 6. + * Represents error status of register. + * 0: Means no failure and that the data of rd_usr_data is reliable + * 1: Means that programming rd_usr_data failed and the number of error bytes is over + * 6. */ #define EFUSE_RD_USR_DATA_FAIL (BIT(11)) #define EFUSE_RD_USR_DATA_FAIL_M (EFUSE_RD_USR_DATA_FAIL_V << EFUSE_RD_USR_DATA_FAIL_S) #define EFUSE_RD_USR_DATA_FAIL_V 0x00000001U #define EFUSE_RD_USR_DATA_FAIL_S 11 /** EFUSE_RD_KEY0_DATA_ERR_NUM : RO; bitpos: [14:12]; default: 0; - * Represents the error number of registers.\\The value of this signal means the - * number of error bytes in rd_key0_data + * Represents the error number of registers. + * The value of this signal means the number of error bytes in rd_key0_data */ #define EFUSE_RD_KEY0_DATA_ERR_NUM 0x00000007U #define EFUSE_RD_KEY0_DATA_ERR_NUM_M (EFUSE_RD_KEY0_DATA_ERR_NUM_V << EFUSE_RD_KEY0_DATA_ERR_NUM_S) #define EFUSE_RD_KEY0_DATA_ERR_NUM_V 0x00000007U #define EFUSE_RD_KEY0_DATA_ERR_NUM_S 12 /** EFUSE_RD_KEY0_DATA_FAIL : RO; bitpos: [15]; default: 0; - * Represents error status of register.\\0: Means no failure and that the data of - * rd_key0_data is reliable\\ 1: Means that programming rd_key0_data failed and the - * number of error bytes is over 6. + * Represents error status of register. + * 0: Means no failure and that the data of rd_key0_data is reliable + * 1: Means that programming rd_key0_data failed and the number of error bytes is over + * 6. */ #define EFUSE_RD_KEY0_DATA_FAIL (BIT(15)) #define EFUSE_RD_KEY0_DATA_FAIL_M (EFUSE_RD_KEY0_DATA_FAIL_V << EFUSE_RD_KEY0_DATA_FAIL_S) #define EFUSE_RD_KEY0_DATA_FAIL_V 0x00000001U #define EFUSE_RD_KEY0_DATA_FAIL_S 15 /** EFUSE_RD_KEY1_DATA_ERR_NUM : RO; bitpos: [18:16]; default: 0; - * Represents the error number of registers.\\The value of this signal means the - * number of error bytes in rd_key1_data + * Represents the error number of registers. + * The value of this signal means the number of error bytes in rd_key1_data */ #define EFUSE_RD_KEY1_DATA_ERR_NUM 0x00000007U #define EFUSE_RD_KEY1_DATA_ERR_NUM_M (EFUSE_RD_KEY1_DATA_ERR_NUM_V << EFUSE_RD_KEY1_DATA_ERR_NUM_S) #define EFUSE_RD_KEY1_DATA_ERR_NUM_V 0x00000007U #define EFUSE_RD_KEY1_DATA_ERR_NUM_S 16 /** EFUSE_RD_KEY1_DATA_FAIL : RO; bitpos: [19]; default: 0; - * Represents error status of register.\\0: Means no failure and that the data of - * rd_key1_data is reliable\\ 1: Means that programming rd_key1_data failed and the - * number of error bytes is over 6. + * Represents error status of register. + * 0: Means no failure and that the data of rd_key1_data is reliable + * 1: Means that programming rd_key1_data failed and the number of error bytes is over + * 6. */ #define EFUSE_RD_KEY1_DATA_FAIL (BIT(19)) #define EFUSE_RD_KEY1_DATA_FAIL_M (EFUSE_RD_KEY1_DATA_FAIL_V << EFUSE_RD_KEY1_DATA_FAIL_S) #define EFUSE_RD_KEY1_DATA_FAIL_V 0x00000001U #define EFUSE_RD_KEY1_DATA_FAIL_S 19 /** EFUSE_RD_KEY2_DATA_ERR_NUM : RO; bitpos: [22:20]; default: 0; - * Represents the error number of registers.\\The value of this signal means the - * number of error bytes in rd_key2_data + * Represents the error number of registers. + * The value of this signal means the number of error bytes in rd_key2_data */ #define EFUSE_RD_KEY2_DATA_ERR_NUM 0x00000007U #define EFUSE_RD_KEY2_DATA_ERR_NUM_M (EFUSE_RD_KEY2_DATA_ERR_NUM_V << EFUSE_RD_KEY2_DATA_ERR_NUM_S) #define EFUSE_RD_KEY2_DATA_ERR_NUM_V 0x00000007U #define EFUSE_RD_KEY2_DATA_ERR_NUM_S 20 /** EFUSE_RD_KEY2_DATA_FAIL : RO; bitpos: [23]; default: 0; - * Represents error status of register.\\0: Means no failure and that the data of - * rd_key2_data is reliable\\ 1: Means that programming rd_key2_data failed and the - * number of error bytes is over 6. + * Represents error status of register. + * 0: Means no failure and that the data of rd_key2_data is reliable + * 1: Means that programming rd_key2_data failed and the number of error bytes is over + * 6. */ #define EFUSE_RD_KEY2_DATA_FAIL (BIT(23)) #define EFUSE_RD_KEY2_DATA_FAIL_M (EFUSE_RD_KEY2_DATA_FAIL_V << EFUSE_RD_KEY2_DATA_FAIL_S) #define EFUSE_RD_KEY2_DATA_FAIL_V 0x00000001U #define EFUSE_RD_KEY2_DATA_FAIL_S 23 /** EFUSE_RD_KEY3_DATA_ERR_NUM : RO; bitpos: [26:24]; default: 0; - * Represents the error number of registers.\\The value of this signal means the - * number of error bytes in rd_key3_data + * Represents the error number of registers. + * The value of this signal means the number of error bytes in rd_key3_data */ #define EFUSE_RD_KEY3_DATA_ERR_NUM 0x00000007U #define EFUSE_RD_KEY3_DATA_ERR_NUM_M (EFUSE_RD_KEY3_DATA_ERR_NUM_V << EFUSE_RD_KEY3_DATA_ERR_NUM_S) #define EFUSE_RD_KEY3_DATA_ERR_NUM_V 0x00000007U #define EFUSE_RD_KEY3_DATA_ERR_NUM_S 24 /** EFUSE_RD_KEY3_DATA_FAIL : RO; bitpos: [27]; default: 0; - * Represents error status of register.\\0: Means no failure and that the data of - * rd_key3_data is reliable\\ 1: Means that programming rd_key3_data failed and the - * number of error bytes is over 6. + * Represents error status of register. + * 0: Means no failure and that the data of rd_key3_data is reliable + * 1: Means that programming rd_key3_data failed and the number of error bytes is over + * 6. */ #define EFUSE_RD_KEY3_DATA_FAIL (BIT(27)) #define EFUSE_RD_KEY3_DATA_FAIL_M (EFUSE_RD_KEY3_DATA_FAIL_V << EFUSE_RD_KEY3_DATA_FAIL_S) #define EFUSE_RD_KEY3_DATA_FAIL_V 0x00000001U #define EFUSE_RD_KEY3_DATA_FAIL_S 27 /** EFUSE_RD_KEY4_DATA_ERR_NUM : RO; bitpos: [30:28]; default: 0; - * Represents the error number of registers.\\The value of this signal means the - * number of error bytes in rd_key4_data + * Represents the error number of registers. + * The value of this signal means the number of error bytes in rd_key4_data */ #define EFUSE_RD_KEY4_DATA_ERR_NUM 0x00000007U #define EFUSE_RD_KEY4_DATA_ERR_NUM_M (EFUSE_RD_KEY4_DATA_ERR_NUM_V << EFUSE_RD_KEY4_DATA_ERR_NUM_S) #define EFUSE_RD_KEY4_DATA_ERR_NUM_V 0x00000007U #define EFUSE_RD_KEY4_DATA_ERR_NUM_S 28 /** EFUSE_RD_KEY4_DATA_FAIL : RO; bitpos: [31]; default: 0; - * Represents error status of register.\\0: Means no failure and that the data of - * rd_key4_data is reliable\\ 1: Means that programming rd_key4_data failed and the - * number of error bytes is over 6. + * Represents error status of register. + * 0: Means no failure and that the data of rd_key4_data is reliable + * 1: Means that programming rd_key4_data failed and the number of error bytes is over + * 6. */ #define EFUSE_RD_KEY4_DATA_FAIL (BIT(31)) #define EFUSE_RD_KEY4_DATA_FAIL_M (EFUSE_RD_KEY4_DATA_FAIL_V << EFUSE_RD_KEY4_DATA_FAIL_S) @@ -2581,17 +3132,18 @@ extern "C" { */ #define EFUSE_RD_RS_DATA_ERR1_REG (DR_REG_EFUSE_BASE + 0x18c) /** EFUSE_RD_SYS_PART2_DATA_ERR_NUM : RO; bitpos: [2:0]; default: 0; - * Represents the error number of registers.\\The value of this signal means the - * number of error bytes in rd_sys_part2_data + * Represents the error number of registers. + * The value of this signal means the number of error bytes in rd_sys_part2_data */ #define EFUSE_RD_SYS_PART2_DATA_ERR_NUM 0x00000007U #define EFUSE_RD_SYS_PART2_DATA_ERR_NUM_M (EFUSE_RD_SYS_PART2_DATA_ERR_NUM_V << EFUSE_RD_SYS_PART2_DATA_ERR_NUM_S) #define EFUSE_RD_SYS_PART2_DATA_ERR_NUM_V 0x00000007U #define EFUSE_RD_SYS_PART2_DATA_ERR_NUM_S 0 /** EFUSE_RD_SYS_PART2_DATA_FAIL : RO; bitpos: [3]; default: 0; - * Represents error status of register.\\0: Means no failure and that the data of - * rd_sys_part2_data is reliable\\ 1: Means that programming rd_sys_part2_data failed - * and the number of error bytes is over 6. + * Represents error status of register. + * 0: Means no failure and that the data of rd_sys_part2_data is reliable + * 1: Means that programming rd_sys_part2_data failed and the number of error bytes is + * over 6. */ #define EFUSE_RD_SYS_PART2_DATA_FAIL (BIT(3)) #define EFUSE_RD_SYS_PART2_DATA_FAIL_M (EFUSE_RD_SYS_PART2_DATA_FAIL_V << EFUSE_RD_SYS_PART2_DATA_FAIL_S) @@ -2616,30 +3168,36 @@ extern "C" { */ #define EFUSE_CLK_REG (DR_REG_EFUSE_BASE + 0x1c8) /** EFUSE_MEM_FORCE_PD : R/W; bitpos: [0]; default: 0; - * Configures whether to force power down eFuse SRAM.\\ 1: Force\\ 0: No effect\\ + * Configures whether to force power down eFuse SRAM. + * 1: Force + * 0: No effect */ #define EFUSE_MEM_FORCE_PD (BIT(0)) #define EFUSE_MEM_FORCE_PD_M (EFUSE_MEM_FORCE_PD_V << EFUSE_MEM_FORCE_PD_S) #define EFUSE_MEM_FORCE_PD_V 0x00000001U #define EFUSE_MEM_FORCE_PD_S 0 /** EFUSE_MEM_CLK_FORCE_ON : R/W; bitpos: [1]; default: 1; - * Configures whether to force activate clock signal of eFuse SRAM.\\ 1: Force - * activate\\ 0: No effect\\ + * Configures whether to force activate clock signal of eFuse SRAM. + * 1: Force activate + * 0: No effect */ #define EFUSE_MEM_CLK_FORCE_ON (BIT(1)) #define EFUSE_MEM_CLK_FORCE_ON_M (EFUSE_MEM_CLK_FORCE_ON_V << EFUSE_MEM_CLK_FORCE_ON_S) #define EFUSE_MEM_CLK_FORCE_ON_V 0x00000001U #define EFUSE_MEM_CLK_FORCE_ON_S 1 /** EFUSE_MEM_FORCE_PU : R/W; bitpos: [2]; default: 0; - * Configures whether to force power up eFuse SRAM.\\ 1: Force\\ 0: No effect\\ + * Configures whether to force power up eFuse SRAM. + * 1: Force + * 0: No effect */ #define EFUSE_MEM_FORCE_PU (BIT(2)) #define EFUSE_MEM_FORCE_PU_M (EFUSE_MEM_FORCE_PU_V << EFUSE_MEM_FORCE_PU_S) #define EFUSE_MEM_FORCE_PU_V 0x00000001U #define EFUSE_MEM_FORCE_PU_S 2 /** EFUSE_CLK_EN : R/W; bitpos: [16]; default: 0; - * Configures whether to force enable eFuse register configuration clock signal.\\ 1: - * Force\\ 0: The clock is enabled only during the reading and writing of registers\\ + * Configures whether to force enable eFuse register configuration clock signal. + * 1: Force + * 0: The clock is enabled only during the reading and writing of registers */ #define EFUSE_CLK_EN (BIT(16)) #define EFUSE_CLK_EN_M (EFUSE_CLK_EN_V << EFUSE_CLK_EN_S) @@ -2651,8 +3209,10 @@ extern "C" { */ #define EFUSE_CONF_REG (DR_REG_EFUSE_BASE + 0x1cc) /** EFUSE_OP_CODE : R/W; bitpos: [15:0]; default: 0; - * Configures operation command type.\\ 0x5A5A: Program operation command\\ 0x5AA5: - * Read operation command\\ Other values: No effect\\ + * Configures operation command type. + * 0x5A5A: Program operation command + * 0x5AA5: Read operation command + * Other values: No effect */ #define EFUSE_OP_CODE 0x0000FFFFU #define EFUSE_OP_CODE_M (EFUSE_OP_CODE_V << EFUSE_OP_CODE_S) @@ -2725,8 +3285,10 @@ extern "C" { */ #define EFUSE_STATUS_REG (DR_REG_EFUSE_BASE + 0x1d4) /** EFUSE_STATE : RO; bitpos: [3:0]; default: 0; - * Represents the state of the eFuse state machine.\\ 0: Reset state, the initial - * state after power-up\\ 1: Idle state\\ Other values: Non-idle state\\ + * Represents the state of the eFuse state machine. + * 0: Reset state, the initial state after power-up + * 1: Idle state + * Other values: Non-idle state */ #define EFUSE_STATE 0x0000000FU #define EFUSE_STATE_M (EFUSE_STATE_V << EFUSE_STATE_S) @@ -2734,6 +3296,7 @@ extern "C" { #define EFUSE_STATE_S 0 /** EFUSE_OTP_LOAD_SW : RO; bitpos: [4]; default: 0; * Represents the value of OTP_LOAD_SW. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define EFUSE_OTP_LOAD_SW (BIT(4)) #define EFUSE_OTP_LOAD_SW_M (EFUSE_OTP_LOAD_SW_V << EFUSE_OTP_LOAD_SW_S) @@ -2741,6 +3304,7 @@ extern "C" { #define EFUSE_OTP_LOAD_SW_S 4 /** EFUSE_OTP_VDDQ_C_SYNC2 : RO; bitpos: [5]; default: 0; * Represents the value of OTP_VDDQ_C_SYNC2. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define EFUSE_OTP_VDDQ_C_SYNC2 (BIT(5)) #define EFUSE_OTP_VDDQ_C_SYNC2_M (EFUSE_OTP_VDDQ_C_SYNC2_V << EFUSE_OTP_VDDQ_C_SYNC2_S) @@ -2748,6 +3312,7 @@ extern "C" { #define EFUSE_OTP_VDDQ_C_SYNC2_S 5 /** EFUSE_OTP_STROBE_SW : RO; bitpos: [6]; default: 0; * Represents the value of OTP_STROBE_SW. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define EFUSE_OTP_STROBE_SW (BIT(6)) #define EFUSE_OTP_STROBE_SW_M (EFUSE_OTP_STROBE_SW_V << EFUSE_OTP_STROBE_SW_S) @@ -2755,6 +3320,7 @@ extern "C" { #define EFUSE_OTP_STROBE_SW_S 6 /** EFUSE_OTP_CSB_SW : RO; bitpos: [7]; default: 0; * Represents the value of OTP_CSB_SW. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define EFUSE_OTP_CSB_SW (BIT(7)) #define EFUSE_OTP_CSB_SW_M (EFUSE_OTP_CSB_SW_V << EFUSE_OTP_CSB_SW_S) @@ -2762,6 +3328,7 @@ extern "C" { #define EFUSE_OTP_CSB_SW_S 7 /** EFUSE_OTP_PGENB_SW : RO; bitpos: [8]; default: 0; * Represents the value of OTP_PGENB_SW. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define EFUSE_OTP_PGENB_SW (BIT(8)) #define EFUSE_OTP_PGENB_SW_M (EFUSE_OTP_PGENB_SW_V << EFUSE_OTP_PGENB_SW_S) @@ -2769,6 +3336,7 @@ extern "C" { #define EFUSE_OTP_PGENB_SW_S 8 /** EFUSE_OTP_VDDQ_IS_SW : RO; bitpos: [9]; default: 0; * Represents the value of OTP_VDDQ_IS_SW. + * This field is only for internal debugging purposes. Do not use it in applications. */ #define EFUSE_OTP_VDDQ_IS_SW (BIT(9)) #define EFUSE_OTP_VDDQ_IS_SW_M (EFUSE_OTP_VDDQ_IS_SW_V << EFUSE_OTP_VDDQ_IS_SW_S) @@ -2787,14 +3355,18 @@ extern "C" { */ #define EFUSE_CMD_REG (DR_REG_EFUSE_BASE + 0x1d8) /** EFUSE_READ_CMD : R/W/SC; bitpos: [0]; default: 0; - * Configures whether to send read commands.\\ 1: Send\\ 0: No effect\\ + * Configures whether to send read commands. + * 1: Send + * 0: No effect */ #define EFUSE_READ_CMD (BIT(0)) #define EFUSE_READ_CMD_M (EFUSE_READ_CMD_V << EFUSE_READ_CMD_S) #define EFUSE_READ_CMD_V 0x00000001U #define EFUSE_READ_CMD_S 0 /** EFUSE_PGM_CMD : R/W/SC; bitpos: [1]; default: 0; - * Configures whether to send programming commands.\\ 1: Send\\ 0: No effect\\ + * Configures whether to send programming commands. + * 1: Send + * 0: No effect */ #define EFUSE_PGM_CMD (BIT(1)) #define EFUSE_PGM_CMD_M (EFUSE_PGM_CMD_V << EFUSE_PGM_CMD_S) @@ -2914,8 +3486,9 @@ extern "C" { #define EFUSE_DAC_NUM_V 0x000000FFU #define EFUSE_DAC_NUM_S 9 /** EFUSE_OE_CLR : R/W; bitpos: [17]; default: 0; - * Configures whether to reduce the power supply of programming voltage.\\ 0: Not - * reduce\\ 1: Reduce\\ + * Configures whether to reduce the power supply of programming voltage. + * 0: Not reduce + * 1: Reduce */ #define EFUSE_OE_CLR (BIT(17)) #define EFUSE_OE_CLR_M (EFUSE_OE_CLR_V << EFUSE_OE_CLR_S) @@ -3015,8 +3588,9 @@ extern "C" { */ #define EFUSE_WR_TIM_CONF0_RS_BYPASS_REG (DR_REG_EFUSE_BASE + 0x1fc) /** EFUSE_BYPASS_RS_CORRECTION : R/W; bitpos: [0]; default: 0; - * Configures whether to bypass the Reed-Solomon (RS) correction step.\\ 0: Not - * bypass\\ 1: Bypass\\ + * Configures whether to bypass the Reed-Solomon (RS) correction step. + * 0: Not bypass + * 1: Bypass */ #define EFUSE_BYPASS_RS_CORRECTION (BIT(0)) #define EFUSE_BYPASS_RS_CORRECTION_M (EFUSE_BYPASS_RS_CORRECTION_V << EFUSE_BYPASS_RS_CORRECTION_S) @@ -3030,8 +3604,9 @@ extern "C" { #define EFUSE_BYPASS_RS_BLK_NUM_V 0x000007FFU #define EFUSE_BYPASS_RS_BLK_NUM_S 1 /** EFUSE_UPDATE : WT; bitpos: [12]; default: 0; - * Configures whether to update multi-bit register signals.\\ 1: Update\\ 0: No - * effect\\ + * Configures whether to update multi-bit register signals. + * 1: Update + * 0: No effect */ #define EFUSE_UPDATE (BIT(12)) #define EFUSE_UPDATE_M (EFUSE_UPDATE_V << EFUSE_UPDATE_S) diff --git a/components/soc/esp32s31/register/soc/efuse_struct.h b/components/soc/esp32s31/register/soc/efuse_struct.h index b05187d5fd5..f8dc5323c06 100644 --- a/components/soc/esp32s31/register/soc/efuse_struct.h +++ b/components/soc/esp32s31/register/soc/efuse_struct.h @@ -3,9 +3,11 @@ * * SPDX-License-Identifier: Apache-2.0 OR MIT */ + #pragma once #include + #ifdef __cplusplus extern "C" { #endif @@ -44,13 +46,150 @@ typedef union { */ typedef union { struct { - /** wr_dis : RO; bitpos: [31:0]; default: 0; - * Represents whether programming of individual eFuse memory bit is disabled. For - * mapping between the bits of this field and the eFuse memory bits, please refer to - * Table \ref{tab:efuse-block0-para} and Table \ref{tab:efuse-block-1-10-para}.\\1: - * Disabled\\0: Enabled\\ + /** wr_dis_rd_dis : RO; bitpos: [0]; default: 0; + * Write disable bit 0 for EFUSE_RD_DIS */ - uint32_t wr_dis:32; + uint32_t wr_dis_rd_dis:1; + /** wr_dis_1 : RO; bitpos: [1]; default: 0; + * Write disable bit 1 for EFUSE_KM_RND_SWITCH_CYCLE, EFUSE_KM_DISABLE_DEPLOY_MODE, + * EFUSE_KM_DEPLOY_ONLY_ONCE, EFUSE_FORCE_USE_KEY_MANAGER_KEY, + * EFUSE_FORCE_DISABLE_SW_INIT_KEY, EFUSE_KM_XTS_KEY_LENGTH_256, EFUSE_LOCK_KM_KEY + */ + uint32_t wr_dis_1:1; + /** wr_dis_2 : RO; bitpos: [2]; default: 0; + * Write disable bit 2 for EFUSE_DIS_USB_JTAG, EFUSE_DIS_USB_SERIAL_JTAG, + * EFUSE_DIS_FORCE_DOWNLOAD, EFUSE_SPI_DOWNLOAD_MSPI_DIS, EFUSE_DIS_TWAI, + * EFUSE_JTAG_SEL_ENABLE, EFUSE_DIS_PAD_JTAG, EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT, + * EFUSE_DIS_WIFI6, EFUSE_WDT_DELAY_SEL, EFUSE_SECURE_BOOT_DISABLE_FAST_WAKE, + * EFUSE_DIS_WDT, EFUSE_DIS_SWD, EFUSE_PMU_FLASH_POWER_SEL, + * EFUSE_PMU_FLASH_POWER_SEL_EN, EFUSE_POWER_GLITCH_EN + */ + uint32_t wr_dis_2:1; + /** wr_dis_3 : RO; bitpos: [3]; default: 0; + * Write disable bit 3 for EFUSE_PVT_0_GLITCH_EN, EFUSE_PVT_0_GLITCH_MODE, + * EFUSE_PVT_1_GLITCH_EN, EFUSE_PVT_1_GLITCH_MODE + */ + uint32_t wr_dis_3:1; + /** wr_dis_spi_boot_crypt_cnt : RO; bitpos: [4]; default: 0; + * Write disable bit 4 for EFUSE_SPI_BOOT_CRYPT_CNT + */ + uint32_t wr_dis_spi_boot_crypt_cnt:1; + /** wr_dis_secure_boot_key_revoke0 : RO; bitpos: [5]; default: 0; + * Write disable bit 5 for EFUSE_SECURE_BOOT_KEY_REVOKE0 + */ + uint32_t wr_dis_secure_boot_key_revoke0:1; + /** wr_dis_secure_boot_key_revoke1 : RO; bitpos: [6]; default: 0; + * Write disable bit 6 for EFUSE_SECURE_BOOT_KEY_REVOKE1 + */ + uint32_t wr_dis_secure_boot_key_revoke1:1; + /** wr_dis_secure_boot_key_revoke2 : RO; bitpos: [7]; default: 0; + * Write disable bit 7 for EFUSE_SECURE_BOOT_KEY_REVOKE2 + */ + uint32_t wr_dis_secure_boot_key_revoke2:1; + /** wr_dis_key_purpose_0 : RO; bitpos: [8]; default: 0; + * Write disable bit 8 for EFUSE_KEY_PURPOSE_0 + */ + uint32_t wr_dis_key_purpose_0:1; + /** wr_dis_key_purpose_1 : RO; bitpos: [9]; default: 0; + * Write disable bit 9 for EFUSE_KEY_PURPOSE_1 + */ + uint32_t wr_dis_key_purpose_1:1; + /** wr_dis_key_purpose_2 : RO; bitpos: [10]; default: 0; + * Write disable bit 10 for EFUSE_KEY_PURPOSE_2 + */ + uint32_t wr_dis_key_purpose_2:1; + /** wr_dis_key_purpose_3 : RO; bitpos: [11]; default: 0; + * Write disable bit 11 for EFUSE_KEY_PURPOSE_3 + */ + uint32_t wr_dis_key_purpose_3:1; + /** wr_dis_key_purpose_4 : RO; bitpos: [12]; default: 0; + * Write disable bit 12 for EFUSE_KEY_PURPOSE_4 + */ + uint32_t wr_dis_key_purpose_4:1; + /** wr_dis_13 : RO; bitpos: [13]; default: 0; + * reserved + */ + uint32_t wr_dis_13:1; + /** wr_dis_14 : RO; bitpos: [14]; default: 0; + * Write disable bit 14 for EFUSE_DIS_SM_CRYPT, EFUSE_ECC_FORCE_CONST_TIME, + * EFUSE_ECDSA_DISABLE_SOFT_K, EFUSE_SEC_DPA_LEVEL, EFUSE_XTS_DPA_CLK_ENABLE, + * EFUSE_XTS_DPA_PSEUDO_LEVEL, EFUSE_SDC_NONCE_ENA, EFUSE_SDC_CHIP_INFO_SOURCE, + * EFUSE_SDC_DISABLE_FAST_VEF, EFUSE_ENA_XTS_SHADOW, + * EFUSE_ENA_SPI_BOOT_CRYPT_SCRAMBLER, EFUSE_RE_ENABLE_JTAG_SOURCE + */ + uint32_t wr_dis_14:1; + /** wr_dis_secure_boot_en : RO; bitpos: [15]; default: 0; + * Write disable bit 15 for EFUSE_SECURE_BOOT_EN + */ + uint32_t wr_dis_secure_boot_en:1; + /** wr_dis_secure_boot_aggressive_revoke : RO; bitpos: [16]; default: 0; + * Write disable bit 16 for EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE + */ + uint32_t wr_dis_secure_boot_aggressive_revoke:1; + /** wr_dis_17 : RO; bitpos: [17]; default: 0; + * reserved + */ + uint32_t wr_dis_17:1; + /** wr_dis_18 : RO; bitpos: [18]; default: 0; + * Write disable bit 18 for EFUSE_FLASH_TYPE, EFUSE_DIS_USB_OTG_DOWNLOAD_MODE, + * EFUSE_FLASH_TPUW, EFUSE_DIS_DOWNLOAD_MODE, EFUSE_DIS_DIRECT_BOOT, + * EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT, EFUSE_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE, + * EFUSE_ENABLE_SECURITY_DOWNLOAD, EFUSE_UART_PRINT_CONTROL, EFUSE_FORCE_SEND_RESUME, + * EFUSE_SECURE_VERSION + */ + uint32_t wr_dis_18:1; + /** wr_dis_huk_gen_state : RO; bitpos: [19]; default: 0; + * Write disable bit 19 for EFUSE_HUK_GEN_STATE + */ + uint32_t wr_dis_huk_gen_state:1; + /** wr_dis_block1 : RO; bitpos: [20]; default: 0; + * Write disable bit 20 for BLOCK1 + */ + uint32_t wr_dis_block1:1; + /** wr_dis_block2 : RO; bitpos: [21]; default: 0; + * Write disable bit 21 for BLOCK2 + */ + uint32_t wr_dis_block2:1; + /** wr_dis_block3 : RO; bitpos: [22]; default: 0; + * Write disable bit 22 for BLOCK3 + */ + uint32_t wr_dis_block3:1; + /** wr_dis_block4 : RO; bitpos: [23]; default: 0; + * Write disable bit 23 for BLOCK4 + */ + uint32_t wr_dis_block4:1; + /** wr_dis_block5 : RO; bitpos: [24]; default: 0; + * Write disable bit 24 for BLOCK5 + */ + uint32_t wr_dis_block5:1; + /** wr_dis_block6 : RO; bitpos: [25]; default: 0; + * Write disable bit 25 for BLOCK6 + */ + uint32_t wr_dis_block6:1; + /** wr_dis_block7 : RO; bitpos: [26]; default: 0; + * Write disable bit 26 for BLOCK7 + */ + uint32_t wr_dis_block7:1; + /** wr_dis_block8 : RO; bitpos: [27]; default: 0; + * Write disable bit 27 for BLOCK8 + */ + uint32_t wr_dis_block8:1; + /** wr_dis_block9 : RO; bitpos: [28]; default: 0; + * Write disable bit 28 for BLOCK9 + */ + uint32_t wr_dis_block9:1; + /** wr_dis_29 : RO; bitpos: [29]; default: 0; + * reserved + */ + uint32_t wr_dis_29:1; + /** wr_dis_30 : RO; bitpos: [30]; default: 0; + * reserved + */ + uint32_t wr_dis_30:1; + /** wr_dis_soft_dis_jtag : RO; bitpos: [31]; default: 0; + * Write disable bit 31 for EFUSE_SOFT_DIS_JTAG + */ + uint32_t wr_dis_soft_dis_jtag:1; }; uint32_t val; } efuse_rd_wr_dis_reg_t; @@ -60,68 +199,108 @@ typedef union { */ typedef union { struct { - /** rd_dis : RO; bitpos: [6:0]; default: 0; - * Represents whether reading of individual eFuse block(block4~block9) is disabled or - * enabled.\\ 1: disabled\\ 0: enabled\\ + /** rd_dis_block4 : RO; bitpos: [0]; default: 0; + * Read disable bit 0 for BLOCK4 */ - uint32_t rd_dis:7; - /** rd_reserve_0_39 : RW; bitpos: [9:7]; default: 0; - * Reserved, it was created by set_missed_fields_in_regs func + uint32_t rd_dis_block4:1; + /** rd_dis_block5 : RO; bitpos: [1]; default: 0; + * Read disable bit 1 for BLOCK5 */ - uint32_t rd_reserve_0_39:3; + uint32_t rd_dis_block5:1; + /** rd_dis_block6 : RO; bitpos: [2]; default: 0; + * Read disable bit 2 for BLOCK6 + */ + uint32_t rd_dis_block6:1; + /** rd_dis_block7 : RO; bitpos: [3]; default: 0; + * Read disable bit 3 for BLOCK7 + */ + uint32_t rd_dis_block7:1; + /** rd_dis_block8 : RO; bitpos: [4]; default: 0; + * Read disable bit 4 for BLOCK8 + */ + uint32_t rd_dis_block8:1; + /** rd_dis_block9 : RO; bitpos: [5]; default: 0; + * Read disable bit 5 for BLOCK9 + */ + uint32_t rd_dis_block9:1; + /** rd_dis_6 : RO; bitpos: [6]; default: 0; + * reserved + */ + uint32_t rd_dis_6:1; + /** reserved_0_39 : R; bitpos: [9:7]; default: 0; + * reserved + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t reserved_0_39:3; /** dis_usb_jtag : RO; bitpos: [10]; default: 0; - * Represents whether the function of usb switch to jtag is disabled or enabled.\\ 1: - * disabled\\ 0: enabled\\ + * Represents whether the function of usb switch to jtag is disabled or enabled. + * 1: disabled + * 0: enabled */ uint32_t dis_usb_jtag:1; /** dis_usb_serial_jtag : RO; bitpos: [11]; default: 0; - * Represents whether USB-Serial-JTAG is disabled or enabled.\\ 1: disabled\\ 0: - * enabled\\ + * Represents whether USB-Serial-JTAG is disabled or enabled. + * 1: disabled + * 0: enabled + * + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t dis_usb_serial_jtag:1; /** dis_force_download : RO; bitpos: [12]; default: 0; * Represents whether the function that forces chip into download mode is disabled or - * enabled.\\ 1: disabled\\ 0: enabled\\ + * enabled. + * 1: disabled + * 0: enabled */ uint32_t dis_force_download:1; /** spi_download_mspi_dis : RO; bitpos: [13]; default: 0; - * Represents whether SPI0 controller during boot_mode_download is disabled or - * enabled.\\ 1: disabled\\ 0: enabled\\ + * Represents whether SPI0 controller during boot_mode_download is disabled or enabled. + * 1: disabled + * 0: enabled */ uint32_t spi_download_mspi_dis:1; /** dis_twai : RO; bitpos: [14]; default: 0; - * Represents whether TWAI function is disabled or enabled.\\ 1: disabled\\ 0: - * enabled\\ + * Represents whether TWAI function is disabled or enabled. + * 1: disabled + * 0: enabled */ uint32_t dis_twai:1; /** jtag_sel_enable : RO; bitpos: [15]; default: 0; * Represents whether the selection between usb_to_jtag and pad_to_jtag through * strapping gpio15 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0 - * is enabled or disabled.\\ 1: enabled\\ 0: disabled\\ + * is enabled or disabled. + * 1: enabled + * 0: disabled */ uint32_t jtag_sel_enable:1; /** soft_dis_jtag : RO; bitpos: [18:16]; default: 0; - * Represents whether JTAG is disabled in soft way.\\ Odd number: disabled\\ Even - * number: enabled\\ + * Represents whether JTAG is disabled in soft way. + * Odd number: disabled + * Even number: enabled */ uint32_t soft_dis_jtag:3; /** dis_pad_jtag : RO; bitpos: [19]; default: 0; - * Represents whether JTAG is disabled in the hard way(permanently).\\ 1: disabled\\ - * 0: enabled\\ + * Represents whether JTAG is disabled in the hard way(permanently). + * 1: disabled + * 0: enabled */ uint32_t dis_pad_jtag:1; /** dis_download_manual_encrypt : RO; bitpos: [20]; default: 0; * Represents whether flash encrypt function is disabled or enabled(except in SPI boot - * mode).\\ 1: disabled\\ 0: enabled\\ + * mode). + * 1: disabled + * 0: enabled */ uint32_t dis_download_manual_encrypt:1; - /** rd_reserve_0_53 : RW; bitpos: [21]; default: 0; - * Reserved, it was created by set_missed_fields_in_regs func + /** reserved_0_53 : R; bitpos: [21]; default: 0; + * reserved + * This field is only for internal debugging purposes. Do not use it in applications. */ - uint32_t rd_reserve_0_53:1; + uint32_t reserved_0_53:1; /** dis_wifi6 : RO; bitpos: [22]; default: 0; - * Represents whether the WIFI6 feature is enabled or disabled. 1: WIFI6 is disabled, 0: - * WIFI6 is enabled. + * Represents whether the WIFI6 feature is enabled or disabled. 1: WIFI6 is disabled; + * 0: WIFI6 is enabled + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t dis_wifi6:1; /** huk_gen_state : RO; bitpos: [27:23]; default: 0; @@ -129,10 +308,11 @@ typedef union { * even of 1 is valid. */ uint32_t huk_gen_state:5; - /** rd_reserve_0_60 : RW; bitpos: [31:28]; default: 0; - * Reserved, it was created by set_missed_fields_in_regs func + /** reserved_0_60 : R; bitpos: [31:28]; default: 0; + * reserved + * This field is only for internal debugging purposes. Do not use it in applications. */ - uint32_t rd_reserve_0_60:4; + uint32_t reserved_0_60:4; }; uint32_t val; } efuse_rd_repeat_data0_reg_t; @@ -147,25 +327,37 @@ typedef union { * register. 1: 8 km clk cycles. 2: 16 km cycles. 3: 32 km cycles */ uint32_t km_rnd_switch_cycle:1; - /** rd_reserve_0_65 : RW; bitpos: [1]; default: 0; - * Reserved, it was created by set_missed_fields_in_regs func + /** reserved_0_65 : R; bitpos: [1]; default: 0; + * reserved + * This field is only for internal debugging purposes. Do not use it in applications. */ - uint32_t rd_reserve_0_65:1; + uint32_t reserved_0_65:1; /** km_disable_deploy_mode : RO; bitpos: [6:2]; default: 0; - * Represents whether the deploy mode of key manager is disable or not. \\ 1: disabled - * \\ 0: enabled.\\ bit 0: ecsda, bit 1: flash & spi boot srambler, bit2: hmac & aes, - * bit3: ds & rma nonce, bit4: psram + * Represents whether the deploy mode of key manager is disable or not. + * 1: disabled + * 0: enabled. + * bit 0: ecsda, bit 1: flash & spi boot srambler, bit2: hmac & aes, bit3: ds & SDC + * nonce, bit4: psram */ uint32_t km_disable_deploy_mode:5; /** km_deploy_only_once : RO; bitpos: [11:7]; default: 0; * Represents whether corresponding key can only be deployed once. 1 is true, 0 is - * false. \\ 0: ecsda\\ 1: flash & spi boot srambler\\ 2: hmac & aes\\ 3: ds & rma - * nonce\\ 4: psram\\ + * false. + * 0: ecsda + * 1: flash & spi boot srambler + * 2: hmac & aes + * 3: ds & SDC nonce + * 4: psram */ uint32_t km_deploy_only_once:5; /** force_use_key_manager_key : RO; bitpos: [16:12]; default: 0; * Represents whether corresponding key must come from key manager. 1 is true, 0 is - * false.\\ 0: ecsda\\ 1: flash\\ 2: reserved\\ 3: reserved\\ 4: psram\\ + * false. + * 0: ecsda + * 1: flash + * 2: reserved + * 3: reserved + * 4: psram */ uint32_t force_use_key_manager_key:5; /** force_disable_sw_init_key : RO; bitpos: [17]; default: 0; @@ -175,45 +367,48 @@ typedef union { uint32_t force_disable_sw_init_key:1; /** km_xts_key_length_256 : RO; bitpos: [18]; default: 0; * Represents whether to configure flash encryption use xts-128 key. else use xts-256 - * key. \\ 0: 128-bit key \\ 1: 256-bit key\\ + * key. + * 0: 128-bit key + * 1: 256-bit key */ uint32_t km_xts_key_length_256:1; /** wdt_delay_sel : RO; bitpos: [19]; default: 0; - * Represents the threshold level of the RTC watchdog STG0 timeout.\\0: Original - * threshold configuration value of STG0 *2 \\1: Original threshold configuration - * value of STG0 *4 \\2: Original threshold configuration value of STG0 *8 \\3: - * Original threshold configuration value of STG0 *16 \\ + * Represents the threshold level of the RTC watchdog STG0 timeout. + * 0: Original threshold configuration value of STG0 *2 + * 1: Original threshold configuration value of STG0 *4 + * 2: Original threshold configuration value of STG0 *8 + * 3: Original threshold configuration value of STG0 *16 */ uint32_t wdt_delay_sel:1; /** dis_sm_crypt : RO; bitpos: [20]; default: 0; - * Represents whether to disable all the SM crypto functions, including SM2, SM3.\\ 1: - * disabled\\ 0: enabled\\ + * Represents whether to disable all the SM crypto functions, including SM2, SM3. + * 1: disabled + * 0: enabled */ uint32_t dis_sm_crypt:1; /** spi_boot_crypt_cnt : RO; bitpos: [23:21]; default: 0; - * Represents whether SPI boot encrypt/decrypt is disabled or enabled.\\ Odd number of - * 1: enabled\\ Even number of 1: disabled\\ + * Represents whether SPI boot encrypt/decrypt is disabled or enabled. + * Odd number of 1: enabled + * Even number of 1: disabled */ uint32_t spi_boot_crypt_cnt:3; /** secure_boot_key_revoke0 : RO; bitpos: [24]; default: 0; - * Represents whether revoking first secure boot key is enabled or disabled.\\ 1: - * enabled\\ 0: disabled\\ + * Revoke 1st secure boot key */ uint32_t secure_boot_key_revoke0:1; /** secure_boot_key_revoke1 : RO; bitpos: [25]; default: 0; - * Represents whether revoking second secure boot key is enabled or disabled.\\ 1: - * enabled\\ 0: disabled\\ + * Revoke 2nd secure boot key */ uint32_t secure_boot_key_revoke1:1; /** secure_boot_key_revoke2 : RO; bitpos: [26]; default: 0; - * Represents whether revoking third secure boot key is enabled or disabled.\\ 1: - * enabled\\ 0: disabled\\ + * Revoke 3rd secure boot key */ uint32_t secure_boot_key_revoke2:1; - /** rd_reserve_0_91 : RW; bitpos: [31:27]; default: 0; - * Reserved, it was created by set_missed_fields_in_regs func + /** reserved_0_91 : R; bitpos: [31:27]; default: 0; + * reserved + * This field is only for internal debugging purposes. Do not use it in applications. */ - uint32_t rd_reserve_0_91:5; + uint32_t reserved_0_91:5; }; uint32_t val; } efuse_rd_repeat_data1_reg_t; @@ -244,13 +439,15 @@ typedef union { */ uint32_t key_purpose_4:5; /** ecc_force_const_time : RO; bitpos: [25]; default: 0; - * Represents whether permanently turn on ECC const-time mode. \\ 1: turn on\\ 0: turn - * off\\ + * Represents whether permanently turn on ECC const-time mode. + * 1: turn on + * 0: turn off */ uint32_t ecc_force_const_time:1; /** ecdsa_disable_soft_k : RO; bitpos: [26]; default: 0; - * Represents whether permanently turn off ECDSA software set KEY.\\ 1: turn off\\ 0: - * turn on\\ + * Represents whether permanently turn off ECDSA software set KEY. + * 1: turn off + * 0: turn on */ uint32_t ecdsa_disable_soft_k:1; /** sec_dpa_level : RO; bitpos: [28:27]; default: 0; @@ -258,14 +455,16 @@ typedef union { */ uint32_t sec_dpa_level:2; /** xts_dpa_clk_enable : RO; bitpos: [29]; default: 0; - * Represents whether to enable xts clock anti-dpa attack function.\\0: Disabled. \\1: - * Enabled\\ + * Represents whether to enable xts clock anti-dpa attack function. + * 0: Disabled. + * 1: Enabled */ uint32_t xts_dpa_clk_enable:1; - /** rd_reserve_0_126 : RW; bitpos: [31:30]; default: 0; - * Reserved, it was created by set_missed_fields_in_regs func + /** reserved_0_126 : R; bitpos: [31:30]; default: 0; + * reserved + * This field is only for internal debugging purposes. Do not use it in applications. */ - uint32_t rd_reserve_0_126:2; + uint32_t reserved_0_126:2; }; uint32_t val; } efuse_rd_repeat_data2_reg_t; @@ -276,40 +475,46 @@ typedef union { typedef union { struct { /** xts_dpa_pseudo_level : RO; bitpos: [1:0]; default: 0; - * Represents the control of the xts pseudo-round anti-dpa attack function.\\ 0: - * controlled by register.\\ 1-3: the higher the value is, the more pseudo-rounds are - * inserted to the xts-aes calculation\\ + * Represents the control of the xts pseudo-round anti-dpa attack function. 0: + * controlled by register. 1-3: the higher the value is; the more pseudo-rounds are + * inserted to the xts-aes calculation */ uint32_t xts_dpa_pseudo_level:2; /** secure_boot_en : RO; bitpos: [2]; default: 0; - * Represents whether secure boot is enabled or disabled.\\ 1: enabled\\ 0: disabled\\ + * Represents whether secure boot is enabled or disabled. + * 1: enabled + * 0: disabled */ uint32_t secure_boot_en:1; /** secure_boot_aggressive_revoke : RO; bitpos: [3]; default: 0; - * Represents whether revoking aggressive secure boot is enabled or disabled.\\ 1: - * enabled.\\ 0: disabled\\ + * Represents whether revoking aggressive secure boot is enabled or disabled. + * 1: enabled. + * 0: disabled */ uint32_t secure_boot_aggressive_revoke:1; - /** rd_reserve_0_132 : RW; bitpos: [4]; default: 0; - * Reserved, it was created by set_missed_fields_in_regs func + /** reserved_0_132 : R; bitpos: [4]; default: 0; + * reserved + * This field is only for internal debugging purposes. Do not use it in applications. */ - uint32_t rd_reserve_0_132:1; + uint32_t reserved_0_132:1; /** flash_type : RO; bitpos: [5]; default: 0; * flash type: 0: nor flash, 1: nand flash */ uint32_t flash_type:1; - /** rd_reserve_0_134 : RW; bitpos: [8:6]; default: 0; - * Reserved, it was created by set_missed_fields_in_regs func + /** reserved_0_134 : R; bitpos: [8:6]; default: 0; + * reserved + * This field is only for internal debugging purposes. Do not use it in applications. */ - uint32_t rd_reserve_0_134:3; + uint32_t reserved_0_134:3; /** dis_usb_otg_download_mode : RO; bitpos: [9]; default: 0; * Set this bit to disable download via USB-OTG. */ uint32_t dis_usb_otg_download_mode:1; - /** rd_reserve_0_138 : RW; bitpos: [11:10]; default: 0; - * Reserved, it was created by set_missed_fields_in_regs func + /** reserved_0_138 : R; bitpos: [11:10]; default: 0; + * reserved + * This field is only for internal debugging purposes. Do not use it in applications. */ - uint32_t rd_reserve_0_138:2; + uint32_t reserved_0_138:2; /** flash_tpuw : RO; bitpos: [15:12]; default: 0; * Represents the flash waiting time after power-up, in unit of ms. When the value * less than 15, the waiting time is the programmed value. Otherwise, the waiting time @@ -317,49 +522,60 @@ typedef union { */ uint32_t flash_tpuw:4; /** dis_download_mode : RO; bitpos: [16]; default: 0; - * Represents whether Download mode is disabled or enabled.\\ 1: disabled\\ 0: - * enabled\\ + * Represents whether Download mode is disabled or enabled. + * 1: disabled + * 0: enabled */ uint32_t dis_download_mode:1; /** dis_direct_boot : RO; bitpos: [17]; default: 0; - * Represents whether direct boot mode is disabled or enabled.\\ 1: disabled\\ 0: - * enabled\\ + * Represents whether direct boot mode is disabled or enabled. + * 1: disabled + * 0: enabled */ uint32_t dis_direct_boot:1; /** dis_usb_serial_jtag_rom_print : RO; bitpos: [18]; default: 0; - * Represents whether print from USB-Serial-JTAG is disabled or enabled.\\ 1: - * disabled\\ 0: enabled\\ + * Represents whether print from USB-Serial-JTAG is disabled or enabled. + * 1: disabled + * 0: enabled */ uint32_t dis_usb_serial_jtag_rom_print:1; /** lock_km_key : RO; bitpos: [19]; default: 0; - * Represetns whether to lock the efuse xts key.\\ 1. Lock\\ 0: Unlock\\ + * Represetns whether to lock the efuse xts key. + * 1. Lock + * 0: Unlock */ uint32_t lock_km_key:1; /** dis_usb_serial_jtag_download_mode : RO; bitpos: [20]; default: 0; - * Represents whether the USB-Serial-JTAG download function is disabled or enabled.\\ - * 1: Disable\\ 0: Enable\\ + * Represents whether the USB-Serial-JTAG download function is disabled or enabled. + * 1: Disable + * 0: Enable */ uint32_t dis_usb_serial_jtag_download_mode:1; /** enable_security_download : RO; bitpos: [21]; default: 0; - * Represents whether security download is enabled or disabled.\\ 1: enabled\\ 0: - * disabled\\ + * Represents whether security download is enabled or disabled. + * 1: enabled + * 0: disabled */ uint32_t enable_security_download:1; /** uart_print_control : RO; bitpos: [23:22]; default: 0; - * Represents the type of UART printing.\\ 00: force enable printing\\ 01: enable - * printing when GPIO8 is reset at low level\\ 10: enable printing when GPIO8 is reset - * at high level\\ 11: force disable printing\\ + * Represents the type of UART printing. + * 00: force enable printing + * 01: enable printing when GPIO8 is reset at low level + * 10: enable printing when GPIO8 is reset at high level + * 11: force disable printing */ uint32_t uart_print_control:2; /** force_send_resume : RO; bitpos: [24]; default: 0; - * Represents whether ROM code is forced to send a resume command during SPI boot.\\ - * 1: forced\\ 0:not forced\\ + * Represents whether ROM code is forced to send a resume command during SPI boot. + * 1: forced + * 0:not forced */ uint32_t force_send_resume:1; - /** rd_reserve_0_153 : RW; bitpos: [31:25]; default: 0; - * Reserved, it was created by set_missed_fields_in_regs func + /** reserved_0_153 : R; bitpos: [31:25]; default: 0; + * reserved + * This field is only for internal debugging purposes. Do not use it in applications. */ - uint32_t rd_reserve_0_153:7; + uint32_t reserved_0_153:7; }; uint32_t val; } efuse_rd_repeat_data3_reg_t; @@ -375,18 +591,22 @@ typedef union { uint32_t secure_version:16; /** secure_boot_disable_fast_wake : RO; bitpos: [16]; default: 0; * Represents whether FAST VERIFY ON WAKE is disabled or enabled when Secure Boot is - * enabled.\\ 1: disabled\\ 0: enabled\\ + * enabled. + * 1: disabled + * 0: enabled */ uint32_t secure_boot_disable_fast_wake:1; /** hys_en_pad : RO; bitpos: [17]; default: 0; - * Represents whether the hysteresis function of corresponding PAD is enabled.\\ 1: - * enabled\\ 0:disabled\\ + * Represents whether the hysteresis function of corresponding PAD is enabled. + * 1: enabled + * 0:disabled */ uint32_t hys_en_pad:1; - /** rd_reserve_0_178 : RW; bitpos: [31:18]; default: 0; - * Reserved, it was created by set_missed_fields_in_regs func + /** reserved_0_178 : R; bitpos: [31:18]; default: 0; + * reserved + * This field is only for internal debugging purposes. Do not use it in applications. */ - uint32_t rd_reserve_0_178:14; + uint32_t reserved_0_178:14; }; uint32_t val; } efuse_rd_repeat_data4_reg_t; @@ -396,10 +616,11 @@ typedef union { */ typedef union { struct { - /** rd_reserve_0_192 : RW; bitpos: [1:0]; default: 0; - * Reserved, it was created by set_missed_fields_in_regs func + /** reserved_0_192 : R; bitpos: [1:0]; default: 0; + * reserved + * This field is only for internal debugging purposes. Do not use it in applications. */ - uint32_t rd_reserve_0_192:2; + uint32_t reserved_0_192:2; /** dcdc_vset_en : RO; bitpos: [2]; default: 0; * Select dcdc vset use efuse_dcdc_vset. */ @@ -412,10 +633,11 @@ typedef union { * Set this bit to disable super-watchdog. */ uint32_t dis_swd:1; - /** rd_reserve_0_197 : RW; bitpos: [10:5]; default: 0; - * Reserved, it was created by set_missed_fields_in_regs func + /** reserved_0_197 : R; bitpos: [10:5]; default: 0; + * reserved + * This field is only for internal debugging purposes. Do not use it in applications. */ - uint32_t rd_reserve_0_197:6; + uint32_t reserved_0_197:6; /** secure_boot_sha384_en : RO; bitpos: [11]; default: 0; * Represents whether secure boot using SHA-384 is enabled. 0: Disable 1: Enable */ @@ -426,13 +648,16 @@ typedef union { */ uint32_t bootloader_anti_rollback_secure_version:4; /** bootloader_anti_rollback_en : RO; bitpos: [16]; default: 0; - * Represents whether the ani-rollback check for the 2nd stage bootloader is - * enabled.\\1: Enabled\\0: Disabled\\ + * Represents whether the ani-rollback check for the 2nd stage bootloader is enabled. + * 1: Enabled + * 0: Disabled */ uint32_t bootloader_anti_rollback_en:1; /** bootloader_anti_rollback_update_in_rom : RO; bitpos: [17]; default: 0; * Represents whether the ani-rollback SECURE_VERSION will be updated from the ROM - * bootloader.\\1: Enable\\0: Disable\\ + * bootloader. + * 1: Enable + * 0: Disable */ uint32_t bootloader_anti_rollback_update_in_rom:1; /** recovery_bootloader_flash_sector : RO; bitpos: [29:18]; default: 0; @@ -441,11 +666,12 @@ typedef union { * - this feature is disabled. */ uint32_t recovery_bootloader_flash_sector:12; - /** rma_ena : RO; bitpos: [31:30]; default: 0; - * Represents whether rma function is supported in download mode.\\ 2'b01/2'b10: - * enabled\\2'b00/2'b11: disabled\\ + /** sdc_ena : RO; bitpos: [31:30]; default: 0; + * Represents whether SDC function is supported in download mode. + * 2'b01/2'b10: enabled + * 2'b00/2'b11: disabled */ - uint32_t rma_ena:2; + uint32_t sdc_ena:2; }; uint32_t val; } efuse_rd_repeat_data5_reg_t; @@ -455,27 +681,34 @@ typedef union { */ typedef union { struct { - /** rma_session_counter : RO; bitpos: [2:0]; default: 0; - * Represents the number of times the RMA session has been entered. + /** sdc_session_counter : RO; bitpos: [2:0]; default: 0; + * Represents the number of times the SDC session has been entered. */ - uint32_t rma_session_counter:3; - /** rma_nonce_ena : RO; bitpos: [4:3]; default: 0; - * Represents whether random number NONCE is used in RMA and whether the KM module is - * used to generate the NONCE\\. 2'bx0: No NONCE\\ 2'b1x: Use KM generate NONCE.\\ + uint32_t sdc_session_counter:3; + /** sdc_nonce_ena : RO; bitpos: [4:3]; default: 0; + * Represents whether random number NONCE is used in SDC and whether the KM module is + * used to generate the NONCE + * . 2'bx0: No NONCE + * 2'b1x: Use KM generate NONCE. */ - uint32_t rma_nonce_ena:2; - /** rma_chip_info_source : RO; bitpos: [5]; default: 0; + uint32_t sdc_nonce_ena:2; + /** sdc_chip_info_source : RO; bitpos: [5]; default: 0; * Represents whether HUK_info is selected as the source for calculating CHIP_info in - * RMA.\\1: use HUK_info\\ 0: use UNIQ_id\\ + * SDC. + * 1: use HUK_info + * 0: use UNIQ_id */ - uint32_t rma_chip_info_source:1; - /** rma_disable_fast_vef : RO; bitpos: [6]; default: 0; - * Represents whether disable FAST_VEF in RMA session.\\1: disable\\0: enable\\ + uint32_t sdc_chip_info_source:1; + /** sdc_disable_fast_vef : RO; bitpos: [6]; default: 0; + * Represents whether disable FAST_VEF in SDC session. + * 1: disable + * 0: enable */ - uint32_t rma_disable_fast_vef:1; + uint32_t sdc_disable_fast_vef:1; /** pvt_0_glitch_en : RO; bitpos: [7]; default: 0; - * Represents whether to enable PVT power glitch monitor function.\\1:Enable. - * \\0:Disable + * Represents whether to enable PVT power glitch monitor function. + * 1:Enable. + * 0:Disable */ uint32_t pvt_0_glitch_en:1; /** pvt_0_glitch_mode : RO; bitpos: [9:8]; default: 0; @@ -483,8 +716,9 @@ typedef union { */ uint32_t pvt_0_glitch_mode:2; /** pvt_1_glitch_en : RO; bitpos: [10]; default: 0; - * Represents whether to enable PVT power glitch monitor function.\\1:Enable. - * \\0:Disable + * Represents whether to enable PVT power glitch monitor function. + * 1:Enable. + * 0:Disable */ uint32_t pvt_1_glitch_en:1; /** pvt_1_glitch_mode : RO; bitpos: [12:11]; default: 0; @@ -492,7 +726,9 @@ typedef union { */ uint32_t pvt_1_glitch_mode:2; /** pmu_flash_power_sel : RO; bitpos: [13]; default: 0; - * FLASH power select.\\ 1'b1: use 3.3V\\1'b0: use 1.8V + * FLASH power select. + * 1'b1: use 3.3V + * 1'b0: use 1.8V */ uint32_t pmu_flash_power_sel:1; /** pmu_flash_power_sel_en : RO; bitpos: [14]; default: 0; @@ -506,23 +742,28 @@ typedef union { uint32_t power_glitch_en:4; /** ena_xts_shadow : RO; bitpos: [19]; default: 0; * Represents whether to enable XTS-AES shadow core countermeasure against fault - * injection attacks. \\ 0: Disabled\\ 1: Enabled\\ + * injection attacks. + * 0: Disabled + * 1: Enabled */ uint32_t ena_xts_shadow:1; /** ena_spi_boot_crypt_scrambler : RO; bitpos: [20]; default: 0; - * Represents whether to enable ciphertext scrambler for external memory . \\ 0: - * Disabled\\ 1: Enabled\\ + * Represents whether to enable ciphertext scrambler for external memory . + * 0: Disabled + * 1: Enabled */ uint32_t ena_spi_boot_crypt_scrambler:1; /** re_enable_jtag_source : RO; bitpos: [21]; default: 0; - * Represents which Crypto peripheral is selected for re-enabling JTAG. \\ 0: RMA\\ 1: - * HMAC\\ + * Represents which Crypto peripheral is selected for re-enabling JTAG. + * 0: SDC + * 1: HMAC */ uint32_t re_enable_jtag_source:1; - /** rd_reserve_0_246 : RW; bitpos: [31:22]; default: 0; - * Reserved, it was created by set_missed_fields_in_regs func + /** reserved_0_246 : R; bitpos: [31:22]; default: 0; + * reserved + * This field is only for internal debugging purposes. Do not use it in applications. */ - uint32_t rd_reserve_0_246:10; + uint32_t reserved_0_246:10; }; uint32_t val; } efuse_rd_repeat_data6_reg_t; @@ -534,12 +775,14 @@ typedef union { struct { /** repeat7_rsvd : RO; bitpos: [15:0]; default: 0; * Reserved. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t repeat7_rsvd:16; - /** rd_reserve_0_272 : RW; bitpos: [31:16]; default: 0; - * Reserved, it was created by set_missed_fields_in_regs func + /** reserved_0_272 : R; bitpos: [31:16]; default: 0; + * reserved + * This field is only for internal debugging purposes. Do not use it in applications. */ - uint32_t rd_reserve_0_272:16; + uint32_t reserved_0_272:16; }; uint32_t val; } efuse_rd_repeat_data7_reg_t; @@ -583,10 +826,12 @@ typedef union { struct { /** mac_reserved_0 : RO; bitpos: [13:0]; default: 0; * Reserved. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mac_reserved_0:14; /** mac_reserved_1 : RO; bitpos: [31:14]; default: 0; * Reserved. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mac_reserved_1:18; }; @@ -600,6 +845,7 @@ typedef union { struct { /** mac_reserved_2 : RO; bitpos: [17:0]; default: 0; * Reserved. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t mac_reserved_2:18; /** wafer_version_minor : R; bitpos: [21:18]; default: 0; @@ -655,10 +901,30 @@ typedef union { * Package version */ uint32_t pkg_version:2; - /** reserved_1_136 : R; bitpos: [31:8]; default: 0; - * reserved + /** ocode : R; bitpos: [15:8]; default: 0; + * OCode calibration */ - uint32_t reserved_1_136:24; + uint32_t ocode:8; + /** active_hp_dbias : R; bitpos: [19:16]; default: 0; + * Active HP DBIAS of fixed voltage + */ + uint32_t active_hp_dbias:4; + /** active_lp_dbias : R; bitpos: [23:20]; default: 0; + * Active LP DBIAS of fixed voltage + */ + uint32_t active_lp_dbias:4; + /** lslp_hp_dbg : R; bitpos: [25:24]; default: 0; + * LSLP HP DBG of fixed voltage + */ + uint32_t lslp_hp_dbg:2; + /** lslp_hp_dbias : R; bitpos: [29:26]; default: 0; + * LSLP HP DBIAS of fixed voltage + */ + uint32_t lslp_hp_dbias:4; + /** dslp_lp_dbg : R; bitpos: [31:30]; default: 0; + * DSLP LP DBG of fixed voltage + */ + uint32_t dslp_lp_dbg:2; }; uint32_t val; } efuse_rd_mac_sys4_reg_t; @@ -668,10 +934,27 @@ typedef union { */ typedef union { struct { - /** sys_data_part0_2 : RO; bitpos: [31:0]; default: 0; - * Represents the third 32-bit of zeroth part of system data. + /** dslp_lp_dbg_1 : R; bitpos: [1:0]; default: 0; + * DSLP LP DBG of fixed voltage */ - uint32_t sys_data_part0_2:32; + uint32_t dslp_lp_dbg_1:2; + /** dslp_lp_dbias : R; bitpos: [6:2]; default: 0; + * DSLP LP DBIAS of fixed voltage + */ + uint32_t dslp_lp_dbias:5; + /** lp_hp_dbias_vol_gap : R; bitpos: [11:7]; default: 0; + * DBIAS gap between LP and HP + */ + uint32_t lp_hp_dbias_vol_gap:5; + /** pvt_dbias : R; bitpos: [15:12]; default: 0; + * PVT DBIAS + */ + uint32_t pvt_dbias:4; + /** reserved_1_176 : R; bitpos: [31:16]; default: 0; + * reserved + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t reserved_1_176:16; }; uint32_t val; } efuse_rd_mac_sys5_reg_t; @@ -735,10 +1018,23 @@ typedef union { */ typedef union { struct { - /** sys_data_part1_4 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of first part of system data. + /** temp_calibration : R; bitpos: [9:0]; default: 0; + * Temperature calibration */ - uint32_t sys_data_part1_4:32; + uint32_t temp_calibration:10; + /** spi_ldo_1v8_dref : R; bitpos: [13:10]; default: 0; + * SPI LDO 1.8 V DREF + */ + uint32_t spi_ldo_1v8_dref:4; + /** spi_ldo_1v8_mul : R; bitpos: [16:14]; default: 0; + * SPI LDO 1.8 V multiplier + */ + uint32_t spi_ldo_1v8_mul:3; + /** reserved_2_145 : R; bitpos: [31:17]; default: 0; + * reserved + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t reserved_2_145:15; }; uint32_t val; } efuse_rd_sys_part1_data4_reg_t; @@ -750,6 +1046,7 @@ typedef union { struct { /** sys_data_part1_5 : RO; bitpos: [31:0]; default: 0; * Represents the zeroth 32-bit of first part of system data. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t sys_data_part1_5:32; }; @@ -763,6 +1060,7 @@ typedef union { struct { /** sys_data_part1_6 : RO; bitpos: [31:0]; default: 0; * Represents the zeroth 32-bit of first part of system data. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t sys_data_part1_6:32; }; @@ -776,6 +1074,7 @@ typedef union { struct { /** sys_data_part1_7 : RO; bitpos: [31:0]; default: 0; * Represents the zeroth 32-bit of first part of system data. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t sys_data_part1_7:32; }; @@ -869,6 +1168,7 @@ typedef union { struct { /** reserved_3_192 : R; bitpos: [7:0]; default: 0; * reserved + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t reserved_3_192:8; /** custom_mac : R; bitpos: [31:8]; default: 0; @@ -890,6 +1190,7 @@ typedef union { uint32_t custom_mac_1:24; /** reserved_3_248 : R; bitpos: [31:24]; default: 0; * reserved + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t reserved_3_248:8; }; @@ -977,10 +1278,18 @@ typedef union { */ typedef union { struct { - /** sys_data_part2_0 : RO; bitpos: [31:0]; default: 0; - * Represents the zeroth 32-bit of second part of system data. + /** adc1_diff_k : R; bitpos: [10:0]; default: 0; + * Fitted slope (K) of ADC1 in differential mode */ - uint32_t sys_data_part2_0:32; + uint32_t adc1_diff_k:11; + /** adc1_diff_b : R; bitpos: [20:11]; default: 0; + * Intercept (B) of ADC1 in differential mode + */ + uint32_t adc1_diff_b:10; + /** adc1_p_k : R; bitpos: [31:21]; default: 0; + * Fitted slope (K) of ADC1 in P mode + */ + uint32_t adc1_p_k:11; }; uint32_t val; } efuse_rd_sys_part2_data0_reg_t; @@ -990,10 +1299,22 @@ typedef union { */ typedef union { struct { - /** sys_data_part2_1 : RO; bitpos: [31:0]; default: 0; - * Represents the first 32-bit of second part of system data. + /** adc1_p_b : R; bitpos: [9:0]; default: 0; + * Intercept (B) of ADC1 in P mode */ - uint32_t sys_data_part2_1:32; + uint32_t adc1_p_b:10; + /** adc1_n_k : R; bitpos: [20:10]; default: 0; + * Fitted slope (K) of ADC1 in N mode + */ + uint32_t adc1_n_k:11; + /** adc1_n_b : R; bitpos: [30:21]; default: 0; + * Intercept (B) of ADC1 in N mode + */ + uint32_t adc1_n_b:10; + /** adc2_diff_k : R; bitpos: [31]; default: 0; + * Fitted slope (K) of ADC2 in differential mode + */ + uint32_t adc2_diff_k:1; }; uint32_t val; } efuse_rd_sys_part2_data1_reg_t; @@ -1003,10 +1324,22 @@ typedef union { */ typedef union { struct { - /** sys_data_part2_2 : RO; bitpos: [31:0]; default: 0; - * Represents the second 32-bit of second part of system data. + /** adc2_diff_k_1 : R; bitpos: [9:0]; default: 0; + * Fitted slope (K) of ADC2 in differential mode */ - uint32_t sys_data_part2_2:32; + uint32_t adc2_diff_k_1:10; + /** adc2_diff_b : R; bitpos: [19:10]; default: 0; + * Intercept (B) of ADC2 in differential mode + */ + uint32_t adc2_diff_b:10; + /** adc2_p_k : R; bitpos: [30:20]; default: 0; + * Fitted slope (K) of ADC2 in P mode + */ + uint32_t adc2_p_k:11; + /** adc2_p_b : R; bitpos: [31]; default: 0; + * Intercept (B) of ADC2 in P mode + */ + uint32_t adc2_p_b:1; }; uint32_t val; } efuse_rd_sys_part2_data2_reg_t; @@ -1016,10 +1349,23 @@ typedef union { */ typedef union { struct { - /** sys_data_part2_3 : RO; bitpos: [31:0]; default: 0; - * Represents the third 32-bit of second part of system data. + /** adc2_p_b_1 : R; bitpos: [8:0]; default: 0; + * Intercept (B) of ADC2 in P mode */ - uint32_t sys_data_part2_3:32; + uint32_t adc2_p_b_1:9; + /** adc2_n_k : R; bitpos: [19:9]; default: 0; + * Fitted slope (K) of ADC2 in N mode + */ + uint32_t adc2_n_k:11; + /** adc2_n_b : R; bitpos: [29:20]; default: 0; + * Intercept (B) of ADC2 in N mode + */ + uint32_t adc2_n_b:10; + /** reserved_9_126 : R; bitpos: [31:30]; default: 0; + * reserved + * This field is only for internal debugging purposes. Do not use it in applications. + */ + uint32_t reserved_9_126:2; }; uint32_t val; } efuse_rd_sys_part2_data3_reg_t; @@ -1031,6 +1377,7 @@ typedef union { struct { /** sys_data_part2_4 : RO; bitpos: [31:0]; default: 0; * Represents the fourth 32-bit of second part of system data. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t sys_data_part2_4:32; }; @@ -1044,6 +1391,7 @@ typedef union { struct { /** sys_data_part2_5 : RO; bitpos: [31:0]; default: 0; * Represents the fifth 32-bit of second part of system data. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t sys_data_part2_5:32; }; @@ -1056,35 +1404,42 @@ typedef union { typedef union { struct { /** usb_device_exchg_pins : RO; bitpos: [0]; default: 0; - * Represents whether enable usb device exchange pins of D+ and D- or not. \\ 1: - * enabled\\ 0: disabled\\ + * Represents whether enable usb device exchange pins of D+ and D- or not. + * 1: enabled + * 0: disabled */ uint32_t usb_device_exchg_pins:1; /** usb_device_drefh : RO; bitpos: [2:1]; default: 0; * Represents the single-end input threshold vrefh, 1.76 V to 2 V with step of 80 mV. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t usb_device_drefh:2; /** usb_device_drefl : RO; bitpos: [4:3]; default: 0; * Represents the usb device single-end input low threshold, 0.8 V to 1.04 V with step * of 80 mV. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t usb_device_drefl:2; - /** rd_reserve_9_197 : RW; bitpos: [16:5]; default: 0; - * Reserved, it was created by set_missed_fields_in_regs func + /** reserved_9_197 : R; bitpos: [16:5]; default: 0; + * reserved + * This field is only for internal debugging purposes. Do not use it in applications. */ - uint32_t rd_reserve_9_197:12; + uint32_t reserved_9_197:12; /** pvt_0_cell_select : RO; bitpos: [23:17]; default: 0; * Power glitch monitor PVT cell select. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t pvt_0_cell_select:7; /** pvt_1_cell_select : RO; bitpos: [30:24]; default: 0; * Power glitch monitor PVT cell select. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t pvt_1_cell_select:7; - /** rd_reserve_9_223 : RW; bitpos: [31]; default: 0; - * Reserved, it was created by set_missed_fields_in_regs func + /** reserved_9_223 : R; bitpos: [31]; default: 0; + * reserved + * This field is only for internal debugging purposes. Do not use it in applications. */ - uint32_t rd_reserve_9_223:1; + uint32_t reserved_9_223:1; }; uint32_t val; } efuse_rd_sys_part2_data6_reg_t; @@ -1096,10 +1451,12 @@ typedef union { struct { /** pvt_0_limit : RO; bitpos: [15:0]; default: 0; * Power glitch monitor threthold. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t pvt_0_limit:16; /** pvt_1_limit : RO; bitpos: [31:16]; default: 0; * Power glitch monitor threthold. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t pvt_1_limit:16; }; @@ -1124,6 +1481,7 @@ typedef union { uint32_t dis_usb_jtag_err:1; /** dis_usb_serial_jtag_err : RO; bitpos: [11]; default: 0; * Represents the programming error of EFUSE_DIS_USB_SERIAL_JTAG + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t dis_usb_serial_jtag_err:1; /** dis_force_download_err : RO; bitpos: [12]; default: 0; @@ -1157,6 +1515,7 @@ typedef union { uint32_t reserved_21:1; /** dis_wifi6_err : RO; bitpos: [22]; default: 0; * Represents the programming error of EFUSE_DIS_WIFI6 + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t dis_wifi6_err:1; /** huk_gen_state_err : RO; bitpos: [27:23]; default: 0; @@ -1499,91 +1858,98 @@ typedef union { typedef union { struct { /** rd_mac_sys_err_num : RO; bitpos: [2:0]; default: 0; - * Represents the error number of registers.\\The value of this signal means the - * number of error bytes in rd_mac_sys + * Represents the error number of registers. + * The value of this signal means the number of error bytes in rd_mac_sys */ uint32_t rd_mac_sys_err_num:3; /** rd_mac_sys_fail : RO; bitpos: [3]; default: 0; - * Represents error status of register.\\0: Means no failure and that the data of - * rd_mac_sys is reliable\\ 1: Means that programming rd_mac_sys failed and the number - * of error bytes is over 6. + * Represents error status of register. + * 0: Means no failure and that the data of rd_mac_sys is reliable + * 1: Means that programming rd_mac_sys failed and the number of error bytes is over 6. */ uint32_t rd_mac_sys_fail:1; /** rd_sys_part1_data_err_num : RO; bitpos: [6:4]; default: 0; - * Represents the error number of registers.\\The value of this signal means the - * number of error bytes in rd_sys_part1_data + * Represents the error number of registers. + * The value of this signal means the number of error bytes in rd_sys_part1_data */ uint32_t rd_sys_part1_data_err_num:3; /** rd_sys_part1_data_fail : RO; bitpos: [7]; default: 0; - * Represents error status of register.\\0: Means no failure and that the data of - * rd_sys_part1_data is reliable\\ 1: Means that programming rd_sys_part1_data failed - * and the number of error bytes is over 6. + * Represents error status of register. + * 0: Means no failure and that the data of rd_sys_part1_data is reliable + * 1: Means that programming rd_sys_part1_data failed and the number of error bytes is + * over 6. */ uint32_t rd_sys_part1_data_fail:1; /** rd_usr_data_err_num : RO; bitpos: [10:8]; default: 0; - * Represents the error number of registers.\\The value of this signal means the - * number of error bytes in rd_usr_data + * Represents the error number of registers. + * The value of this signal means the number of error bytes in rd_usr_data */ uint32_t rd_usr_data_err_num:3; /** rd_usr_data_fail : RO; bitpos: [11]; default: 0; - * Represents error status of register.\\0: Means no failure and that the data of - * rd_usr_data is reliable\\ 1: Means that programming rd_usr_data failed and the - * number of error bytes is over 6. + * Represents error status of register. + * 0: Means no failure and that the data of rd_usr_data is reliable + * 1: Means that programming rd_usr_data failed and the number of error bytes is over + * 6. */ uint32_t rd_usr_data_fail:1; /** rd_key0_data_err_num : RO; bitpos: [14:12]; default: 0; - * Represents the error number of registers.\\The value of this signal means the - * number of error bytes in rd_key0_data + * Represents the error number of registers. + * The value of this signal means the number of error bytes in rd_key0_data */ uint32_t rd_key0_data_err_num:3; /** rd_key0_data_fail : RO; bitpos: [15]; default: 0; - * Represents error status of register.\\0: Means no failure and that the data of - * rd_key0_data is reliable\\ 1: Means that programming rd_key0_data failed and the - * number of error bytes is over 6. + * Represents error status of register. + * 0: Means no failure and that the data of rd_key0_data is reliable + * 1: Means that programming rd_key0_data failed and the number of error bytes is over + * 6. */ uint32_t rd_key0_data_fail:1; /** rd_key1_data_err_num : RO; bitpos: [18:16]; default: 0; - * Represents the error number of registers.\\The value of this signal means the - * number of error bytes in rd_key1_data + * Represents the error number of registers. + * The value of this signal means the number of error bytes in rd_key1_data */ uint32_t rd_key1_data_err_num:3; /** rd_key1_data_fail : RO; bitpos: [19]; default: 0; - * Represents error status of register.\\0: Means no failure and that the data of - * rd_key1_data is reliable\\ 1: Means that programming rd_key1_data failed and the - * number of error bytes is over 6. + * Represents error status of register. + * 0: Means no failure and that the data of rd_key1_data is reliable + * 1: Means that programming rd_key1_data failed and the number of error bytes is over + * 6. */ uint32_t rd_key1_data_fail:1; /** rd_key2_data_err_num : RO; bitpos: [22:20]; default: 0; - * Represents the error number of registers.\\The value of this signal means the - * number of error bytes in rd_key2_data + * Represents the error number of registers. + * The value of this signal means the number of error bytes in rd_key2_data */ uint32_t rd_key2_data_err_num:3; /** rd_key2_data_fail : RO; bitpos: [23]; default: 0; - * Represents error status of register.\\0: Means no failure and that the data of - * rd_key2_data is reliable\\ 1: Means that programming rd_key2_data failed and the - * number of error bytes is over 6. + * Represents error status of register. + * 0: Means no failure and that the data of rd_key2_data is reliable + * 1: Means that programming rd_key2_data failed and the number of error bytes is over + * 6. */ uint32_t rd_key2_data_fail:1; /** rd_key3_data_err_num : RO; bitpos: [26:24]; default: 0; - * Represents the error number of registers.\\The value of this signal means the - * number of error bytes in rd_key3_data + * Represents the error number of registers. + * The value of this signal means the number of error bytes in rd_key3_data */ uint32_t rd_key3_data_err_num:3; /** rd_key3_data_fail : RO; bitpos: [27]; default: 0; - * Represents error status of register.\\0: Means no failure and that the data of - * rd_key3_data is reliable\\ 1: Means that programming rd_key3_data failed and the - * number of error bytes is over 6. + * Represents error status of register. + * 0: Means no failure and that the data of rd_key3_data is reliable + * 1: Means that programming rd_key3_data failed and the number of error bytes is over + * 6. */ uint32_t rd_key3_data_fail:1; /** rd_key4_data_err_num : RO; bitpos: [30:28]; default: 0; - * Represents the error number of registers.\\The value of this signal means the - * number of error bytes in rd_key4_data + * Represents the error number of registers. + * The value of this signal means the number of error bytes in rd_key4_data */ uint32_t rd_key4_data_err_num:3; /** rd_key4_data_fail : RO; bitpos: [31]; default: 0; - * Represents error status of register.\\0: Means no failure and that the data of - * rd_key4_data is reliable\\ 1: Means that programming rd_key4_data failed and the - * number of error bytes is over 6. + * Represents error status of register. + * 0: Means no failure and that the data of rd_key4_data is reliable + * 1: Means that programming rd_key4_data failed and the number of error bytes is over + * 6. */ uint32_t rd_key4_data_fail:1; }; @@ -1596,14 +1962,15 @@ typedef union { typedef union { struct { /** rd_sys_part2_data_err_num : RO; bitpos: [2:0]; default: 0; - * Represents the error number of registers.\\The value of this signal means the - * number of error bytes in rd_sys_part2_data + * Represents the error number of registers. + * The value of this signal means the number of error bytes in rd_sys_part2_data */ uint32_t rd_sys_part2_data_err_num:3; /** rd_sys_part2_data_fail : RO; bitpos: [3]; default: 0; - * Represents error status of register.\\0: Means no failure and that the data of - * rd_sys_part2_data is reliable\\ 1: Means that programming rd_sys_part2_data failed - * and the number of error bytes is over 6. + * Represents error status of register. + * 0: Means no failure and that the data of rd_sys_part2_data is reliable + * 1: Means that programming rd_sys_part2_data failed and the number of error bytes is + * over 6. */ uint32_t rd_sys_part2_data_fail:1; uint32_t reserved_4:28; @@ -1636,22 +2003,28 @@ typedef union { typedef union { struct { /** mem_force_pd : R/W; bitpos: [0]; default: 0; - * Configures whether to force power down eFuse SRAM.\\ 1: Force\\ 0: No effect\\ + * Configures whether to force power down eFuse SRAM. + * 1: Force + * 0: No effect */ uint32_t mem_force_pd:1; /** mem_clk_force_on : R/W; bitpos: [1]; default: 1; - * Configures whether to force activate clock signal of eFuse SRAM.\\ 1: Force - * activate\\ 0: No effect\\ + * Configures whether to force activate clock signal of eFuse SRAM. + * 1: Force activate + * 0: No effect */ uint32_t mem_clk_force_on:1; /** mem_force_pu : R/W; bitpos: [2]; default: 0; - * Configures whether to force power up eFuse SRAM.\\ 1: Force\\ 0: No effect\\ + * Configures whether to force power up eFuse SRAM. + * 1: Force + * 0: No effect */ uint32_t mem_force_pu:1; uint32_t reserved_3:13; /** clk_en : R/W; bitpos: [16]; default: 0; - * Configures whether to force enable eFuse register configuration clock signal.\\ 1: - * Force\\ 0: The clock is enabled only during the reading and writing of registers\\ + * Configures whether to force enable eFuse register configuration clock signal. + * 1: Force + * 0: The clock is enabled only during the reading and writing of registers */ uint32_t clk_en:1; uint32_t reserved_17:15; @@ -1667,8 +2040,10 @@ typedef union { typedef union { struct { /** op_code : R/W; bitpos: [15:0]; default: 0; - * Configures operation command type.\\ 0x5A5A: Program operation command\\ 0x5AA5: - * Read operation command\\ Other values: No effect\\ + * Configures operation command type. + * 0x5A5A: Program operation command + * 0x5AA5: Read operation command + * Other values: No effect */ uint32_t op_code:16; uint32_t reserved_16:16; @@ -1697,8 +2072,9 @@ typedef union { */ uint32_t dac_num:8; /** oe_clr : R/W; bitpos: [17]; default: 0; - * Configures whether to reduce the power supply of programming voltage.\\ 0: Not - * reduce\\ 1: Reduce\\ + * Configures whether to reduce the power supply of programming voltage. + * 0: Not reduce + * 1: Reduce */ uint32_t oe_clr:1; uint32_t reserved_18:14; @@ -1785,8 +2161,9 @@ typedef union { typedef union { struct { /** bypass_rs_correction : R/W; bitpos: [0]; default: 0; - * Configures whether to bypass the Reed-Solomon (RS) correction step.\\ 0: Not - * bypass\\ 1: Bypass\\ + * Configures whether to bypass the Reed-Solomon (RS) correction step. + * 0: Not bypass + * 1: Bypass */ uint32_t bypass_rs_correction:1; /** bypass_rs_blk_num : R/W; bitpos: [11:1]; default: 0; @@ -1794,8 +2171,9 @@ typedef union { */ uint32_t bypass_rs_blk_num:11; /** update : WT; bitpos: [12]; default: 0; - * Configures whether to update multi-bit register signals.\\ 1: Update\\ 0: No - * effect\\ + * Configures whether to update multi-bit register signals. + * 1: Update + * 0: No effect */ uint32_t update:1; /** tpgm_inactive : R/W; bitpos: [20:13]; default: 1; @@ -1859,32 +2237,40 @@ typedef union { typedef union { struct { /** state : RO; bitpos: [3:0]; default: 0; - * Represents the state of the eFuse state machine.\\ 0: Reset state, the initial - * state after power-up\\ 1: Idle state\\ Other values: Non-idle state\\ + * Represents the state of the eFuse state machine. + * 0: Reset state, the initial state after power-up + * 1: Idle state + * Other values: Non-idle state */ uint32_t state:4; /** otp_load_sw : RO; bitpos: [4]; default: 0; * Represents the value of OTP_LOAD_SW. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t otp_load_sw:1; /** otp_vddq_c_sync2 : RO; bitpos: [5]; default: 0; * Represents the value of OTP_VDDQ_C_SYNC2. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t otp_vddq_c_sync2:1; /** otp_strobe_sw : RO; bitpos: [6]; default: 0; * Represents the value of OTP_STROBE_SW. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t otp_strobe_sw:1; /** otp_csb_sw : RO; bitpos: [7]; default: 0; * Represents the value of OTP_CSB_SW. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t otp_csb_sw:1; /** otp_pgenb_sw : RO; bitpos: [8]; default: 0; * Represents the value of OTP_PGENB_SW. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t otp_pgenb_sw:1; /** otp_vddq_is_sw : RO; bitpos: [9]; default: 0; * Represents the value of OTP_VDDQ_IS_SW. + * This field is only for internal debugging purposes. Do not use it in applications. */ uint32_t otp_vddq_is_sw:1; /** blk0_valid_bit_cnt : RO; bitpos: [19:10]; default: 0; @@ -1904,11 +2290,15 @@ typedef union { typedef union { struct { /** read_cmd : R/W/SC; bitpos: [0]; default: 0; - * Configures whether to send read commands.\\ 1: Send\\ 0: No effect\\ + * Configures whether to send read commands. + * 1: Send + * 0: No effect */ uint32_t read_cmd:1; /** pgm_cmd : R/W/SC; bitpos: [1]; default: 0; - * Configures whether to send programming commands.\\ 1: Send\\ 0: No effect\\ + * Configures whether to send programming commands. + * 1: Send + * 0: No effect */ uint32_t pgm_cmd:1; /** blk_num : R/W; bitpos: [5:2]; default: 0;