feat(dac): use default clock source for zero config

2026-10-02 11:10:54 +03:00 · 2026-08-28 10:16:31 +08:00
parent 43e6da1796
commit b8e9a18e95
9 changed files with 26 additions and 49 deletions
@@ -83,7 +83,6 @@ void app_main(void)
        .desc_num = 4,
        .buf_size = 2048,
        .freq_hz = CONFIG_EXAMPLE_AUDIO_SAMPLE_RATE,
-        .offset = 0,
        .clk_src = DAC_DIGI_CLK_SRC_APLL,   // Using APLL as clock source to get a wider frequency range
        /* Assume the data in buffer is 'A B C D E F'
         * DAC_CHANNEL_MODE_SIMUL: