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feat(dac): use default clock source for zero config

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morris
2026-08-28 10:16:31 +08:00
parent 43e6da1796
commit b8e9a18e95
9 changed files with 26 additions and 49 deletions
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components/esp_driver_dac/test_apps/dac/main/test_dac.c
-20
View File
@@ -59,8 +59,6 @@ TEST_CASE("DAC_API_basic_logic_test", "[dac]")
dac_cosine_config_t cos0_cfg = {
.chan_id = DAC_CHAN_0,
.freq_hz = 1000, // It will be covered by 8000 in the latter configuration
.clk_src = DAC_COSINE_CLK_SRC_DEFAULT,
.offset = 0,
.phase = DAC_COSINE_PHASE_0,
.atten = DAC_COSINE_ATTEN_DEFAULT,
.flags.force_set_freq = false,
@@ -68,8 +66,6 @@ TEST_CASE("DAC_API_basic_logic_test", "[dac]")
dac_cosine_config_t cos1_cfg = {
.chan_id = DAC_CHAN_1,
.freq_hz = 8000,
.clk_src = DAC_COSINE_CLK_SRC_DEFAULT,
.offset = 0,
.phase = DAC_COSINE_PHASE_180,
.atten = DAC_COSINE_ATTEN_DB_6,
.flags.force_set_freq = false,
@@ -96,8 +92,6 @@ TEST_CASE("DAC_API_basic_logic_test", "[dac]")
.desc_num = 8,
.buf_size = 2048,
.freq_hz = 48000,
.offset = 0,
.clk_src = DAC_DIGI_CLK_SRC_DEFAULT,
.chan_mode = DAC_CHANNEL_MODE_SIMUL,
};
/* DMA peripheral availability test */
@@ -129,8 +123,6 @@ TEST_CASE("DAC_memory_leak_test", "[dac]")
.desc_num = 8,
.buf_size = 2048,
.freq_hz = 48000,
.offset = 0,
.clk_src = DAC_DIGI_CLK_SRC_DEFAULT,
.chan_mode = DAC_CHANNEL_MODE_SIMUL,
};
size_t len = 1024;
@@ -206,8 +198,6 @@ TEST_CASE("DAC_dma_write_test", "[dac]")
.desc_num = 8,
.buf_size = 1024,
.freq_hz = 48000,
.offset = 0,
.clk_src = DAC_DIGI_CLK_SRC_DEFAULT,
.chan_mode = DAC_CHANNEL_MODE_SIMUL,
};
size_t len = 520; // To test if the driver can work correctly with uncommon length
@@ -244,8 +234,6 @@ TEST_CASE("DAC_dma_sync_write_resume_test", "[dac]")
.desc_num = 4,
.buf_size = 256,
.freq_hz = 48000,
.offset = 0,
.clk_src = DAC_DIGI_CLK_SRC_DEFAULT,
.chan_mode = DAC_CHANNEL_MODE_SIMUL,
};
@@ -316,8 +304,6 @@ TEST_CASE("DAC_dma_convert_frequency_test", "[dac]")
.desc_num = 8,
.buf_size = 2048,
.freq_hz = 20000,
.offset = 0,
.clk_src = DAC_DIGI_CLK_SRC_DEFAULT,
.chan_mode = DAC_CHANNEL_MODE_SIMUL,
};
TEST_ESP_OK(dac_continuous_new_channels(&cont_cfg, &cont_handle));
@@ -373,8 +359,6 @@ TEST_CASE("DAC_cosine_wave_test", "[dac]")
dac_cosine_config_t cos0_cfg = {
.chan_id = DAC_CHAN_0,
.freq_hz = 1000, // It will be covered by 8000 in the latter configuration
.clk_src = DAC_COSINE_CLK_SRC_DEFAULT,
.offset = 0,
.phase = DAC_COSINE_PHASE_0,
.atten = DAC_COSINE_ATTEN_DEFAULT,
.flags.force_set_freq = false,
@@ -382,8 +366,6 @@ TEST_CASE("DAC_cosine_wave_test", "[dac]")
dac_cosine_config_t cos1_cfg = {
.chan_id = DAC_CHAN_1,
.freq_hz = 1000,
.clk_src = DAC_COSINE_CLK_SRC_DEFAULT,
.offset = 0,
.phase = DAC_COSINE_PHASE_180,
.atten = DAC_COSINE_ATTEN_DB_6,
.flags.force_set_freq = false,
@@ -452,8 +434,6 @@ TEST_CASE("DAC_continuous_mode_concurrency_test", "[dac]")
.desc_num = 8,
.buf_size = 1024,
.freq_hz = 48000,
.offset = 0,
.clk_src = DAC_DIGI_CLK_SRC_DEFAULT,
.chan_mode = DAC_CHANNEL_MODE_SIMUL,
};
components/esp_driver_dac/test_apps/dac/main/test_dac_iram.c
-2
View File
@@ -68,8 +68,6 @@ TEST_CASE("DAC_IRAM_safe_test", "[dac]")
.desc_num = 8,
.buf_size = 2048,
.freq_hz = 40000,
.offset = 0,
.clk_src = DAC_DIGI_CLK_SRC_DEFAULT, // If the frequency is out of range, try 'DAC_DIGI_CLK_SRC_APLL'
/* Assume the data in buffer is 'A B C D E F'
* DAC_CHANNEL_MODE_SIMUL:
* - channel 0: A B C D E F