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feat(dac): use default clock source for zero config

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morris
2026-08-28 10:16:31 +08:00
parent 43e6da1796
commit b8e9a18e95
9 changed files with 26 additions and 49 deletions
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components/esp_driver_dac/include/driver/dac_continuous.h
+2 -3
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@@ -43,9 +43,8 @@ typedef struct {
* Typically not suggest to set the frequency higher than 2 MHz, otherwise the severe distortion will appear
*/
int8_t offset; /*!< The offset of the DAC digital data. Range -128~127 */
dac_continuous_digi_clk_src_t clk_src; /*!< The clock source of digital controller, which can affect the range of supported frequency
* Currently `DAC_DIGI_CLK_SRC_DEFAULT` and `DAC_DIGI_CLK_SRC_APLL` are available
*/
dac_continuous_digi_clk_src_t clk_src; /*!< The clock source of digital controller, which can affect the range of supported frequency.
Set to 0 to use `DAC_DIGI_CLK_SRC_DEFAULT`.*/
dac_continuous_channel_mode_t chan_mode; /*!< The channel mode of continuous mode, only take effect when multiple channels enabled, depends converting the buffer alternately or simultaneously */
} dac_continuous_config_t;
components/esp_driver_dac/include/driver/dac_cosine.h
+2 -1
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@@ -30,7 +30,8 @@ typedef struct {
* the waveform will distort at high frequency due to the hardware limitation.
* Typically not suggest to set the frequency higher than 200 KHz
*/
dac_cosine_clk_src_t clk_src; /*!< The clock source of the cosine wave generator, currently only support `DAC_COSINE_CLK_SRC_DEFAULT` */
dac_cosine_clk_src_t clk_src; /*!< The clock source of the cosine wave generator.
Set to 0 to use `DAC_COSINE_CLK_SRC_DEFAULT`. */
dac_cosine_atten_t atten; /*!< The attenuation of cosine wave amplitude */
dac_cosine_phase_t phase; /*!< The phase of cosine wave, can only support DAC_COSINE_PHASE_0 or DAC_COSINE_PHASE_180, default as 0 while setting an unsupported phase */
int8_t offset; /*!< The DC offset of cosine wave */