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refactor(parlio): refactor of the private parlio caps
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@@ -815,18 +815,6 @@ config SOC_MCPWM_SUPPORT_SLEEP_RETENTION
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bool
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default y
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config SOC_PARLIO_GROUPS
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int
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default 1
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config SOC_PARLIO_TX_UNITS_PER_GROUP
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int
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default 1
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config SOC_PARLIO_RX_UNITS_PER_GROUP
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int
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default 1
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config SOC_PARLIO_TX_UNIT_MAX_DATA_WIDTH
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int
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default 8
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@@ -843,14 +831,6 @@ config SOC_PARLIO_RX_CLK_SUPPORT_GATING
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bool
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default y
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config SOC_PARLIO_RX_CLK_SUPPORT_OUTPUT
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bool
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default y
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config SOC_PARLIO_TRANS_BIT_ALIGN
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bool
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default y
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config SOC_PARLIO_TX_SUPPORT_LOOP_TRANSMISSION
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bool
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default y
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@@ -346,15 +346,10 @@
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// #define SOC_USB_SERIAL_JTAG_SUPPORT_LIGHT_SLEEP (1) /*!< Support to maintain minimum usb communication during light sleep */ // TODO: IDF-6395
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/*-------------------------- PARLIO CAPS --------------------------------------*/
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#define SOC_PARLIO_GROUPS 1U /*!< Number of parallel IO peripherals */
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#define SOC_PARLIO_TX_UNITS_PER_GROUP 1U /*!< number of TX units in each group */
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#define SOC_PARLIO_RX_UNITS_PER_GROUP 1U /*!< number of RX units in each group */
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#define SOC_PARLIO_TX_UNIT_MAX_DATA_WIDTH 8 /*!< Number of data lines of the TX unit */
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#define SOC_PARLIO_RX_UNIT_MAX_DATA_WIDTH 8 /*!< Number of data lines of the RX unit */
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#define SOC_PARLIO_TX_CLK_SUPPORT_GATING 1 /*!< Support gating TX clock */
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#define SOC_PARLIO_RX_CLK_SUPPORT_GATING 1 /*!< Support gating RX clock */
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#define SOC_PARLIO_RX_CLK_SUPPORT_OUTPUT 1 /*!< Support output RX clock to a GPIO */
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#define SOC_PARLIO_TRANS_BIT_ALIGN 1 /*!< Support bit alignment in transaction */
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#define SOC_PARLIO_TX_SUPPORT_LOOP_TRANSMISSION 1 /*!< Support loop transmission. Note, 1 data-width loop transmission only avliable in chip version above 1.2 */
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#define SOC_PARLIO_SUPPORT_SLEEP_RETENTION 1 /*!< Support back up registers before sleep */
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