Mirrors/esp-idf
1
0
Fork 0
mirror of https://github.com/espressif/esp-idf.git synced 2026-10-02 03:00:34 +03:00
Code Issues Packages Projects Releases Wiki Activity

refactor(i2c): cleanup I2C definitions in soc_caps.h

Browse Source
This commit is contained in:
Chen Chen
2026-01-13 17:29:23 +08:00
parent b685c0e733
commit b7e82de9d8
46 changed files with 342 additions and 591 deletions
Download Patch File Download Diff File Expand all files Collapse all files
components/soc/esp32s2/include/soc/Kconfig.soc_caps.in
+6 -18
View File
@@ -419,13 +419,13 @@ config SOC_HP_I2C_NUM
int
default 2
config SOC_I2C_FIFO_LEN
int
default 32
config SOC_I2C_SUPPORT_REF_TICK
bool
default y
config SOC_I2C_CMD_REG_NUM
int
default 16
config SOC_I2C_SUPPORT_APB
bool
default y
config SOC_I2C_SUPPORT_SLAVE
bool
@@ -435,18 +435,6 @@ config SOC_I2C_SLAVE_CAN_GET_STRETCH_CAUSE
bool
default y
config SOC_I2C_SUPPORT_HW_CLR_BUS
bool
default y
config SOC_I2C_SUPPORT_REF_TICK
bool
default y
config SOC_I2C_SUPPORT_APB
bool
default y
config SOC_I2S_HW_VERSION_1
bool
default y
components/soc/esp32s2/include/soc/soc_caps.h
+7 -14
View File
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2020-2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2020-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -190,21 +190,14 @@
#define SOC_DEDIC_GPIO_HAS_INTERRUPT (1) /*!< Dedicated GPIO has its own interrupt source */
/*-------------------------- I2C CAPS ----------------------------------------*/
// ESP32-S2 has 2 I2C
#define SOC_I2C_NUM (2U)
#define SOC_HP_I2C_NUM (2U)
#define SOC_I2C_NUM (2U)
#define SOC_HP_I2C_NUM (2U)
#define SOC_I2C_FIFO_LEN (32) /*!< I2C hardware FIFO depth */
#define SOC_I2C_CMD_REG_NUM (16) /*!< Number of I2C command registers */
#define SOC_I2C_SUPPORT_SLAVE (1)
#define SOC_I2C_SLAVE_CAN_GET_STRETCH_CAUSE (1)
#define SOC_I2C_SUPPORT_REF_TICK (1)
#define SOC_I2C_SUPPORT_APB (1)
// FSM_RST only resets the FSM, not using it. So SOC_I2C_SUPPORT_HW_FSM_RST not defined.
//ESP32-S2 support hardware clear bus
#define SOC_I2C_SUPPORT_HW_CLR_BUS (1)
#define SOC_I2C_SUPPORT_REF_TICK (1)
#define SOC_I2C_SUPPORT_APB (1)
#define SOC_I2C_SUPPORT_SLAVE (1)
#define SOC_I2C_SLAVE_CAN_GET_STRETCH_CAUSE (1)
/*-------------------------- I2S CAPS ----------------------------------------*/
// ESP32-S2 has 1 I2S