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synced 2026-10-03 03:31:41 +03:00
refactor(i2c): cleanup I2C definitions in soc_caps.h
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@@ -651,21 +651,9 @@ config SOC_HP_I2C_NUM
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int
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default 1
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config SOC_I2C_FIFO_LEN
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config SOC_LP_I2C_NUM
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int
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default 32
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config SOC_I2C_CMD_REG_NUM
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int
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default 8
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config SOC_I2C_SUPPORT_SLAVE
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bool
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default y
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config SOC_I2C_SUPPORT_HW_FSM_RST
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bool
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default y
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default 1
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config SOC_I2C_SUPPORT_XTAL
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bool
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@@ -679,6 +667,10 @@ config SOC_I2C_SUPPORT_10BIT_ADDR
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bool
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default y
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config SOC_I2C_SUPPORT_SLAVE
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bool
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default y
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config SOC_I2C_SLAVE_SUPPORT_BROADCAST
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bool
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default y
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@@ -687,26 +679,10 @@ config SOC_I2C_SLAVE_CAN_GET_STRETCH_CAUSE
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bool
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default y
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config SOC_I2C_SLAVE_SUPPORT_I2CRAM_ACCESS
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bool
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default y
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config SOC_I2C_SLAVE_SUPPORT_SLAVE_UNMATCH
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bool
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default y
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config SOC_I2C_SUPPORT_SLEEP_RETENTION
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bool
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default y
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config SOC_LP_I2C_NUM
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int
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default 1
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config SOC_LP_I2C_FIFO_LEN
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int
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default 16
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config SOC_I2S_HW_VERSION_2
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bool
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default y
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@@ -1,5 +1,5 @@
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/*
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* SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2023-2026 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@@ -268,29 +268,19 @@
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#define SOC_ANA_CMPR_SUPPORT_ETM (1)
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/*-------------------------- I2C CAPS ----------------------------------------*/
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#define SOC_I2C_NUM (2U)
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#define SOC_HP_I2C_NUM (1U)
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#define SOC_I2C_NUM (2U)
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#define SOC_HP_I2C_NUM (1U)
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#define SOC_LP_I2C_NUM (1U)
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#define SOC_I2C_FIFO_LEN (32) /*!< I2C hardware FIFO depth */
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#define SOC_I2C_CMD_REG_NUM (8) /*!< Number of I2C command registers */
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#define SOC_I2C_SUPPORT_SLAVE (1)
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#define SOC_I2C_SUPPORT_XTAL (1)
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#define SOC_I2C_SUPPORT_RTC (1)
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#define SOC_I2C_SUPPORT_10BIT_ADDR (1)
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#define SOC_I2C_SUPPORT_HW_FSM_RST (1)
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#define SOC_I2C_SUPPORT_XTAL (1)
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#define SOC_I2C_SUPPORT_RTC (1)
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#define SOC_I2C_SUPPORT_10BIT_ADDR (1)
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#define SOC_I2C_SLAVE_SUPPORT_BROADCAST (1)
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#define SOC_I2C_SLAVE_CAN_GET_STRETCH_CAUSE (1)
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#define SOC_I2C_SLAVE_SUPPORT_I2CRAM_ACCESS (1)
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#define SOC_I2C_SLAVE_SUPPORT_SLAVE_UNMATCH (1)
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#define SOC_I2C_SUPPORT_SLAVE (1)
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#define SOC_I2C_SLAVE_SUPPORT_BROADCAST (1)
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#define SOC_I2C_SLAVE_CAN_GET_STRETCH_CAUSE (1)
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#define SOC_I2C_SUPPORT_SLEEP_RETENTION (1)
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/*-------------------------- LP_I2C CAPS -------------------------------------*/
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// ESP32-C5 has 1 LP_I2C
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#define SOC_LP_I2C_NUM (1U)
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#define SOC_LP_I2C_FIFO_LEN (16) /*!< LP_I2C hardware FIFO depth */
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#define SOC_I2C_SUPPORT_SLEEP_RETENTION (1)
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/*-------------------------- I2S CAPS ----------------------------------------*/
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#define SOC_I2S_HW_VERSION_2 (1)
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