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Merge branch 'feature/esp32c5_efuse_calib_update' into 'master'

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feat(efuse): Adds efuse calibration field for esp32c5

Closes IDF-15574

See merge request espressif/esp-idf!47701
This commit is contained in:
Konstantin Kondrashov
2026-04-20 16:31:05 +03:00
parent 52edbc934d ea6b477da4
commit b43ee27ebc
5 changed files with 47 additions and 14 deletions
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components/soc/esp32c5/register/soc/efuse_reg.h
+13 -6
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@@ -1,5 +1,5 @@
/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0 OR MIT
*/
@@ -1238,13 +1238,20 @@ extern "C" {
#define EFUSE_ADC1_CH5_ATTEN0_INITCODE_DIFF_M (EFUSE_ADC1_CH5_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC1_CH5_ATTEN0_INITCODE_DIFF_S)
#define EFUSE_ADC1_CH5_ATTEN0_INITCODE_DIFF_V 0x0000000FU
#define EFUSE_ADC1_CH5_ATTEN0_INITCODE_DIFF_S 21
/** EFUSE_RESERVED_2_249 : R; bitpos: [31:25]; default: 0;
/** EFUSE_PVT_DBIAS : R; bitpos: [29:25]; default: 0;
* Average initcode of ADC1 atten0
*/
#define EFUSE_PVT_DBIAS 0x0000001FU
#define EFUSE_PVT_DBIAS_M (EFUSE_PVT_DBIAS_V << EFUSE_PVT_DBIAS_S)
#define EFUSE_PVT_DBIAS_V 0x0000001FU
#define EFUSE_PVT_DBIAS_S 25
/** EFUSE_RESERVED_2_254 : R; bitpos: [31:30]; default: 0;
* reserved
*/
#define EFUSE_RESERVED_2_249 0x0000007FU
#define EFUSE_RESERVED_2_249_M (EFUSE_RESERVED_2_249_V << EFUSE_RESERVED_2_249_S)
#define EFUSE_RESERVED_2_249_V 0x0000007FU
#define EFUSE_RESERVED_2_249_S 25
#define EFUSE_RESERVED_2_254 0x00000003U
#define EFUSE_RESERVED_2_254_M (EFUSE_RESERVED_2_254_V << EFUSE_RESERVED_2_254_S)
#define EFUSE_RESERVED_2_254_V 0x00000003U
#define EFUSE_RESERVED_2_254_S 30
/** EFUSE_RD_USR_DATA0_REG register
* Represents rd_usr_data0
components/soc/esp32c5/register/soc/efuse_struct.h
+7 -3
View File
@@ -1,5 +1,5 @@
/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0 OR MIT
*/
@@ -863,10 +863,14 @@ typedef union {
* Gap between ADC1 CH5 and average initcode
*/
uint32_t adc1_ch5_atten0_initcode_diff:4;
/** reserved_2_249 : R; bitpos: [31:25]; default: 0;
/** pvt_dbias : R; bitpos: [29:25]; default: 0;
* Average initcode of ADC1 atten0
*/
uint32_t pvt_dbias:5;
/** reserved_2_254 : R; bitpos: [31:30]; default: 0;
* reserved
*/
uint32_t reserved_2_249:7;
uint32_t reserved_2_254:2;
};
uint32_t val;
} efuse_rd_sys_part1_data7_reg_t;