diff --git a/components/bootloader/Kconfig.projbuild b/components/bootloader/Kconfig.projbuild index 4c75181f8f7..8d27927acc8 100644 --- a/components/bootloader/Kconfig.projbuild +++ b/components/bootloader/Kconfig.projbuild @@ -1136,8 +1136,9 @@ menu "Security features" config SECURE_FLASH_PSEUDO_ROUND_FUNC bool "Permanently enable XTS-AES's pseudo rounds function" - default y - depends on SECURE_FLASH_ENCRYPTION_MODE_RELEASE && SOC_FLASH_ENCRYPTION_XTS_AES_SUPPORT_PSEUDO_ROUND + default y if SECURE_FLASH_ENCRYPTION_MODE_RELEASE + default n + depends on SECURE_FLASH_ENC_ENABLED && SOC_FLASH_ENCRYPTION_XTS_AES_SUPPORT_PSEUDO_ROUND help If set (default), the bootloader will permanently enable the XTS-AES peripheral's pseudo rounds function. Note: Enabling this config would burn an efuse. diff --git a/components/bootloader_support/src/esp32h2/flash_encryption_secure_features.c b/components/bootloader_support/src/esp32h2/flash_encryption_secure_features.c index d4b063a4d6b..bb3517616ed 100644 --- a/components/bootloader_support/src/esp32h2/flash_encryption_secure_features.c +++ b/components/bootloader_support/src/esp32h2/flash_encryption_secure_features.c @@ -36,7 +36,7 @@ esp_err_t esp_flash_encryption_enable_secure_features(void) esp_efuse_write_field_bit(ESP_EFUSE_DIS_DIRECT_BOOT); -#if defined(CONFIG_SECURE_FLASH_ENCRYPTION_MODE_RELEASE) && defined(SOC_FLASH_ENCRYPTION_XTS_AES_SUPPORT_PSEUDO_ROUND) +#if defined(CONFIG_SECURE_FLASH_PSEUDO_ROUND_FUNC) if (spi_flash_encrypt_ll_is_pseudo_rounds_function_supported()) { ESP_LOGI(TAG, "Enable XTS-AES pseudo rounds function..."); uint8_t xts_pseudo_level = CONFIG_SECURE_FLASH_PSEUDO_ROUND_FUNC_STRENGTH; diff --git a/components/bootloader_support/src/flash_encrypt.c b/components/bootloader_support/src/flash_encrypt.c index 381f17ed40e..dcfc5798a2b 100644 --- a/components/bootloader_support/src/flash_encrypt.c +++ b/components/bootloader_support/src/flash_encrypt.c @@ -210,13 +210,6 @@ void esp_flash_encryption_set_release_mode(void) #endif // CONFIG_SOC_FLASH_ENCRYPTION_XTS_AES_128_DERIVED #endif // !CONFIG_IDF_TARGET_ESP32 -#ifdef SOC_FLASH_ENCRYPTION_XTS_AES_SUPPORT_PSEUDO_ROUND - if (spi_flash_encrypt_ll_is_pseudo_rounds_function_supported()) { - uint8_t xts_pseudo_level = ESP_XTS_AES_PSEUDO_ROUNDS_LOW; - esp_efuse_write_field_blob(ESP_EFUSE_XTS_DPA_PSEUDO_LEVEL, &xts_pseudo_level, ESP_EFUSE_XTS_DPA_PSEUDO_LEVEL[0]->bit_count); - } -#endif - #ifdef CONFIG_IDF_TARGET_ESP32 esp_efuse_write_field_bit(ESP_EFUSE_WR_DIS_DIS_CACHE); #else diff --git a/components/esp_security/src/init.c b/components/esp_security/src/init.c index 11d01f89d91..51adb01edf6 100644 --- a/components/esp_security/src/init.c +++ b/components/esp_security/src/init.c @@ -42,6 +42,8 @@ ESP_SYSTEM_INIT_FN(esp_security_init, SECONDARY, BIT(0), 103) esp_crypto_dpa_protection_startup(); #endif + esp_err_t err = ESP_FAIL; + #if CONFIG_ESP_CRYPTO_FORCE_ECC_CONSTANT_TIME_POINT_MUL bool force_constant_time = true; #if CONFIG_IDF_TARGET_ESP32H2 @@ -51,7 +53,7 @@ ESP_SYSTEM_INIT_FN(esp_security_init, SECONDARY, BIT(0), 103) #endif if (!esp_efuse_read_field_bit(ESP_EFUSE_ECC_FORCE_CONST_TIME) && force_constant_time) { ESP_EARLY_LOGD(TAG, "Forcefully enabling ECC constant time operations"); - esp_err_t err = esp_efuse_write_field_bit(ESP_EFUSE_ECC_FORCE_CONST_TIME); + err = esp_efuse_write_field_bit(ESP_EFUSE_ECC_FORCE_CONST_TIME); if (err != ESP_OK) { ESP_EARLY_LOGE(TAG, "Enabling ECC constant time operations forcefully failed."); return err; @@ -60,14 +62,14 @@ ESP_SYSTEM_INIT_FN(esp_security_init, SECONDARY, BIT(0), 103) #endif #if CONFIG_ESP_ECDSA_ENABLE_P192_CURVE - esp_err_t err; err = esp_efuse_enable_ecdsa_p192_curve_mode(); if (err != ESP_OK) { return err; } #endif - return ESP_OK; + err = ESP_OK; + return err; } void esp_security_init_include_impl(void)