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feat(esp32p4): support rev3 on fpga

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This commit is contained in:
armando
2025-10-13 15:24:14 +08:00
parent 7863b3c419
commit b3fd689da9
34 changed files with 2005 additions and 76 deletions
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components/riscv/include/esp_private/interrupt_clic.h
+3 -3
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@@ -46,7 +46,7 @@ extern "C" {
#define MTVT_CSR 0x307
#if CONFIG_IDF_TARGET_ESP32P4
#if CONFIG_IDF_TARGET_ESP32P4 && CONFIG_ESP32P4_SELECTS_REV_LESS_V2
/**
* The ESP32-P4 and the beta version of the ESP32-C5 implement a non-standard version of the CLIC:
@@ -56,9 +56,9 @@ extern "C" {
#define INTTHRESH_STANDARD 0
#define MINTSTATUS_CSR 0x346
#elif CONFIG_IDF_TARGET_ESP32C5 || CONFIG_IDF_TARGET_ESP32C61
#elif CONFIG_IDF_TARGET_ESP32C5 || CONFIG_IDF_TARGET_ESP32C61 || !CONFIG_ESP32P4_SELECTS_REV_LESS_V2
/* The ESP32-C5 (MP) and C61 use the standard CLIC specification, for example, it defines the mintthresh CSR */
/* The ESP32-C5 (MP), C61 and P4 (since REV2) use the standard CLIC specification, for example, it defines the mintthresh CSR */
#define INTTHRESH_STANDARD 1
#define MINTSTATUS_CSR 0xFB1
#define MINTTHRESH_CSR 0x347