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Merge branch 'feature/esp32s31_ppa_support' into 'master'

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feat(ppa): add support for ESP32S31

Closes IDF-14769

See merge request espressif/esp-idf!47281
This commit is contained in:
Song Ruo Jing
2026-04-24 15:43:38 +08:00
parent 0aa8b1ce13 d2b2578244
commit b18f90cd82
42 changed files with 1988 additions and 484 deletions
Download Patch File Download Diff File Expand all files Collapse all files
components/soc/esp32s31/include/soc/Kconfig.soc_caps.in
+4
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@@ -215,6 +215,10 @@ config SOC_TOUCH_SENSOR_SUPPORTED
bool
default y
config SOC_PPA_SUPPORTED
bool
default y
config SOC_MODEM_CLOCK_SUPPORTED
bool
default y
components/soc/esp32s31/include/soc/soc_caps.h
+1 -1
View File
@@ -96,7 +96,7 @@
#define SOC_SPI_FLASH_SUPPORTED 1 // TODO: [ESP32S31] IDF-14777
#define SOC_TOUCH_SENSOR_SUPPORTED 1
// #define SOC_RNG_SUPPORTED 1 // TODO: [ESP32S31] IDF-14632
// #define SOC_PPA_SUPPORTED 1 // TODO: [ESP32S31] IDF-14769
#define SOC_PPA_SUPPORTED 1
// #define SOC_LIGHT_SLEEP_SUPPORTED 1 // TODO: [ESP32S31] IDF-14645
// #define SOC_DEEP_SLEEP_SUPPORTED 1 // TODO: [ESP32S31] IDF-14643
#define SOC_MODEM_CLOCK_SUPPORTED 1
components/soc/esp32s31/register/soc/ppa_reg.h
+21 -21
View File
@@ -1,5 +1,5 @@
/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0 OR MIT
*/
@@ -272,20 +272,20 @@ extern "C" {
#define PPA_YUV_TX_RANGE_M (PPA_YUV_TX_RANGE_V << PPA_YUV_TX_RANGE_S)
#define PPA_YUV_TX_RANGE_V 0x00000001U
#define PPA_YUV_TX_RANGE_S 9
/** PPA_YUV2RGB_PROTOCAL : R/W; bitpos: [10]; default: 0;
/** PPA_YUV2RGB_PROTOCOL : R/W; bitpos: [10]; default: 0;
* YUV to RGB protocol when reg_sr_rx_cm is 4'd8. 0: BT601. 1: BT709
*/
#define PPA_YUV2RGB_PROTOCAL (BIT(10))
#define PPA_YUV2RGB_PROTOCAL_M (PPA_YUV2RGB_PROTOCAL_V << PPA_YUV2RGB_PROTOCAL_S)
#define PPA_YUV2RGB_PROTOCAL_V 0x00000001U
#define PPA_YUV2RGB_PROTOCAL_S 10
/** PPA_RGB2YUV_PROTOCAL : R/W; bitpos: [11]; default: 0;
#define PPA_YUV2RGB_PROTOCOL (BIT(10))
#define PPA_YUV2RGB_PROTOCOL_M (PPA_YUV2RGB_PROTOCOL_V << PPA_YUV2RGB_PROTOCOL_S)
#define PPA_YUV2RGB_PROTOCOL_V 0x00000001U
#define PPA_YUV2RGB_PROTOCOL_S 10
/** PPA_RGB2YUV_PROTOCOL : R/W; bitpos: [11]; default: 0;
* RGB to YUV protocol when reg_sr_tx_cm is 4'd8. 0: BT601. 1: BT709
*/
#define PPA_RGB2YUV_PROTOCAL (BIT(11))
#define PPA_RGB2YUV_PROTOCAL_M (PPA_RGB2YUV_PROTOCAL_V << PPA_RGB2YUV_PROTOCAL_S)
#define PPA_RGB2YUV_PROTOCAL_V 0x00000001U
#define PPA_RGB2YUV_PROTOCAL_S 11
#define PPA_RGB2YUV_PROTOCOL (BIT(11))
#define PPA_RGB2YUV_PROTOCOL_M (PPA_RGB2YUV_PROTOCOL_V << PPA_RGB2YUV_PROTOCOL_S)
#define PPA_RGB2YUV_PROTOCOL_V 0x00000001U
#define PPA_RGB2YUV_PROTOCOL_S 11
/** PPA_YUV422_RX_BYTE_ORDER : R/W; bitpos: [13:12]; default: 0;
* YUV422 input byte order when reg_sr_rx_cm is 4'd9. 0: YVYU, 1:YUYV, 2: VYUY, 3: UYVY (high addr -> low addr)
*/
@@ -336,20 +336,20 @@ extern "C" {
#define PPA_BLEND_TX_YUV_RANGE_M (PPA_BLEND_TX_YUV_RANGE_V << PPA_BLEND_TX_YUV_RANGE_S)
#define PPA_BLEND_TX_YUV_RANGE_V 0x00000001U
#define PPA_BLEND_TX_YUV_RANGE_S 13
/** PPA_BLEND0_RX_YUV2RGB_PROTOCAL : R/W; bitpos: [14]; default: 0;
/** PPA_BLEND0_RX_YUV2RGB_PROTOCOL : R/W; bitpos: [14]; default: 0;
* YUV to RGB protocol when blend0 rx cm is yuv. 0: BT601. 1: BT709
*/
#define PPA_BLEND0_RX_YUV2RGB_PROTOCAL (BIT(14))
#define PPA_BLEND0_RX_YUV2RGB_PROTOCAL_M (PPA_BLEND0_RX_YUV2RGB_PROTOCAL_V << PPA_BLEND0_RX_YUV2RGB_PROTOCAL_S)
#define PPA_BLEND0_RX_YUV2RGB_PROTOCAL_V 0x00000001U
#define PPA_BLEND0_RX_YUV2RGB_PROTOCAL_S 14
/** PPA_BLEND_TX_RGB2YUV_PROTOCAL : R/W; bitpos: [15]; default: 0;
#define PPA_BLEND0_RX_YUV2RGB_PROTOCOL (BIT(14))
#define PPA_BLEND0_RX_YUV2RGB_PROTOCOL_M (PPA_BLEND0_RX_YUV2RGB_PROTOCOL_V << PPA_BLEND0_RX_YUV2RGB_PROTOCOL_S)
#define PPA_BLEND0_RX_YUV2RGB_PROTOCOL_V 0x00000001U
#define PPA_BLEND0_RX_YUV2RGB_PROTOCOL_S 14
/** PPA_BLEND_TX_RGB2YUV_PROTOCOL : R/W; bitpos: [15]; default: 0;
* RGB to YUV protocol when blend tx cm is yuv. 0: BT601. 1: BT709
*/
#define PPA_BLEND_TX_RGB2YUV_PROTOCAL (BIT(15))
#define PPA_BLEND_TX_RGB2YUV_PROTOCAL_M (PPA_BLEND_TX_RGB2YUV_PROTOCAL_V << PPA_BLEND_TX_RGB2YUV_PROTOCAL_S)
#define PPA_BLEND_TX_RGB2YUV_PROTOCAL_V 0x00000001U
#define PPA_BLEND_TX_RGB2YUV_PROTOCAL_S 15
#define PPA_BLEND_TX_RGB2YUV_PROTOCOL (BIT(15))
#define PPA_BLEND_TX_RGB2YUV_PROTOCOL_M (PPA_BLEND_TX_RGB2YUV_PROTOCOL_V << PPA_BLEND_TX_RGB2YUV_PROTOCOL_S)
#define PPA_BLEND_TX_RGB2YUV_PROTOCOL_V 0x00000001U
#define PPA_BLEND_TX_RGB2YUV_PROTOCOL_S 15
/** PPA_BLEND0_RX_YUV422_BYTE_ORDER : R/W; bitpos: [17:16]; default: 0;
* YUV422 input byte order when reg_sr_rx_cm is 4'd9. 0: YVYU, 1:YUYV, 2: VYUY, 3: UYVY (high addr -> low addr)
*/
components/soc/esp32s31/register/soc/ppa_struct.h
+11 -10
View File
@@ -1,5 +1,5 @@
/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0 OR MIT
*/
@@ -108,14 +108,14 @@ typedef union {
* YUV output range when reg_sr_tx_cm is 4'd8. 0: limit range. 1: full range
*/
uint32_t yuv_tx_range:1;
/** yuv2rgb_protocal : R/W; bitpos: [10]; default: 0;
/** yuv2rgb_protocol : R/W; bitpos: [10]; default: 0;
* YUV to RGB protocol when reg_sr_rx_cm is 4'd8. 0: BT601. 1: BT709
*/
uint32_t yuv2rgb_protocal:1;
/** rgb2yuv_protocal : R/W; bitpos: [11]; default: 0;
uint32_t yuv2rgb_protocol:1;
/** rgb2yuv_protocol : R/W; bitpos: [11]; default: 0;
* RGB to YUV protocol when reg_sr_tx_cm is 4'd8. 0: BT601. 1: BT709
*/
uint32_t rgb2yuv_protocal:1;
uint32_t rgb2yuv_protocol:1;
/** yuv422_rx_byte_order : R/W; bitpos: [13:12]; default: 0;
* YUV422 input byte order when reg_sr_rx_cm is 4'd9. 0: YVYU, 1:YUYV, 2: VYUY, 3: UYVY (high addr -> low addr)
*/
@@ -153,14 +153,14 @@ typedef union {
* YUV output range when blend tx cm is yuv. 0: limit range. 1: full range
*/
uint32_t blend_tx_yuv_range:1;
/** blend0_rx_yuv2rgb_protocal : R/W; bitpos: [14]; default: 0;
/** blend0_rx_yuv2rgb_protocol : R/W; bitpos: [14]; default: 0;
* YUV to RGB protocol when blend0 rx cm is yuv. 0: BT601. 1: BT709
*/
uint32_t blend0_rx_yuv2rgb_protocal:1;
/** blend_tx_rgb2yuv_protocal : R/W; bitpos: [15]; default: 0;
uint32_t blend0_rx_yuv2rgb_protocol:1;
/** blend_tx_rgb2yuv_protocol : R/W; bitpos: [15]; default: 0;
* RGB to YUV protocol when blend tx cm is yuv. 0: BT601. 1: BT709
*/
uint32_t blend_tx_rgb2yuv_protocal:1;
uint32_t blend_tx_rgb2yuv_protocol:1;
/** blend0_rx_yuv422_byte_order : R/W; bitpos: [17:16]; default: 0;
* YUV422 input byte order when reg_sr_rx_cm is 4'd9. 0: YVYU, 1:YUYV, 2: VYUY, 3: UYVY (high addr -> low addr)
*/
@@ -969,7 +969,7 @@ typedef union {
} ppa_date_reg_t;
typedef struct {
typedef struct ppa_dev_t {
volatile ppa_blend0_clut_data_reg_t blend0_clut_data;
volatile ppa_blend1_clut_data_reg_t blend1_clut_data;
uint32_t reserved_008;
@@ -1013,6 +1013,7 @@ typedef struct {
volatile ppa_date_reg_t date;
} ppa_dev_t;
extern ppa_dev_t PPA;
#ifndef __cplusplus
_Static_assert(sizeof(ppa_dev_t) == 0x104, "Invalid size of ppa_dev_t structure");