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https://github.com/espressif/esp-idf.git
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Merge branch 'fix/change_write_protection_bit_of_shared_security_efuses_v5.4' into 'release/v5.4'
Reorder write protection bits of some shared security efuses (v5.4) See merge request espressif/esp-idf!42328
This commit is contained in:
@@ -1136,8 +1136,9 @@ menu "Security features"
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config SECURE_FLASH_PSEUDO_ROUND_FUNC
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config SECURE_FLASH_PSEUDO_ROUND_FUNC
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bool "Permanently enable XTS-AES's pseudo rounds function"
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bool "Permanently enable XTS-AES's pseudo rounds function"
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default y
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default y if SECURE_FLASH_ENCRYPTION_MODE_RELEASE
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depends on SECURE_FLASH_ENCRYPTION_MODE_RELEASE && SOC_FLASH_ENCRYPTION_XTS_AES_SUPPORT_PSEUDO_ROUND
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default n
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depends on SECURE_FLASH_ENC_ENABLED && SOC_FLASH_ENCRYPTION_XTS_AES_SUPPORT_PSEUDO_ROUND
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help
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help
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If set (default), the bootloader will permanently enable the XTS-AES peripheral's pseudo rounds function.
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If set (default), the bootloader will permanently enable the XTS-AES peripheral's pseudo rounds function.
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Note: Enabling this config would burn an efuse.
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Note: Enabling this config would burn an efuse.
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@@ -215,6 +215,10 @@ bool esp_flash_encryption_cfg_verify_release_mode(void);
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* It burns:
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* It burns:
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* - "disable encrypt in dl mode"
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* - "disable encrypt in dl mode"
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* - set FLASH_CRYPT_CNT efuse to max
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* - set FLASH_CRYPT_CNT efuse to max
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*
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* In case of the targets that support the XTS-AES peripheral's pseudo rounds function,
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* this API would configure the pseudo rounds level efuse bit to level low if the efuse bit
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* is not set already.
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*/
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*/
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void esp_flash_encryption_set_release_mode(void);
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void esp_flash_encryption_set_release_mode(void);
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@@ -36,7 +36,7 @@ esp_err_t esp_flash_encryption_enable_secure_features(void)
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esp_efuse_write_field_bit(ESP_EFUSE_DIS_DIRECT_BOOT);
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esp_efuse_write_field_bit(ESP_EFUSE_DIS_DIRECT_BOOT);
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#if defined(CONFIG_SECURE_FLASH_ENCRYPTION_MODE_RELEASE) && defined(SOC_FLASH_ENCRYPTION_XTS_AES_SUPPORT_PSEUDO_ROUND)
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#if CONFIG_SECURE_FLASH_PSEUDO_ROUND_FUNC
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if (spi_flash_encrypt_ll_is_pseudo_rounds_function_supported()) {
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if (spi_flash_encrypt_ll_is_pseudo_rounds_function_supported()) {
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ESP_LOGI(TAG, "Enable XTS-AES pseudo rounds function...");
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ESP_LOGI(TAG, "Enable XTS-AES pseudo rounds function...");
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uint8_t xts_pseudo_level = CONFIG_SECURE_FLASH_PSEUDO_ROUND_FUNC_STRENGTH;
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uint8_t xts_pseudo_level = CONFIG_SECURE_FLASH_PSEUDO_ROUND_FUNC_STRENGTH;
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@@ -212,8 +212,13 @@ void esp_flash_encryption_set_release_mode(void)
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#ifdef SOC_FLASH_ENCRYPTION_XTS_AES_SUPPORT_PSEUDO_ROUND
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#ifdef SOC_FLASH_ENCRYPTION_XTS_AES_SUPPORT_PSEUDO_ROUND
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if (spi_flash_encrypt_ll_is_pseudo_rounds_function_supported()) {
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if (spi_flash_encrypt_ll_is_pseudo_rounds_function_supported()) {
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uint8_t xts_pseudo_level = ESP_XTS_AES_PSEUDO_ROUNDS_LOW;
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uint8_t xts_pseudo_level = 0;
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esp_efuse_write_field_blob(ESP_EFUSE_XTS_DPA_PSEUDO_LEVEL, &xts_pseudo_level, ESP_EFUSE_XTS_DPA_PSEUDO_LEVEL[0]->bit_count);
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esp_efuse_read_field_blob(ESP_EFUSE_XTS_DPA_PSEUDO_LEVEL, &xts_pseudo_level, ESP_EFUSE_XTS_DPA_PSEUDO_LEVEL[0]->bit_count);
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if (xts_pseudo_level == ESP_XTS_AES_PSEUDO_ROUNDS_DISABLE) {
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xts_pseudo_level = ESP_XTS_AES_PSEUDO_ROUNDS_LOW;
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esp_efuse_write_field_blob(ESP_EFUSE_XTS_DPA_PSEUDO_LEVEL, &xts_pseudo_level, ESP_EFUSE_XTS_DPA_PSEUDO_LEVEL[0]->bit_count);
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}
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}
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}
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#endif
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#endif
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@@ -13,6 +13,9 @@
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#include "esp_security_priv.h"
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#include "esp_security_priv.h"
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#include "esp_err.h"
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#include "esp_err.h"
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#include "hal/efuse_hal.h"
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#include "hal/efuse_hal.h"
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#if SOC_ECDSA_P192_CURVE_DEFAULT_DISABLED
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#include "hal/ecdsa_ll.h"
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#endif
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#if SOC_KEY_MANAGER_ECDSA_KEY_DEPLOY || SOC_KEY_MANAGER_FE_KEY_DEPLOY
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#if SOC_KEY_MANAGER_ECDSA_KEY_DEPLOY || SOC_KEY_MANAGER_FE_KEY_DEPLOY
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#include "hal/key_mgr_ll.h"
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#include "hal/key_mgr_ll.h"
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@@ -42,6 +45,8 @@ ESP_SYSTEM_INIT_FN(esp_security_init, SECONDARY, BIT(0), 103)
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esp_crypto_dpa_protection_startup();
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esp_crypto_dpa_protection_startup();
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#endif
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#endif
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esp_err_t err = ESP_FAIL;
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#if CONFIG_ESP_CRYPTO_FORCE_ECC_CONSTANT_TIME_POINT_MUL
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#if CONFIG_ESP_CRYPTO_FORCE_ECC_CONSTANT_TIME_POINT_MUL
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bool force_constant_time = true;
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bool force_constant_time = true;
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#if CONFIG_IDF_TARGET_ESP32H2
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#if CONFIG_IDF_TARGET_ESP32H2
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@@ -51,7 +56,7 @@ ESP_SYSTEM_INIT_FN(esp_security_init, SECONDARY, BIT(0), 103)
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#endif
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#endif
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if (!esp_efuse_read_field_bit(ESP_EFUSE_ECC_FORCE_CONST_TIME) && force_constant_time) {
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if (!esp_efuse_read_field_bit(ESP_EFUSE_ECC_FORCE_CONST_TIME) && force_constant_time) {
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ESP_EARLY_LOGD(TAG, "Forcefully enabling ECC constant time operations");
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ESP_EARLY_LOGD(TAG, "Forcefully enabling ECC constant time operations");
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esp_err_t err = esp_efuse_write_field_bit(ESP_EFUSE_ECC_FORCE_CONST_TIME);
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err = esp_efuse_write_field_bit(ESP_EFUSE_ECC_FORCE_CONST_TIME);
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if (err != ESP_OK) {
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if (err != ESP_OK) {
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ESP_EARLY_LOGE(TAG, "Enabling ECC constant time operations forcefully failed.");
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ESP_EARLY_LOGE(TAG, "Enabling ECC constant time operations forcefully failed.");
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return err;
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return err;
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@@ -60,14 +65,25 @@ ESP_SYSTEM_INIT_FN(esp_security_init, SECONDARY, BIT(0), 103)
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#endif
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#endif
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#if CONFIG_ESP_ECDSA_ENABLE_P192_CURVE
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#if CONFIG_ESP_ECDSA_ENABLE_P192_CURVE
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esp_err_t err;
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err = esp_efuse_enable_ecdsa_p192_curve_mode();
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err = esp_efuse_enable_ecdsa_p192_curve_mode();
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if (err != ESP_OK) {
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if (err != ESP_OK) {
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return err;
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return err;
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}
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}
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#endif
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#endif
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return ESP_OK;
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#if CONFIG_SECURE_BOOT_V2_ENABLED && SOC_ECDSA_P192_CURVE_DEFAULT_DISABLED
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// Also write protect the ECDSA_CURVE_MODE efuse bit.
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if (ecdsa_ll_is_configurable_curve_supported()) {
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err = esp_efuse_write_field_bit(ESP_EFUSE_WR_DIS_ECDSA_CURVE_MODE);
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if (err != ESP_OK) {
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ESP_LOGE(TAG, "Failed to write protect the ECDSA_CURVE_MODE efuse bit.");
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return err;
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}
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}
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#endif
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err = ESP_OK;
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return err;
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}
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}
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void esp_security_init_include_impl(void)
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void esp_security_init_include_impl(void)
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@@ -485,6 +485,7 @@ In this workflow we shall use ``espsecure`` tool to generate signing keys and us
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:SOC_EFUSE_DIS_USB_JTAG: - ``DIS_USB_JTAG``: Disable USB switch to JTAG.
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:SOC_EFUSE_DIS_USB_JTAG: - ``DIS_USB_JTAG``: Disable USB switch to JTAG.
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:SOC_EFUSE_DIS_PAD_JTAG: - ``DIS_PAD_JTAG``: Disable JTAG permanently.
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:SOC_EFUSE_DIS_PAD_JTAG: - ``DIS_PAD_JTAG``: Disable JTAG permanently.
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:SOC_EFUSE_REVOKE_BOOT_KEY_DIGESTS: - ``SECURE_BOOT_AGGRESSIVE_REVOKE``: Aggressive revocation of key digests, see :ref:`secure-boot-v2-aggressive-key-revocation` for more details.
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:SOC_EFUSE_REVOKE_BOOT_KEY_DIGESTS: - ``SECURE_BOOT_AGGRESSIVE_REVOKE``: Aggressive revocation of key digests, see :ref:`secure-boot-v2-aggressive-key-revocation` for more details.
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:SOC_ECDSA_P192_CURVE_DEFAULT_DISABLED: - ``WR_DIS_ECDSA_CURVE_MODE``: Disable writing to the ECDSA curve mode eFuse bit. As this write protection bit is shared with ``ECC_FORCE_CONST_TIME``, it is recommended to write protect this bit only after configuring the ``ECC_FORCE_CONST_TIME`` eFuse.
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The respective eFuses can be burned by running:
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The respective eFuses can be burned by running:
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@@ -485,6 +485,7 @@ flash 加密指南
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:SOC_EFUSE_DIS_USB_JTAG: - ``DIS_USB_JTAG``:禁止从 USB 切换到 JTAG
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:SOC_EFUSE_DIS_USB_JTAG: - ``DIS_USB_JTAG``:禁止从 USB 切换到 JTAG
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:SOC_EFUSE_DIS_PAD_JTAG: - ``DIS_PAD_JTAG``:永久禁用 JTAG。
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:SOC_EFUSE_DIS_PAD_JTAG: - ``DIS_PAD_JTAG``:永久禁用 JTAG。
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:SOC_EFUSE_REVOKE_BOOT_KEY_DIGESTS: - ``SECURE_BOOT_AGGRESSIVE_REVOKE``:主动吊销密钥摘要。详请请参阅 :ref:`secure-boot-v2-aggressive-key-revocation`。
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:SOC_EFUSE_REVOKE_BOOT_KEY_DIGESTS: - ``SECURE_BOOT_AGGRESSIVE_REVOKE``:主动吊销密钥摘要。详请请参阅 :ref:`secure-boot-v2-aggressive-key-revocation`。
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:SOC_ECDSA_P192_CURVE_DEFAULT_DISABLED: - ``WR_DIS_ECDSA_CURVE_MODE``:禁止写入 ECDSA 曲线模式的 eFuse 位。由于此写保护位与 ``ECC_FORCE_CONST_TIME`` 共享,建议先配置好 ``ECC_FORCE_CONST_TIME`` eFuse 字段后,再设置此写保护位)。
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运行以下命令烧录相应的 eFuse:
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运行以下命令烧录相应的 eFuse:
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