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Merge branch 'feat/csi_error_event_v6.0' into 'release/v6.0'

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Add MIPI-CSI error event (v6.0)

See merge request espressif/esp-idf!50681
This commit is contained in:
morris
2026-07-17 12:17:02 +08:00
parent 7c49a6a4d8 bdf42b6a99
commit afb9f5a719
8 changed files with 352 additions and 15 deletions
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components/esp_hal_cam/esp32p4/include/hal/mipi_csi_host_ll.h
+117 -1
View File
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -20,6 +20,32 @@ extern "C" {
#define MIPI_CSI_HOST_LL_LANE_NUM_MAX 2
/**
* @brief MIPI CSI host interrupt categories, bit layout aligned with the `int_st_main` register
*/
typedef enum {
MIPI_CSI_HOST_LL_INTR_PHY_FATAL = (1 << 0), /*!< PHY fatal error, e.g. data lane Start-of-Transmission sync error (ErrSotSyncHS) */
MIPI_CSI_HOST_LL_INTR_PKT_FATAL = (1 << 1), /*!< Packet fatal error, e.g. header double-bit ECC error or shorter payload */
MIPI_CSI_HOST_LL_INTR_BNDRY_FRAME_FATAL = (1 << 2), /*!< Frame boundary error, e.g. unpaired Frame Start / Frame End */
MIPI_CSI_HOST_LL_INTR_SEQ_FRAME_FATAL = (1 << 3), /*!< Frame sequence error */
MIPI_CSI_HOST_LL_INTR_CRC_FRAME_FATAL = (1 << 4), /*!< A frame containing at least one CRC error */
MIPI_CSI_HOST_LL_INTR_PLD_CRC_FATAL = (1 << 5), /*!< Payload CRC error */
MIPI_CSI_HOST_LL_INTR_DATA_ID = (1 << 6), /*!< Unrecognized or unsupported data type detected */
MIPI_CSI_HOST_LL_INTR_ECC_CORRECTED = (1 << 7), /*!< Header single-bit ECC error (corrected by hardware) */
MIPI_CSI_HOST_LL_INTR_PHY = (1 << 16), /*!< PHY error, e.g. Start-of-Transmission error (ErrSotHS) or escape entry error (ErrEsc) */
} mipi_csi_host_ll_intr_t;
/// Mask covering all MIPI CSI host error interrupts
#define MIPI_CSI_HOST_LL_INTR_ERR_ALL (MIPI_CSI_HOST_LL_INTR_PHY_FATAL | \
MIPI_CSI_HOST_LL_INTR_PKT_FATAL | \
MIPI_CSI_HOST_LL_INTR_BNDRY_FRAME_FATAL | \
MIPI_CSI_HOST_LL_INTR_SEQ_FRAME_FATAL | \
MIPI_CSI_HOST_LL_INTR_CRC_FRAME_FATAL | \
MIPI_CSI_HOST_LL_INTR_PLD_CRC_FATAL | \
MIPI_CSI_HOST_LL_INTR_DATA_ID | \
MIPI_CSI_HOST_LL_INTR_ECC_CORRECTED | \
MIPI_CSI_HOST_LL_INTR_PHY)
/**
* @brief Enable CSI host reset output
*
@@ -64,6 +90,96 @@ static inline void mipi_csi_host_ll_enable_scrambling(csi_host_dev_t *dev, bool
dev->scrambling.scramble_enable = en;
}
/**
* @brief Enable or disable the MIPI CSI host error interrupts
*
* @param dev Pointer to the CSI Host controller register base address
* @param mask Interrupt categories to operate on, see `mipi_csi_host_ll_intr_t`
* @param en True to enable (unmask), false to disable (mask)
*/
static inline void mipi_csi_host_ll_enable_intr(csi_host_dev_t *dev, uint32_t mask, bool en)
{
if (mask & MIPI_CSI_HOST_LL_INTR_PHY_FATAL) {
dev->int_msk_phy_fatal.val = en ? 0x3 : 0x0;
}
if (mask & MIPI_CSI_HOST_LL_INTR_PKT_FATAL) {
dev->int_msk_pkt_fatal.val = en ? 0x3 : 0x0;
}
if (mask & MIPI_CSI_HOST_LL_INTR_BNDRY_FRAME_FATAL) {
dev->int_msk_bndry_frame_fatal.val = en ? 0xffff : 0x0;
}
if (mask & MIPI_CSI_HOST_LL_INTR_SEQ_FRAME_FATAL) {
dev->int_msk_seq_frame_fatal.val = en ? 0xffff : 0x0;
}
if (mask & MIPI_CSI_HOST_LL_INTR_CRC_FRAME_FATAL) {
dev->int_msk_crc_frame_fatal.val = en ? 0xffff : 0x0;
}
if (mask & MIPI_CSI_HOST_LL_INTR_PLD_CRC_FATAL) {
dev->int_msk_pld_crc_fatal.val = en ? 0xffff : 0x0;
}
if (mask & MIPI_CSI_HOST_LL_INTR_DATA_ID) {
dev->int_msk_data_id.val = en ? 0xffff : 0x0;
}
if (mask & MIPI_CSI_HOST_LL_INTR_ECC_CORRECTED) {
dev->int_msk_ecc_corrected.val = en ? 0xffff : 0x0;
}
if (mask & MIPI_CSI_HOST_LL_INTR_PHY) {
dev->int_msk_phy.val = en ? 0x30003 : 0x0;
}
}
/**
* @brief Get the MIPI CSI host top-level interrupt status
*
* @param dev Pointer to the CSI Host controller register base address
*
* @return The top-level interrupt status, a combination of `mipi_csi_host_ll_intr_t`
*/
static inline uint32_t mipi_csi_host_ll_get_intr_status(csi_host_dev_t *dev)
{
return dev->int_st_main.val;
}
/**
* @brief Clear the MIPI CSI host interrupt status
*
* @note The per-category status registers are clear-on-read, reading them also clears the
* corresponding bit in the `int_st_main` register.
*
* @param dev Pointer to the CSI Host controller register base address
* @param mask Interrupt categories to clear, see `mipi_csi_host_ll_intr_t`
*/
static inline void mipi_csi_host_ll_clear_intr_status(csi_host_dev_t *dev, uint32_t mask)
{
if (mask & MIPI_CSI_HOST_LL_INTR_PHY_FATAL) {
(void)dev->int_st_phy_fatal.val;
}
if (mask & MIPI_CSI_HOST_LL_INTR_PKT_FATAL) {
(void)dev->int_st_pkt_fatal.val;
}
if (mask & MIPI_CSI_HOST_LL_INTR_BNDRY_FRAME_FATAL) {
(void)dev->int_st_bndry_frame_fatal.val;
}
if (mask & MIPI_CSI_HOST_LL_INTR_SEQ_FRAME_FATAL) {
(void)dev->int_st_seq_frame_fatal.val;
}
if (mask & MIPI_CSI_HOST_LL_INTR_CRC_FRAME_FATAL) {
(void)dev->int_st_crc_frame_fatal.val;
}
if (mask & MIPI_CSI_HOST_LL_INTR_PLD_CRC_FATAL) {
(void)dev->int_st_pld_crc_fatal.val;
}
if (mask & MIPI_CSI_HOST_LL_INTR_DATA_ID) {
(void)dev->int_st_data_id.val;
}
if (mask & MIPI_CSI_HOST_LL_INTR_ECC_CORRECTED) {
(void)dev->int_st_ecc_corrected.val;
}
if (mask & MIPI_CSI_HOST_LL_INTR_PHY) {
(void)dev->int_st_phy.val;
}
}
#ifdef __cplusplus
}
#endif
components/esp_hal_cam/esp32p4/mipi_csi_periph.c
+8 -1
View File
@@ -1,10 +1,11 @@
/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2024-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "hal/mipi_csi_periph.h"
#include "soc/interrupts.h"
const soc_mipi_csi_phy_pll_freq_range_t soc_mipi_csi_phy_pll_ranges[] = {
{90, 99, 0x00}, // [90,100) Mbps
@@ -48,3 +49,9 @@ const soc_mipi_csi_phy_pll_freq_range_t soc_mipi_csi_phy_pll_ranges[] = {
};
const size_t num_of_soc_mipi_csi_phy_pll_ranges = sizeof(soc_mipi_csi_phy_pll_ranges) / sizeof(soc_mipi_csi_phy_pll_freq_range_t);
const soc_mipi_csi_signal_desc_t soc_mipi_csi_signals[MIPI_CSI_LL_HOST_CTLR_NUMS] = {
[0] = {
.host_irq_id = ETS_CSI_INTR_SOURCE,
}
};
components/esp_hal_cam/include/hal/mipi_csi_periph.h
+15 -1
View File
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2024-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -8,11 +8,17 @@
#include <stdint.h>
#include <stddef.h>
#include "soc/soc_caps.h"
#if SOC_HAS(MIPI_CSI)
#include "hal/mipi_csi_ll.h"
#endif
#ifdef __cplusplus
extern "C" {
#endif
#if SOC_HAS(MIPI_CSI)
/**
* @brief MIPI CSI PHY PLL frequency range
*/
@@ -25,6 +31,14 @@ typedef struct {
extern const soc_mipi_csi_phy_pll_freq_range_t soc_mipi_csi_phy_pll_ranges[];
extern const size_t num_of_soc_mipi_csi_phy_pll_ranges;
typedef struct {
const int host_irq_id; // interrupt source ID for MIPI CSI Host
} soc_mipi_csi_signal_desc_t;
extern const soc_mipi_csi_signal_desc_t soc_mipi_csi_signals[MIPI_CSI_LL_HOST_CTLR_NUMS];
#endif // SOC_HAS(MIPI_CSI)
#ifdef __cplusplus
}
#endif