feat(spi_flash): implement dynamic CPU frequency switching workaround for encrypted writes

This commit implements a workaround that allows ESP32-C5 to run at 240MHz CPU frequency
normally, while automatically reducing CPU frequency during encrypted flash writes to
ensure correct operation. The frequency limit is chip revision dependent:
- v1.2 and above: limited to 160MHz during encrypted writes
- v1.0 and below: limited to 80MHz during encrypted writes

Key implementation details:
- Frequency limiting is triggered automatically when esp_flash_write_encrypted() is called
- Uses start() flags (ESP_FLASH_START_FLAG_LIMIT_CPU_FREQ) to integrate with OS layer
- Works with both PM enabled and disabled configurations
- Frequency is automatically restored after encrypted write completes
- For ESP32-C5 with 120MHz flash, Flash clock and timing registers are adjusted when
  CPU frequency is reduced to 80MHz
- SPI1 timing registers are configured during frequency switching since encrypted writes
  use SPI1 and must work correctly at reduced CPU frequencies

Code improvements:
- Use SOC_MSPI_FREQ_AXI_CONSTRAINED capability macro instead of hardcoded chip checks
- Control workaround via Kconfig (CONFIG_PM_WORKAROUND_FREQ_LIMIT_ENABLED) instead of
  hardcoded macros
- Add comprehensive test cases covering various PM configurations and edge cases

This workaround enables ESP32-C5 applications to benefit from 240MHz CPU performance
while maintaining reliable encrypted flash write functionality.

components/esp_system/port/soc/esp32c5/Kconfig.cpu

@@ -20,6 +20,13 @@ choice ESP_DEFAULT_CPU_FREQ_MHZ
         # Please see SoC Errata document for details.
         depends on !SECURE_FLASH_ENC_ENABLED
         bool "240 MHz"
+        help
+            When 240MHz is selected, esp_flash_write_encrypted() will automatically limit CPU frequency during
+            execution:
+            - v1.2 and above chips: limited to 160MHz
+            - v1.0 and below chips: limited to 80MHz
+            When 160MHz or lower is selected, no frequency limiting occurs during encrypted writes. Please refer to
+            the ESP32-C5 SoC Errata document for more details.
 endchoice
 
 config ESP_DEFAULT_CPU_FREQ_MHZ