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feat(hal/spi_flash_encrypted): Enable pseudo rounds function during XTS-AES operations

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This commit is contained in:
harshal.patil
2025-01-23 14:06:16 +05:30
parent 8d30077744
commit ae4e693cfc
8 changed files with 153 additions and 16 deletions
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components/soc/esp32h2/include/soc/Kconfig.soc_caps.in
+4
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@@ -1231,6 +1231,10 @@ config SOC_FLASH_ENCRYPTION_XTS_AES_128
bool
default y
config SOC_FLASH_ENCRYPTION_XTS_AES_SUPPORT_PSEUDO_ROUND
bool
default y
config SOC_CRYPTO_DPA_PROTECTION_SUPPORTED
bool
default y
components/soc/esp32h2/include/soc/soc_caps.h
+1
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@@ -497,6 +497,7 @@
#define SOC_FLASH_ENCRYPTED_XTS_AES_BLOCK_MAX (64)
#define SOC_FLASH_ENCRYPTION_XTS_AES 1
#define SOC_FLASH_ENCRYPTION_XTS_AES_128 1
#define SOC_FLASH_ENCRYPTION_XTS_AES_SUPPORT_PSEUDO_ROUND 1 /*!< Only avliable in chip version above 1.2*/
/*------------------------ Anti DPA (Security) CAPS --------------------------*/
#define SOC_CRYPTO_DPA_PROTECTION_SUPPORTED 1
components/soc/esp32h2/include/soc/spi_mem_struct.h
+15 -6
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -70,7 +70,7 @@ typedef volatile struct spi_mem_dev_s {
} ctrl;
union {
struct {
uint32_t clk_mode : 2; /*SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on.*/
uint32_t clk_mode : 2; /*SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is always on.*/
uint32_t cs_hold_dly_res : 10; /*After RES/DP/HPM command is sent, SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 512) SPI_CLK cycles.*/
uint32_t reserved2 : 9; /*reserved*/
uint32_t reg_ar_size0_1_support_en : 1; /*1: MSPI supports ARSIZE 0~3. When ARSIZE =0~2, MSPI read address is 4*n and reply the real AXI read data back. 0: When ARSIZE 0~1, MSPI reply SLV_ERR.*/
@@ -272,7 +272,7 @@ typedef volatile struct spi_mem_dev_s {
uint32_t sclkcnt_h : 8; /*For SPI0 external RAM interface, it must be floor((spi_mem_clkcnt_N+1)/2-1).*/
uint32_t sclkcnt_n : 8; /*For SPI0 external RAM interface, it is the divider of spi_mem_clk. So spi_mem_clk frequency is system/(spi_mem_clkcnt_N+1)*/
uint32_t reserved24 : 7; /*reserved*/
uint32_t sclk_equ_sysclk : 1; /*For SPI0 external RAM interface, 1: spi_mem_clk is eqaul to system 0: spi_mem_clk is divided from system clock.*/
uint32_t sclk_equ_sysclk : 1; /*For SPI0 external RAM interface, 1: spi_mem_clk is equal to system 0: spi_mem_clk is divided from system clock.*/
};
uint32_t val;
} sram_clk;
@@ -389,7 +389,7 @@ typedef volatile struct spi_mem_dev_s {
uint32_t axi_raddr_err : 1; /*The raw bit for SPI_MEM_AXI_RADDR_ERR_INT interrupt. 1: Triggered when AXI read address is invalid by compared to MMU configuration. 0: Others.*/
uint32_t axi_wr_flash_err : 1; /*The raw bit for SPI_MEM_AXI_WR_FALSH_ERR_INT interrupt. 1: Triggered when AXI write flash request is received. 0: Others.*/
uint32_t axi_waddr_err : 1; /*The raw bit for SPI_MEM_AXI_WADDR_ERR_INT interrupt. 1: Triggered when AXI write address is invalid by compared to MMU configuration. 0: Others.*/
uint32_t brown_out : 1; /*The raw bit for SPI_MEM_BROWN_OUT_INT interrupt. 1: Triggered condition is that chip is loosing power and RTC module sends out brown out close flash request to SPI1. After SPI1 sends out suspend command to flash, this interrupt is triggered and MSPI returns to idle state. 0: Others.*/
uint32_t brown_out : 1; /*The raw bit for SPI_MEM_BROWN_OUT_INT interrupt. 1: Triggered condition is that chip is losing power and RTC module sends out brown out close flash request to SPI1. After SPI1 sends out suspend command to flash, this interrupt is triggered and MSPI returns to idle state. 0: Others.*/
uint32_t reserved11 : 21; /*reserved*/
};
uint32_t val;
@@ -1026,14 +1026,23 @@ typedef volatile struct spi_mem_dev_s {
} mmu_power_ctrl;
union {
struct {
uint32_t reg_crypt_security_level : 3; /*Set the security level of spi mem cryption. 0: Shut off cryption DPA funtion. 1-7: The bigger the number is, the more secure the cryption is. (Note that the performance of cryption will decrease together with this number increasing)*/
uint32_t reg_crypt_security_level : 3; /*Set the security level of spi mem cryption. 0: Shut off cryption DPA function. 1-7: The bigger the number is, the more secure the cryption is. (Note that the performance of cryption will decrease together with this number increasing)*/
uint32_t reg_crypt_calc_d_dpa_en : 1; /*Only available when SPI_CRYPT_SECURITY_LEVEL is not 0. 1: Enable DPA in the calculation that using key 1 or key 2. 0: Enable DPA only in the calculation that using key 1.*/
uint32_t reg_crypt_dpa_selectister : 1; /*1: MSPI XTS DPA clock gate is controlled by SPI_CRYPT_CALC_D_DPA_EN and SPI_CRYPT_SECURITY_LEVEL. 0: Controlled by efuse bits.*/
uint32_t reserved5 : 27; /*reserved*/
};
uint32_t val;
} dpa_ctrl;
uint32_t reserved_38c;
union {
struct {
uint32_t reg_mode_pseudo : 2; /*Set the mode of pseudo. 2'b00: crypto without pseudo. 2'b01: state T with pseudo and state D without pseudo. 2'b10: state T with pseudo and state D with few pseudo. 2'b11: crypto with pseudo.*/
uint32_t reg_pseudo_rng_cnt : 3; /*xts aes peseudo function base round that must be performed.*/
uint32_t reg_pseudo_base : 4; /*xts aes peseudo function base round that must be performed.*/
uint32_t reg_pseudo_inc : 2; /*xts aes peseudo function increment round that will be performed randomly between 0 & 2**(inc+1).*/
uint32_t reserved11 : 21; /*reserved*/
};
uint32_t val;
} xts_pseudo_round_conf;
uint32_t reserved_390;
uint32_t reserved_394;
uint32_t reserved_398;
components/soc/esp32h2/include/soc/xts_aes_reg.h
+40 -4
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@@ -1,5 +1,5 @@
/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -32,7 +32,7 @@ s. Please do not use this field..*/
#define XTS_AES_DESTINATION_REG(i) (REG_SPI_MEM_BASE(i) + 0x344)
/* XTS_AES_DESTINATION : R/W ;bitpos:[0] ;default: 1'b0 ; */
/*description: This bit stores the destination parameter which will be used in manual encryptio
/*description: This bit stores the destination parameter which will be used in manual encryption
n calculation. 0: flash(default), 1: psram(reserved). Only default value can be
used..*/
#define XTS_AES_DESTINATION (BIT(0))
@@ -54,7 +54,7 @@ size parameter..*/
/* XTS_AES_TRIGGER : WT ;bitpos:[0] ;default: 1'b0 ; */
/*description: Set this bit to trigger the process of manual encryption calculation. This actio
n should only be asserted when manual encryption status is 0. After this action,
manual encryption status becomes 1. After calculation is done, manual encryptio
manual encryption status becomes 1. After calculation is done, manual encryption
n status becomes 2..*/
#define XTS_AES_TRIGGER (BIT(0))
#define XTS_AES_TRIGGER_M (BIT(0))
@@ -116,7 +116,7 @@ ing key 1..*/
#define XTS_AES_CRYPT_CALC_D_DPA_EN_V 0x1
#define XTS_AES_CRYPT_CALC_D_DPA_EN_S 3
/* XTS_AES_CRYPT_SECURITY_LEVEL : R/W ;bitpos:[2:0] ;default: 3'd7 ; */
/*description: Set the security level of spi mem cryption. 0: Shut off cryption DPA funtion. 1-
/*description: Set the security level of spi mem cryption. 0: Shut off cryption DPA function. 1-
7: The bigger the number is, the more secure the cryption is. (Note that the per
formance of cryption will decrease together with this number increasing).*/
#define XTS_AES_CRYPT_SECURITY_LEVEL 0x00000007
@@ -124,6 +124,42 @@ formance of cryption will decrease together with this number increasing).*/
#define XTS_AES_CRYPT_SECURITY_LEVEL_V 0x7
#define XTS_AES_CRYPT_SECURITY_LEVEL_S 0
/** XTS_AES_PSEUDO_ROUND_CONF_REG register
* SPI memory encryption PSEUDO register
*/
#define XTS_AES_PSEUDO_ROUND_CONF_REG(i) (REG_SPI_MEM_BASE(i) + 0x38c)
/** XTS_AES_MODE_PSEUDO : R/W; bitpos: [1:0]; default: 0;
* Set the mode of pseudo. 2'b00: crypto without pseudo. 2'b01: state T with pseudo
* and state D without pseudo. 2'b10: state T with pseudo and state D with few pseudo.
* 2'b11: crypto with pseudo.
*/
#define XTS_AES_MODE_PSEUDO 0x00000003U
#define XTS_AES_MODE_PSEUDO_M (XTS_AES_MODE_PSEUDO_V << XTS_AES_MODE_PSEUDO_S)
#define XTS_AES_MODE_PSEUDO_V 0x00000003U
#define XTS_AES_MODE_PSEUDO_S 0
/** XTS_AES_PSEUDO_RNG_CNT : R/W; bitpos: [4:2]; default: 7;
* xts aes peseudo function base round that must be performed.
*/
#define XTS_AES_PSEUDO_RNG_CNT 0x00000007U
#define XTS_AES_PSEUDO_RNG_CNT_M (XTS_AES_PSEUDO_RNG_CNT_V << XTS_AES_PSEUDO_RNG_CNT_S)
#define XTS_AES_PSEUDO_RNG_CNT_V 0x00000007U
#define XTS_AES_PSEUDO_RNG_CNT_S 2
/** XTS_AES_PSEUDO_BASE : R/W; bitpos: [8:5]; default: 2;
* xts aes peseudo function base round that must be performed.
*/
#define XTS_AES_PSEUDO_BASE 0x0000000FU
#define XTS_AES_PSEUDO_BASE_M (XTS_AES_PSEUDO_BASE_V << XTS_AES_PSEUDO_BASE_S)
#define XTS_AES_PSEUDO_BASE_V 0x0000000FU
#define XTS_AES_PSEUDO_BASE_S 5
/** XTS_AES_PSEUDO_INC : R/W; bitpos: [10:9]; default: 2;
* xts aes peseudo function increment round that will be performed randomly between 0 &
* 2**(inc+1).
*/
#define XTS_AES_PSEUDO_INC 0x00000003U
#define XTS_AES_PSEUDO_INC_M (XTS_AES_PSEUDO_INC_V << XTS_AES_PSEUDO_INC_S)
#define XTS_AES_PSEUDO_INC_V 0x00000003U
#define XTS_AES_PSEUDO_INC_S 9
#ifdef __cplusplus
}
#endif