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feat: enable Secure Boot, Flash Encryption and Key Manager support for S31

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This commit is contained in:
nilesh.kale
2026-06-02 13:09:44 +05:30
parent 9cede1d920
commit ae1ec76e82
10 changed files with 838 additions and 291 deletions
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components/esp_hal_mspi/esp32s31/include/hal/spi_flash_encrypted_ll.h
+57 -14
View File
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -15,11 +15,12 @@
#include <stdbool.h>
#include <string.h>
#include "soc/system_reg.h"
#include "soc/hwcrypto_reg.h"
#include "soc/hp_system_reg.h"
#include "soc/spi_mem_c_reg.h"
#include "soc/soc.h"
#include "soc/soc_caps.h"
#include "hal/assert.h"
#include "hal/spi_flash_encrypt_types.h"
#ifdef __cplusplus
extern "C" {
@@ -36,7 +37,9 @@ typedef enum {
*/
static inline void spi_flash_encrypt_ll_enable(void)
{
// TODO: ["ESP32S31"] IDF-14628
REG_SET_BIT(HP_SYSTEM_CRYPTO_CTRL_REG,
HP_SYSTEM_REG_ENABLE_DOWNLOAD_MANUAL_ENCRYPT |
HP_SYSTEM_REG_ENABLE_SPI_MANUAL_ENCRYPT);
}
/*
@@ -44,7 +47,8 @@ static inline void spi_flash_encrypt_ll_enable(void)
*/
static inline void spi_flash_encrypt_ll_disable(void)
{
// TODO: ["ESP32S31"] IDF-14628
REG_CLR_BIT(HP_SYSTEM_CRYPTO_CTRL_REG,
HP_SYSTEM_REG_ENABLE_SPI_MANUAL_ENCRYPT);
}
/**
@@ -56,7 +60,9 @@ static inline void spi_flash_encrypt_ll_disable(void)
*/
static inline void spi_flash_encrypt_ll_type(flash_encrypt_ll_type_t type)
{
// TODO: ["ESP32S31"] IDF-14628
// Our hardware only support flash encryption
HAL_ASSERT(type == FLASH_ENCRYPTION_MANU);
REG_SET_FIELD(SPI_MEM_C_XTS_DESTINATION_REG, SPI_XTS_DESTINATION, type);
}
/**
@@ -66,7 +72,8 @@ static inline void spi_flash_encrypt_ll_type(flash_encrypt_ll_type_t type)
*/
static inline void spi_flash_encrypt_ll_buffer_length(uint32_t size)
{
// TODO: ["ESP32S31"] IDF-14628
// Desired block should not be larger than the block size.
REG_SET_FIELD(SPI_MEM_C_XTS_LINESIZE_REG, SPI_XTS_LINESIZE, size >> 5);
}
/**
@@ -79,7 +86,9 @@ static inline void spi_flash_encrypt_ll_buffer_length(uint32_t size)
*/
static inline void spi_flash_encrypt_ll_plaintext_save(uint32_t address, const uint32_t* buffer, uint32_t size)
{
// TODO: ["ESP32S31"] IDF-14628
uint32_t plaintext_offs = (address % SOC_FLASH_ENCRYPTED_XTS_AES_BLOCK_MAX);
HAL_ASSERT(plaintext_offs + size <= SOC_FLASH_ENCRYPTED_XTS_AES_BLOCK_MAX);
memcpy((void *)(SPI_MEM_C_XTS_PLAIN_BASE_REG + plaintext_offs), buffer, size);
}
/**
@@ -89,7 +98,7 @@ static inline void spi_flash_encrypt_ll_plaintext_save(uint32_t address, const u
*/
static inline void spi_flash_encrypt_ll_address_save(uint32_t flash_addr)
{
// TODO: ["ESP32S31"] IDF-14628
REG_SET_FIELD(SPI_MEM_C_XTS_PHYSICAL_ADDRESS_REG, SPI_XTS_PHYSICAL_ADDRESS, flash_addr);
}
/**
@@ -97,7 +106,7 @@ static inline void spi_flash_encrypt_ll_address_save(uint32_t flash_addr)
*/
static inline void spi_flash_encrypt_ll_calculate_start(void)
{
// TODO: ["ESP32S31"] IDF-14628
REG_SET_FIELD(SPI_MEM_C_XTS_TRIGGER_REG, SPI_XTS_TRIGGER, 1);
}
/**
@@ -105,7 +114,8 @@ static inline void spi_flash_encrypt_ll_calculate_start(void)
*/
static inline void spi_flash_encrypt_ll_calculate_wait_idle(void)
{
// TODO: ["ESP32S31"] IDF-14628
while (REG_GET_FIELD(SPI_MEM_C_XTS_STATE_REG, SPI_XTS_STATE) == 0x1) {
}
}
/**
@@ -113,7 +123,9 @@ static inline void spi_flash_encrypt_ll_calculate_wait_idle(void)
*/
static inline void spi_flash_encrypt_ll_done(void)
{
// TODO: ["ESP32S31"] IDF-14628
REG_SET_BIT(SPI_MEM_C_XTS_RELEASE_REG, SPI_XTS_RELEASE);
while (REG_GET_FIELD(SPI_MEM_C_XTS_STATE_REG, SPI_XTS_STATE) != 0x3) {
}
}
/**
@@ -121,7 +133,7 @@ static inline void spi_flash_encrypt_ll_done(void)
*/
static inline void spi_flash_encrypt_ll_destroy(void)
{
// TODO: ["ESP32S31"] IDF-14628
REG_SET_BIT(SPI_MEM_C_XTS_DESTROY_REG, SPI_XTS_DESTROY);
}
/**
@@ -132,7 +144,38 @@ static inline void spi_flash_encrypt_ll_destroy(void)
*/
static inline bool spi_flash_encrypt_ll_check(uint32_t address, uint32_t length)
{
return 0;//((address % length) == 0) ? true : false;
return ((address % length) == 0) ? true : false;
}
/**
* @brief Enable the pseudo-round function during XTS-AES operations
*
* @param mode set the mode for pseudo rounds, zero to disable, with increasing security upto three.
* @param base basic number of pseudo rounds, zero if disable
* @param increment increment number of pseudo rounds, zero if disable
* @param key_rng_cnt update frequency of the pseudo-key, zero if disable
*/
static inline void spi_flash_encrypt_ll_enable_pseudo_rounds(esp_xts_aes_psuedo_rounds_state_t mode, uint8_t base, uint8_t increment, uint8_t key_rng_cnt)
{
REG_SET_FIELD(SPI_MEM_C_XTS_PSEUDO_ROUND_CONF_REG, SPI_MEM_C_MODE_PSEUDO, mode);
if (mode != ESP_XTS_AES_PSEUDO_ROUNDS_DISABLE) {
REG_SET_FIELD(SPI_MEM_C_XTS_PSEUDO_ROUND_CONF_REG, SPI_MEM_C_PSEUDO_BASE, base);
REG_SET_FIELD(SPI_MEM_C_XTS_PSEUDO_ROUND_CONF_REG, SPI_MEM_C_PSEUDO_INC, increment);
REG_SET_FIELD(SPI_MEM_C_XTS_PSEUDO_ROUND_CONF_REG, SPI_MEM_C_PSEUDO_RNG_CNT, key_rng_cnt);
} else {
REG_SET_FIELD(SPI_MEM_C_XTS_PSEUDO_ROUND_CONF_REG, SPI_MEM_C_PSEUDO_BASE, 0);
REG_SET_FIELD(SPI_MEM_C_XTS_PSEUDO_ROUND_CONF_REG, SPI_MEM_C_PSEUDO_INC, 0);
REG_SET_FIELD(SPI_MEM_C_XTS_PSEUDO_ROUND_CONF_REG, SPI_MEM_C_PSEUDO_RNG_CNT, 0);
}
}
/**
* @brief Check if the pseudo round function is supported
*/
static inline bool spi_flash_encrypt_ll_is_pseudo_rounds_function_supported(void)
{
return true;
}
#ifdef __cplusplus