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Merge branch 'feature/esp32h21_esp32h4_ledc_support' into 'master'

Browse Source 
feat(ledc): Add LEDC support for ESP32H21 and ESP32H4

Closes IDF-12343, IDF-12344, IDF-12920, IDF-11568, IDF-11569, IDF-12115, and IDF-13672

See merge request espressif/esp-idf!41172
This commit is contained in:
Song Ruo Jing
2025-09-17 10:55:00 +08:00
parent a3b8073d96 1cb1acd02e
commit addfa2aa01
93 changed files with 2836 additions and 671 deletions
Download Patch File Download Diff File Expand all files Collapse all files
components/soc/esp32c2/include/soc/Kconfig.soc_caps.in
-12
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@@ -335,18 +335,6 @@ config SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP
bool
default y
config SOC_DEDIC_GPIO_OUT_CHANNELS_NUM
int
default 8
config SOC_DEDIC_GPIO_IN_CHANNELS_NUM
int
default 8
config SOC_DEDIC_PERIPH_ALWAYS_ENABLE
bool
default y
config SOC_I2C_NUM
int
default 1
components/soc/esp32c2/include/soc/soc_caps.h
+1 -6
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2021-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -154,11 +154,6 @@
// "RTC"_IOs and DIG_IOs can be hold during deep sleep and after waking up
#define SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP (1)
/*-------------------------- Dedicated GPIO CAPS -----------------------------*/
#define SOC_DEDIC_GPIO_OUT_CHANNELS_NUM (8) /*!< 8 outward channels on each CPU core */
#define SOC_DEDIC_GPIO_IN_CHANNELS_NUM (8) /*!< 8 inward channels on each CPU core */
#define SOC_DEDIC_PERIPH_ALWAYS_ENABLE (1) /*!< The dedicated GPIO (a.k.a. fast GPIO) is featured by some customized CPU instructions, which is always enabled */
/*-------------------------- I2C CAPS ----------------------------------------*/
// ESP32-C2 has 1 I2C
#define SOC_I2C_NUM (1U)
components/soc/esp32c2/include/soc/soc_caps_full.h
+4
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@@ -19,3 +19,7 @@
/*--------------------------- Watch Dog ------------------------------------------*/
#define _SOC_CAPS_WDT_MWDTS_PER_TIMG 1 // Number of main watchdog timers in each Timer Group
/*------------------------------- Dedicated GPIO ------------------------------*/
#define _SOC_CAPS_DEDIC_GPIO_OUT_CHANS_PER_CPU 8 /*!< 8 outward channels on each CPU core */
#define _SOC_CAPS_DEDIC_GPIO_IN_CHANS_PER_CPU 8 /*!< 8 inward channels on each CPU core */
components/soc/esp32c3/include/soc/Kconfig.soc_caps.in
-12
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@@ -431,18 +431,6 @@ config SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP
bool
default y
config SOC_DEDIC_GPIO_OUT_CHANNELS_NUM
int
default 8
config SOC_DEDIC_GPIO_IN_CHANNELS_NUM
int
default 8
config SOC_DEDIC_PERIPH_ALWAYS_ENABLE
bool
default y
config SOC_I2C_NUM
int
default 1
components/soc/esp32c3/include/soc/soc_caps.h
-5
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@@ -193,11 +193,6 @@
// "RTC"_IOs and DIG_IOs can be hold during deep sleep and after waking up
#define SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP (1)
/*-------------------------- Dedicated GPIO CAPS -----------------------------*/
#define SOC_DEDIC_GPIO_OUT_CHANNELS_NUM (8) /*!< 8 outward channels on each CPU core */
#define SOC_DEDIC_GPIO_IN_CHANNELS_NUM (8) /*!< 8 inward channels on each CPU core */
#define SOC_DEDIC_PERIPH_ALWAYS_ENABLE (1) /*!< The dedicated GPIO (a.k.a. fast GPIO) is featured by some customized CPU instructions, which is always enabled */
/*-------------------------- I2C CAPS ----------------------------------------*/
// ESP32-C3 has 1 I2C
#define SOC_I2C_NUM (1U)
components/soc/esp32c3/include/soc/soc_caps_full.h
+4
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@@ -23,3 +23,7 @@
/*--------------------------- SDM (Sigma-Delta Modulator) ------------------------*/
#define _SOC_CAPS_SDM_INST_NUM 1 // Number of SDM instances
#define _SOC_CAPS_SDM_CHANS_PER_INST 4 // Number of channels in each SDM instance
/*------------------------------- Dedicated GPIO ------------------------------*/
#define _SOC_CAPS_DEDIC_GPIO_OUT_CHANS_PER_CPU 8 /*!< 8 outward channels on each CPU core */
#define _SOC_CAPS_DEDIC_GPIO_IN_CHANS_PER_CPU 8 /*!< 8 inward channels on each CPU core */
components/soc/esp32c5/include/soc/Kconfig.soc_caps.in
-12
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@@ -623,18 +623,6 @@ config SOC_RTCIO_EDGE_WAKE_SUPPORTED
bool
default y
config SOC_DEDIC_GPIO_OUT_CHANNELS_NUM
int
default 8
config SOC_DEDIC_GPIO_IN_CHANNELS_NUM
int
default 8
config SOC_DEDIC_PERIPH_ALWAYS_ENABLE
bool
default y
config SOC_SDM_SUPPORT_SLEEP_RETENTION
bool
default y
components/soc/esp32c5/include/soc/soc_caps.h
+3 -5
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@@ -257,12 +257,10 @@
#define SOC_RTCIO_WAKE_SUPPORTED 1
#define SOC_RTCIO_EDGE_WAKE_SUPPORTED 1
/*-------------------------- Dedicated GPIO CAPS -----------------------------*/
#define SOC_DEDIC_GPIO_OUT_CHANNELS_NUM (8) /*!< 8 outward channels on each CPU core */
#define SOC_DEDIC_GPIO_IN_CHANNELS_NUM (8) /*!< 8 inward channels on each CPU core */
#define SOC_DEDIC_PERIPH_ALWAYS_ENABLE (1) /*!< The dedicated GPIO (a.k.a. fast GPIO) is featured by some customized CPU instructions, which is always enabled */
/*-------------------------- Sigma Delta Modulator CAPS -----------------*/
#define SOC_SDM_SUPPORT_SLEEP_RETENTION 1
/*-------------------------- ETM CAPS -----------------------------------*/
#define SOC_ETM_SUPPORT_SLEEP_RETENTION 1
/*------------------------- Analog Comparator CAPS ---------------------------*/
components/soc/esp32c5/include/soc/soc_caps_full.h
+4
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@@ -20,6 +20,10 @@
/*--------------------------- Watch Dog ------------------------------------------*/
#define _SOC_CAPS_WDT_MWDTS_PER_TIMG 1 // Number of main watchdog timers in each Timer Group
/*------------------------------- Dedicated GPIO ------------------------------*/
#define _SOC_CAPS_DEDIC_GPIO_OUT_CHANS_PER_CPU 8 /*!< 8 outward channels on each CPU core */
#define _SOC_CAPS_DEDIC_GPIO_IN_CHANS_PER_CPU 8 /*!< 8 inward channels on each CPU core */
/*--------------------------- SDM (Sigma-Delta Modulator) ------------------------*/
#define _SOC_CAPS_SDM_INST_NUM 1 // Number of SDM instances
#define _SOC_CAPS_SDM_CHANS_PER_INST 4 // Number of channels in each SDM instance
components/soc/esp32c6/include/soc/Kconfig.soc_caps.in
-12
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@@ -559,18 +559,6 @@ config SOC_RTCIO_EDGE_WAKE_SUPPORTED
bool
default y
config SOC_DEDIC_GPIO_OUT_CHANNELS_NUM
int
default 8
config SOC_DEDIC_GPIO_IN_CHANNELS_NUM
int
default 8
config SOC_DEDIC_PERIPH_ALWAYS_ENABLE
bool
default y
config SOC_SDM_SUPPORT_SLEEP_RETENTION
bool
default y
components/soc/esp32c6/include/soc/soc_caps.h
+3 -5
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@@ -237,12 +237,10 @@
#define SOC_RTCIO_WAKE_SUPPORTED 1
#define SOC_RTCIO_EDGE_WAKE_SUPPORTED 1
/*-------------------------- Dedicated GPIO CAPS -----------------------------*/
#define SOC_DEDIC_GPIO_OUT_CHANNELS_NUM (8) /*!< 8 outward channels on each CPU core */
#define SOC_DEDIC_GPIO_IN_CHANNELS_NUM (8) /*!< 8 inward channels on each CPU core */
#define SOC_DEDIC_PERIPH_ALWAYS_ENABLE (1) /*!< The dedicated GPIO (a.k.a. fast GPIO) is featured by some customized CPU instructions, which is always enabled */
/*-------------------------- Sigma Delta Modulator CAPS -----------------*/
#define SOC_SDM_SUPPORT_SLEEP_RETENTION 1
/*-------------------------- ETM CAPS -----------------------------------*/
#define SOC_ETM_SUPPORT_SLEEP_RETENTION 1
/*-------------------------- I2C CAPS ----------------------------------------*/
components/soc/esp32c6/include/soc/soc_caps_full.h
+4
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@@ -20,6 +20,10 @@
/*--------------------------- Watch Dog ------------------------------------------*/
#define _SOC_CAPS_WDT_MWDTS_PER_TIMG 1 // Number of main watchdog timers in each Timer Group
/*------------------------------- Dedicated GPIO ------------------------------*/
#define _SOC_CAPS_DEDIC_GPIO_OUT_CHANS_PER_CPU 8 /*!< 8 outward channels on each CPU core */
#define _SOC_CAPS_DEDIC_GPIO_IN_CHANS_PER_CPU 8 /*!< 8 inward channels on each CPU core */
/*--------------------------- SDM (Sigma-Delta Modulator) ------------------------*/
#define _SOC_CAPS_SDM_INST_NUM 1 // Number of SDM instances
#define _SOC_CAPS_SDM_CHANS_PER_INST 4 // Number of channels in each SDM instance
components/soc/esp32c61/include/soc/Kconfig.soc_caps.in
-12
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@@ -503,18 +503,6 @@ config SOC_RTCIO_EDGE_WAKE_SUPPORTED
bool
default y
config SOC_DEDIC_GPIO_OUT_CHANNELS_NUM
int
default 8
config SOC_DEDIC_GPIO_IN_CHANNELS_NUM
int
default 8
config SOC_DEDIC_PERIPH_ALWAYS_ENABLE
bool
default y
config SOC_ANA_CMPR_NUM
int
default 1
components/soc/esp32c61/include/soc/soc_caps.h
+1 -5
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@@ -161,6 +161,7 @@
#define SOC_AHB_GDMA_SUPPORT_PSRAM 1
#define SOC_GDMA_SUPPORT_WEIGHTED_ARBITRATION 1
/*-------------------------- ETM CAPS -----------------------------------*/
#define SOC_ETM_SUPPORT_SLEEP_RETENTION 1
/*-------------------------- GPIO CAPS ---------------------------------------*/
@@ -216,11 +217,6 @@
#define SOC_RTCIO_WAKE_SUPPORTED 1
#define SOC_RTCIO_EDGE_WAKE_SUPPORTED 1
/*-------------------------- Dedicated GPIO CAPS -----------------------------*/
#define SOC_DEDIC_GPIO_OUT_CHANNELS_NUM (8) /*!< 8 outward channels on each CPU core */
#define SOC_DEDIC_GPIO_IN_CHANNELS_NUM (8) /*!< 8 inward channels on each CPU core */
#define SOC_DEDIC_PERIPH_ALWAYS_ENABLE (1) /*!< The dedicated GPIO (a.k.a. fast GPIO) is featured by some customized CPU instructions, which is always enabled */
/*------------------------- Analog Comparator CAPS ---------------------------*/
#define SOC_ANA_CMPR_NUM (1U)
#define SOC_ANA_CMPR_CAN_DISTINGUISH_EDGE (1) // Support positive/negative/any cross interrupt
components/soc/esp32c61/include/soc/soc_caps_full.h
+4
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@@ -20,6 +20,10 @@
/*--------------------------- Watch Dog ------------------------------------------*/
#define _SOC_CAPS_WDT_MWDTS_PER_TIMG 1 // Number of main watchdog timers in each Timer Group
/*------------------------------- Dedicated GPIO ------------------------------*/
#define _SOC_CAPS_DEDIC_GPIO_OUT_CHANS_PER_CPU 8 /*!< 8 outward channels on each CPU core */
#define _SOC_CAPS_DEDIC_GPIO_IN_CHANS_PER_CPU 8 /*!< 8 inward channels on each CPU core */
/*--------------------------- ETM (Event Task Matrix) ----------------------------*/
#define _SOC_CAPS_ETM_INST_NUM 1 // Number of ETM instances
#define _SOC_CAPS_ETM_CHANS_PER_INST 50 // Number of channels in each ETM instance
components/soc/esp32h2/include/soc/Kconfig.soc_caps.in
-12
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@@ -563,18 +563,6 @@ config SOC_RTCIO_HOLD_SUPPORTED
bool
default y
config SOC_DEDIC_GPIO_OUT_CHANNELS_NUM
int
default 8
config SOC_DEDIC_GPIO_IN_CHANNELS_NUM
int
default 8
config SOC_DEDIC_PERIPH_ALWAYS_ENABLE
bool
default y
config SOC_SDM_SUPPORT_SLEEP_RETENTION
bool
default y
components/soc/esp32h2/include/soc/soc_caps.h
+3 -5
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@@ -257,12 +257,10 @@
#define SOC_RTCIO_PIN_COUNT (8U)
#define SOC_RTCIO_HOLD_SUPPORTED (1)
/*-------------------------- Dedicated GPIO CAPS -----------------------------*/
#define SOC_DEDIC_GPIO_OUT_CHANNELS_NUM (8) /*!< 8 outward channels on each CPU core */
#define SOC_DEDIC_GPIO_IN_CHANNELS_NUM (8) /*!< 8 inward channels on each CPU core */
#define SOC_DEDIC_PERIPH_ALWAYS_ENABLE (1) /*!< The dedicated GPIO (a.k.a. fast GPIO) is featured by some customized CPU instructions, which is always enabled */
/*-------------------------- Sigma Delta Modulator CAPS -----------------*/
#define SOC_SDM_SUPPORT_SLEEP_RETENTION 1
/*-------------------------- ETM CAPS -----------------------------------*/
#define SOC_ETM_SUPPORT_SLEEP_RETENTION 1
/*------------------------- Analog Comparator CAPS ---------------------------*/
components/soc/esp32h2/include/soc/soc_caps_full.h
+4
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@@ -20,6 +20,10 @@
/*--------------------------- Watch Dog ------------------------------------------*/
#define _SOC_CAPS_WDT_MWDTS_PER_TIMG 1 // Number of main watchdog timers in each Timer Group
/*------------------------------- Dedicated GPIO ------------------------------*/
#define _SOC_CAPS_DEDIC_GPIO_OUT_CHANS_PER_CPU 8 /*!< 8 outward channels on each CPU core */
#define _SOC_CAPS_DEDIC_GPIO_IN_CHANS_PER_CPU 8 /*!< 8 inward channels on each CPU core */
/*--------------------------- SDM (Sigma-Delta Modulator) ------------------------*/
#define _SOC_CAPS_SDM_INST_NUM 1 // Number of SDM instances
#define _SOC_CAPS_SDM_CHANS_PER_INST 4 // Number of channels in each SDM instance
components/soc/esp32h21/include/soc/Kconfig.soc_caps.in
+40 -12
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@@ -47,6 +47,10 @@ config SOC_GPSPI_SUPPORTED
bool
default y
config SOC_LEDC_SUPPORTED
bool
default y
config SOC_I2C_SUPPORTED
bool
default y
@@ -395,18 +399,6 @@ config SOC_RTCIO_HOLD_SUPPORTED
bool
default y
config SOC_DEDIC_GPIO_OUT_CHANNELS_NUM
int
default 8
config SOC_DEDIC_GPIO_IN_CHANNELS_NUM
int
default 8
config SOC_DEDIC_PERIPH_ALWAYS_ENABLE
bool
default y
config SOC_ANA_CMPR_NUM
int
default 1
@@ -471,10 +463,46 @@ config SOC_I2C_SLAVE_SUPPORT_SLAVE_UNMATCH
bool
default y
config SOC_LEDC_SUPPORT_PLL_DIV_CLOCK
bool
default y
config SOC_LEDC_SUPPORT_XTAL_CLOCK
bool
default y
config SOC_LEDC_TIMER_NUM
int
default 4
config SOC_LEDC_CHANNEL_NUM
int
default 6
config SOC_LEDC_TIMER_BIT_WIDTH
int
default 20
config SOC_LEDC_SUPPORT_FADE_STOP
bool
default y
config SOC_LEDC_GAMMA_CURVE_FADE_SUPPORTED
bool
default y
config SOC_LEDC_GAMMA_CURVE_FADE_RANGE_MAX
int
default 16
config SOC_LEDC_FADE_PARAMS_BIT_WIDTH
int
default 10
config SOC_LEDC_SUPPORT_SLEEP_RETENTION
bool
default y
config SOC_PCNT_SUPPORT_RUNTIME_THRES_UPDATE
bool
default y
components/soc/esp32h21/include/soc/clk_tree_defs.h
+17
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@@ -268,6 +268,23 @@ typedef enum {
I2C_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the default source clock */
} soc_periph_i2c_clk_src_t;
//////////////////////////////////////////////////LEDC/////////////////////////////////////////////////////////////////
/**
* @brief Array initializer for all supported clock sources of LEDC
*/
#define SOC_LEDC_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_PLL_F96M, SOC_MOD_CLK_RC_FAST}
/**
* @brief Type of LEDC clock source, reserved for the legacy LEDC driver
*/
typedef enum {
LEDC_AUTO_CLK = 0, /*!< LEDC source clock will be automatically selected based on the giving resolution and duty parameter when init the timer*/
LEDC_USE_PLL_DIV_CLK = SOC_MOD_CLK_PLL_F96M, /*!< Select PLL_F96M clock as the source clock */
LEDC_USE_RC_FAST_CLK = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */
LEDC_USE_XTAL_CLK = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
} soc_periph_ledc_clk_src_legacy_t;
/////////////////////////////////////////////////SPI////////////////////////////////////////////////////////////////////
/**
components/soc/esp32h21/include/soc/soc_caps.h
+14 -14
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@@ -45,7 +45,7 @@
// #define SOC_I2S_SUPPORTED 1 //TODO: [ESP32H21] IDF-11606, IDF-11608
// #define SOC_SDM_SUPPORTED 1 //TODO: [ESP32H21] IDF-11573
#define SOC_GPSPI_SUPPORTED 1
// #define SOC_LEDC_SUPPORTED 1 //TODO: [ESP32H21] IDF-11568
#define SOC_LEDC_SUPPORTED 1
#define SOC_I2C_SUPPORTED 1
#define SOC_SYSTIMER_SUPPORTED 1
// #define SOC_SUPPORT_COEXISTENCE 1 //TODO: [ESP32H21] IDF-11658, IDF-11659, IDF-11660
@@ -233,7 +233,10 @@
// #define SOC_CLOCKOUT_HAS_SOURCE_GATE (1)
// #define SOC_GPIO_CLOCKOUT_CHANNEL_NUM (3)
/*-------------------------- Sigma Delta Modulator CAPS -----------------*/
#define SOC_SDM_SUPPORT_SLEEP_RETENTION 1
/*-------------------------- ETM CAPS -----------------------------------*/
#define SOC_ETM_SUPPORT_SLEEP_RETENTION 1
/*-------------------------- RTCIO CAPS --------------------------------------*/
@@ -242,11 +245,6 @@
#define SOC_RTCIO_PIN_COUNT (7U)
#define SOC_RTCIO_HOLD_SUPPORTED (1)
/*-------------------------- Dedicated GPIO CAPS -----------------------------*/
#define SOC_DEDIC_GPIO_OUT_CHANNELS_NUM (8) /*!< 8 outward channels on each CPU core */
#define SOC_DEDIC_GPIO_IN_CHANNELS_NUM (8) /*!< 8 inward channels on each CPU core */
#define SOC_DEDIC_PERIPH_ALWAYS_ENABLE (1) /*!< The dedicated GPIO (a.k.a. fast GPIO) is featured by some customized CPU instructions, which is always enabled */
/*------------------------- Analog Comparator CAPS ---------------------------*/
#define SOC_ANA_CMPR_NUM (1U)
#define SOC_ANA_CMPR_INTR_SHARE_WITH_GPIO (1)
@@ -287,14 +285,16 @@
// #define SOC_I2S_TDM_FULL_DATA_WIDTH (1) /*!< No limitation to data bit width when using multiple slots */
/*-------------------------- LEDC CAPS ---------------------------------------*/
// #define SOC_LEDC_SUPPORT_PLL_DIV_CLOCK (1)
// #define SOC_LEDC_SUPPORT_XTAL_CLOCK (1)
#define SOC_LEDC_CHANNEL_NUM (6) // Check, todo IDF-11568
// #define SOC_LEDC_TIMER_BIT_WIDTH (20)
// #define SOC_LEDC_SUPPORT_FADE_STOP (1)
// #define SOC_LEDC_GAMMA_CURVE_FADE_SUPPORTED (1)
// #define SOC_LEDC_GAMMA_CURVE_FADE_RANGE_MAX (16)
// #define SOC_LEDC_FADE_PARAMS_BIT_WIDTH (10)
#define SOC_LEDC_SUPPORT_PLL_DIV_CLOCK (1)
#define SOC_LEDC_SUPPORT_XTAL_CLOCK (1)
#define SOC_LEDC_TIMER_NUM (4)
#define SOC_LEDC_CHANNEL_NUM (6)
#define SOC_LEDC_TIMER_BIT_WIDTH (20)
#define SOC_LEDC_SUPPORT_FADE_STOP (1)
#define SOC_LEDC_GAMMA_CURVE_FADE_SUPPORTED (1)
#define SOC_LEDC_GAMMA_CURVE_FADE_RANGE_MAX (16)
#define SOC_LEDC_FADE_PARAMS_BIT_WIDTH (10)
#define SOC_LEDC_SUPPORT_SLEEP_RETENTION (1)
/*-------------------------- MPU CAPS ----------------------------------------*/
// #define SOC_MPU_CONFIGURABLE_REGIONS_SUPPORTED 0
components/soc/esp32h21/ledc_periph.c
+159
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@@ -0,0 +1,159 @@
/*
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/ledc_periph.h"
#include "soc/gpio_sig_map.h"
/*
Bunch of constants for every LEDC peripheral: GPIO signals
*/
const ledc_signal_conn_t ledc_periph_signal[1] = {
{
.sig_out0_idx = LEDC_LS_SIG_OUT0_IDX,
}
};
/**
* LEDC registers to be saved for sleep retention
*
* channel:
* LEDC_CHx_CONF0_REG, LEDC_CHx_HPOINT_REG, LEDC_CHx_DUTY_R_REG -> LEDC_CHx_DUTY_REG,
*
* timer:
* LEDC_TIMERn_CONF_REG, LEDC_TIMERn_CMP_REG,
*
* common:
* LEDC_INT_ENA_REG,
* LEDC_EVT_TASK_EN0_REG, LEDC_EVT_TASK_EN1_REG, LEDC_EVT_TASK_EN2_REG,
* LEDC_CONF_REG,
*
* Note 1: Gamma feature is hard to do hardware retention, will consider to use software to do the backup and restore.
* We won't start a fade automatically after wake-up.
* Instead, we will only start a PWM with a fixed duty cycle, the same value as before entering the sleep.
*
* Note 2: For timer/channel registers to get synced, update bits need to be set
*
* Note 3: Retention backup/restore does not rely on LEDC function clock enabled
*/
#define LEDC_COMMON_RETENTION_REGS_CNT 5
#define LEDC_COMMON_RETENTION_REGS_BASE (DR_REG_LEDC_BASE + 0xc8)
static const uint32_t ledc_common_regs_map[4] = {0x1, 0x1c00000, 0x400, 0x0};
static const regdma_entries_config_t ledc_common_regdma_entries[] = {
// If a fade is in process, the DUTY_CHNG_END_CHx intr bit is enabled, however, we don't want it to be restored after wake-up (no fade after wake-up).
// Therefore, we can set it to 0 before backup the LEDC_INT_ENA_REG.
[0] = {
.config = REGDMA_LINK_WRITE_INIT(REGDMA_LEDC_LINK(0x00),
LEDC_INT_ENA_REG, 0,
(LEDC_DUTY_CHNG_END_CH0_INT_ENA_M | LEDC_DUTY_CHNG_END_CH1_INT_ENA_M | LEDC_DUTY_CHNG_END_CH2_INT_ENA_M | LEDC_DUTY_CHNG_END_CH3_INT_ENA_M | LEDC_DUTY_CHNG_END_CH4_INT_ENA_M | LEDC_DUTY_CHNG_END_CH5_INT_ENA_M), 0, 1),
.owner = LEDC_RETENTION_ENTRY
},
[1] = {
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_LEDC_LINK(0x01),
LEDC_COMMON_RETENTION_REGS_BASE, LEDC_COMMON_RETENTION_REGS_BASE,
LEDC_COMMON_RETENTION_REGS_CNT, 0, 0,
ledc_common_regs_map[0], ledc_common_regs_map[1],
ledc_common_regs_map[2], ledc_common_regs_map[3]),
.owner = LEDC_RETENTION_ENTRY
},
};
#define LEDC_TIMER_RETENTION_ENTRIES(timer) { \
[0] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_LEDC_LINK(0x00), \
LEDC_TIMER##timer##_CONF_REG, LEDC_TIMER##timer##_CONF_REG, \
1, 0, 0), \
.owner = LEDC_RETENTION_ENTRY }, \
[1] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_LEDC_LINK(0x01), \
LEDC_TIMER##timer##_CMP_REG, LEDC_TIMER##timer##_CMP_REG, \
1, 0, 0), \
.owner = LEDC_RETENTION_ENTRY }, \
[2] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_LEDC_LINK(0x02), \
LEDC_TIMER##timer##_CONF_REG, LEDC_TIMER##timer##_PARA_UP, \
LEDC_TIMER##timer##_PARA_UP_M, 1, 0), \
.owner = LEDC_RETENTION_ENTRY }, \
}
#define LEDC_CHANNEL_RETENTION_REGS_CNT 2
static const uint32_t ledc_channel_regs_map[4] = {0x3, 0x0, 0x0, 0x0};
#define LEDC_CHANNEL_RETENTION_ENTRIES(chan) { \
[0] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_LEDC_LINK(0x00), \
LEDC_CH##chan##_CONF0_REG, LEDC_CH##chan##_CONF0_REG, \
LEDC_CHANNEL_RETENTION_REGS_CNT, 0, 0, \
ledc_channel_regs_map[0], ledc_channel_regs_map[1], \
ledc_channel_regs_map[2], ledc_channel_regs_map[3]), \
.owner = LEDC_RETENTION_ENTRY }, \
[1] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_LEDC_LINK(0x01), \
LEDC_CH##chan##_DUTY_R_REG, LEDC_CH##chan##_DUTY_REG, \
1, 0, 0), \
.owner = LEDC_RETENTION_ENTRY }, \
[2] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_LEDC_LINK(0x02), \
LEDC_CH##chan##_CONF1_REG, LEDC_DUTY_START_CH##chan, \
LEDC_DUTY_START_CH##chan##_M, 1, 0), \
.owner = LEDC_RETENTION_ENTRY }, \
[3] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_LEDC_LINK(0x03), \
LEDC_CH##chan##_CONF0_REG, LEDC_PARA_UP_CH##chan, \
LEDC_PARA_UP_CH##chan##_M, 1, 0), \
.owner = LEDC_RETENTION_ENTRY }, \
}
static const regdma_entries_config_t ledc_timer0_regdma_entries[] = LEDC_TIMER_RETENTION_ENTRIES(0);
static const regdma_entries_config_t ledc_timer1_regdma_entries[] = LEDC_TIMER_RETENTION_ENTRIES(1);
static const regdma_entries_config_t ledc_timer2_regdma_entries[] = LEDC_TIMER_RETENTION_ENTRIES(2);
static const regdma_entries_config_t ledc_timer3_regdma_entries[] = LEDC_TIMER_RETENTION_ENTRIES(3);
static const regdma_entries_config_t ledc_channel0_regdma_entries[] = LEDC_CHANNEL_RETENTION_ENTRIES(0);
static const regdma_entries_config_t ledc_channel1_regdma_entries[] = LEDC_CHANNEL_RETENTION_ENTRIES(1);
static const regdma_entries_config_t ledc_channel2_regdma_entries[] = LEDC_CHANNEL_RETENTION_ENTRIES(2);
static const regdma_entries_config_t ledc_channel3_regdma_entries[] = LEDC_CHANNEL_RETENTION_ENTRIES(3);
static const regdma_entries_config_t ledc_channel4_regdma_entries[] = LEDC_CHANNEL_RETENTION_ENTRIES(4);
static const regdma_entries_config_t ledc_channel5_regdma_entries[] = LEDC_CHANNEL_RETENTION_ENTRIES(5);
const ledc_reg_retention_info_t ledc_reg_retention_info = {
.common = {
.regdma_entry_array = ledc_common_regdma_entries,
.array_size = ARRAY_SIZE(ledc_common_regdma_entries),
},
.timer[0] = {
.regdma_entry_array = ledc_timer0_regdma_entries,
.array_size = ARRAY_SIZE(ledc_timer0_regdma_entries),
},
.timer[1] = {
.regdma_entry_array = ledc_timer1_regdma_entries,
.array_size = ARRAY_SIZE(ledc_timer1_regdma_entries),
},
.timer[2] = {
.regdma_entry_array = ledc_timer2_regdma_entries,
.array_size = ARRAY_SIZE(ledc_timer2_regdma_entries),
},
.timer[3] = {
.regdma_entry_array = ledc_timer3_regdma_entries,
.array_size = ARRAY_SIZE(ledc_timer3_regdma_entries),
},
.channel[0] = {
.regdma_entry_array = ledc_channel0_regdma_entries,
.array_size = ARRAY_SIZE(ledc_channel0_regdma_entries),
},
.channel[1] = {
.regdma_entry_array = ledc_channel1_regdma_entries,
.array_size = ARRAY_SIZE(ledc_channel1_regdma_entries),
},
.channel[2] = {
.regdma_entry_array = ledc_channel2_regdma_entries,
.array_size = ARRAY_SIZE(ledc_channel2_regdma_entries),
},
.channel[3] = {
.regdma_entry_array = ledc_channel3_regdma_entries,
.array_size = ARRAY_SIZE(ledc_channel3_regdma_entries),
},
.channel[4] = {
.regdma_entry_array = ledc_channel4_regdma_entries,
.array_size = ARRAY_SIZE(ledc_channel4_regdma_entries),
},
.channel[5] = {
.regdma_entry_array = ledc_channel5_regdma_entries,
.array_size = ARRAY_SIZE(ledc_channel5_regdma_entries),
},
.module_id = SLEEP_RETENTION_MODULE_LEDC,
};
components/soc/esp32h21/register/soc/ledc_struct.h
+128 -142
View File
@@ -16,43 +16,43 @@ extern "C" {
*/
typedef union {
struct {
/** timer_sel_chn : R/W; bitpos: [1:0]; default: 0;
/** timer_sel : R/W; bitpos: [1:0]; default: 0;
* This field is used to select one of timers for channel n.
*
* 0: select timer0, 1: select timer1, 2: select timer2, 3: select timer3
*/
uint32_t timer_sel_chn:2;
/** sig_out_en_chn : R/W; bitpos: [2]; default: 0;
uint32_t timer_sel:2;
/** sig_out_en : R/W; bitpos: [2]; default: 0;
* Set this bit to enable signal output on channel n.
*/
uint32_t sig_out_en_chn:1;
/** idle_lv_chn : R/W; bitpos: [3]; default: 0;
uint32_t sig_out_en:1;
/** idle_lv : R/W; bitpos: [3]; default: 0;
* This bit is used to control the output value when channel n is inactive (when
* LEDC_SIG_OUT_EN_CHn is 0).
*/
uint32_t idle_lv_chn:1;
/** para_up_chn : WT; bitpos: [4]; default: 0;
uint32_t idle_lv:1;
/** para_up : WT; bitpos: [4]; default: 0;
* This bit is used to update LEDC_HPOINT_CHn, LEDC_DUTY_START_CHn,
* LEDC_SIG_OUT_EN_CHn, LEDC_TIMER_SEL_CHn, LEDC_DUTY_NUM_CHn, LEDC_DUTY_CYCLE_CHn,
* LEDC_DUTY_SCALE_CHn, LEDC_DUTY_INC_CHn, and LEDC_OVF_CNT_EN_CHn fields for channel
* n, and will be automatically cleared by hardware.
*/
uint32_t para_up_chn:1;
/** ovf_num_chn : R/W; bitpos: [14:5]; default: 0;
uint32_t para_up:1;
/** ovf_num : R/W; bitpos: [14:5]; default: 0;
* This register is used to configure the maximum times of overflow minus 1.
*
* The LEDC_OVF_CNT_CHn_INT interrupt will be triggered when channel n overflows for
* (LEDC_OVF_NUM_CHn + 1) times.
*/
uint32_t ovf_num_chn:10;
/** ovf_cnt_en_chn : R/W; bitpos: [15]; default: 0;
uint32_t ovf_num:10;
/** ovf_cnt_en : R/W; bitpos: [15]; default: 0;
* This bit is used to enable the ovf_cnt of channel n.
*/
uint32_t ovf_cnt_en_chn:1;
/** ovf_cnt_reset_chn : WT; bitpos: [16]; default: 0;
uint32_t ovf_cnt_en:1;
/** ovf_cnt_reset : WT; bitpos: [16]; default: 0;
* Set this bit to reset the ovf_cnt of channel n.
*/
uint32_t ovf_cnt_reset_chn:1;
uint32_t ovf_cnt_reset:1;
uint32_t reserved_17:15;
};
uint32_t val;
@@ -64,11 +64,11 @@ typedef union {
typedef union {
struct {
uint32_t reserved_0:31;
/** duty_start_chn : R/W/SC; bitpos: [31]; default: 0;
/** duty_start : R/W/SC; bitpos: [31]; default: 0;
* Other configured fields in LEDC_CHn_CONF1_REG will start to take effect when this
* bit is set to 1.
*/
uint32_t duty_start_chn:1;
uint32_t duty_start:1;
};
uint32_t val;
} ledc_chn_conf1_reg_t;
@@ -396,33 +396,33 @@ typedef union {
uint32_t val;
} ledc_evt_task_en2_reg_t;
/** Type of timern_cmp register
* Ledc timern compare value register.
/** Type of timerx_cmp register
* Ledc timer x compare value register.
*/
typedef union {
struct {
/** timern_cmp : R/W; bitpos: [19:0]; default: 0;
* This register stores ledc timern compare value.
/** cmp : R/W; bitpos: [19:0]; default: 0;
* This register stores ledc timer x compare value.
*/
uint32_t timern_cmp:20;
uint32_t cmp:20;
uint32_t reserved_20:12;
};
uint32_t val;
} ledc_timern_cmp_reg_t;
} ledc_timerx_cmp_reg_t;
/** Type of timern_cnt_cap register
* Ledc timern count value capture register.
/** Type of timerx_cnt_cap register
* Ledc timer x count value capture register.
*/
typedef union {
struct {
/** timern_cnt_cap : RO; bitpos: [19:0]; default: 0;
* This register stores ledc timern count value.
/** cnt_cap : RO; bitpos: [19:0]; default: 0;
* This register stores ledc timer x count value.
*/
uint32_t timern_cnt_cap:20;
uint32_t cnt_cap:20;
uint32_t reserved_20:12;
};
uint32_t val;
} ledc_timern_cnt_cap_reg_t;
} ledc_timerx_cnt_cap_reg_t;
/** Type of conf register
* Global ledc configuration register
@@ -496,11 +496,11 @@ typedef union {
*/
typedef union {
struct {
/** hpoint_chn : R/W; bitpos: [19:0]; default: 0;
/** hpoint : R/W; bitpos: [19:0]; default: 0;
* The output value changes to high when the selected timers has reached the value
* specified by this register.
*/
uint32_t hpoint_chn:20;
uint32_t hpoint:20;
uint32_t reserved_20:12;
};
uint32_t val;
@@ -513,12 +513,12 @@ typedef union {
*/
typedef union {
struct {
/** duty_chn : R/W; bitpos: [24:0]; default: 0;
/** duty : R/W; bitpos: [24:0]; default: 0;
* This register is used to change the output duty by controlling the Lpoint.
*
* The output value turns to low when the selected timers has reached the Lpoint.
*/
uint32_t duty_chn:25;
uint32_t duty:25;
uint32_t reserved_25:7;
};
uint32_t val;
@@ -529,10 +529,10 @@ typedef union {
*/
typedef union {
struct {
/** duty_chn_r : RO; bitpos: [24:0]; default: 0;
/** duty_r : RO; bitpos: [24:0]; default: 0;
* This register stores the current duty of output signal on channel n.
*/
uint32_t duty_chn_r:25;
uint32_t duty_r:25;
uint32_t reserved_25:7;
};
uint32_t val;
@@ -540,52 +540,52 @@ typedef union {
/** Group: Timer Register */
/** Type of timern_conf register
* Timer n configuration
/** Type of timerx_conf register
* Timer x configuration
*/
typedef union {
struct {
/** timern_duty_res : R/W; bitpos: [4:0]; default: 0;
* This register is used to control the range of the counter in timer n.
/** duty_res : R/W; bitpos: [4:0]; default: 0;
* This register is used to control the range of the counter in timer x.
*/
uint32_t timern_duty_res:5;
/** clk_div_timern : R/W; bitpos: [22:5]; default: 0;
* This register is used to configure the divisor for the divider in timer n.
uint32_t duty_res:5;
/** clk_div : R/W; bitpos: [22:5]; default: 0;
* This register is used to configure the divisor for the divider in timer x.
*
* The least significant eight bits represent the fractional part.
*/
uint32_t clk_div_timern:18;
/** timern_pause : R/W; bitpos: [23]; default: 0;
* This bit is used to suspend the counter in timer n.
uint32_t clk_div:18;
/** pause : R/W; bitpos: [23]; default: 0;
* This bit is used to suspend the counter in timer x.
*/
uint32_t timern_pause:1;
/** timern_rst : R/W; bitpos: [24]; default: 1;
* This bit is used to reset timer n. The counter will show 0 after reset.
uint32_t pause:1;
/** rst : R/W; bitpos: [24]; default: 1;
* This bit is used to reset timer x. The counter will show 0 after reset.
*/
uint32_t timern_rst:1;
uint32_t rst:1;
uint32_t reserved_25:1;
/** timern_para_up : WT; bitpos: [26]; default: 0;
/** para_up : WT; bitpos: [26]; default: 0;
* Set this bit to update LEDC_CLK_DIV_TIMERn and LEDC_TIMERn_DUTY_RES.
*/
uint32_t timern_para_up:1;
uint32_t para_up:1;
uint32_t reserved_27:5;
};
uint32_t val;
} ledc_timern_conf_reg_t;
} ledc_timerx_conf_reg_t;
/** Type of timern_value register
* Timer n current counter value
/** Type of timerx_value register
* Timer x current counter value
*/
typedef union {
struct {
/** timern_cnt : RO; bitpos: [19:0]; default: 0;
* This register stores the current counter value of timer n.
/** timer_cnt : RO; bitpos: [19:0]; default: 0;
* This register stores the current counter value of timer x.
*/
uint32_t timern_cnt:20;
uint32_t timer_cnt:20;
uint32_t reserved_20:12;
};
uint32_t val;
} ledc_timern_value_reg_t;
} ledc_timerx_value_reg_t;
/** Group: Interrupt Register */
@@ -924,28 +924,28 @@ typedef union {
*/
typedef union {
struct {
/** chn_gamma_duty_inc : R/W; bitpos: [0]; default: 0;
/** gamma_duty_inc : R/W; bitpos: [0]; default: 0;
* Ledc chn gamma duty inc of current ram write address.This register is used to
* increase or decrease the duty of output signal on channel n.
*
* 1: Increase 0: Decrease.
*/
uint32_t chn_gamma_duty_inc:1;
/** chn_gamma_duty_cycle : R/W; bitpos: [10:1]; default: 0;
uint32_t gamma_duty_inc:1;
/** gamma_duty_cycle : R/W; bitpos: [10:1]; default: 0;
* Ledc chn gamma duty cycle of current ram write address.The duty will change every
* LEDC_CHn_GAMMA_DUTY_CYCLE on channel n.
*/
uint32_t chn_gamma_duty_cycle:10;
/** chn_gamma_scale : R/W; bitpos: [20:11]; default: 0;
uint32_t gamma_duty_cycle:10;
/** gamma_scale : R/W; bitpos: [20:11]; default: 0;
* Ledc chn gamma scale of current ram write address.This register is used to
* configure the changing step scale of duty on channel n.
*/
uint32_t chn_gamma_scale:10;
/** chn_gamma_duty_num : R/W; bitpos: [30:21]; default: 0;
uint32_t gamma_scale:10;
/** gamma_duty_num : R/W; bitpos: [30:21]; default: 0;
* Ledc chn gamma duty num of current ram write address.This register is used to
* control the number of times the duty cycle will be changed.
*/
uint32_t chn_gamma_duty_num:10;
uint32_t gamma_duty_num:10;
uint32_t reserved_31:1;
};
uint32_t val;
@@ -956,10 +956,10 @@ typedef union {
*/
typedef union {
struct {
/** chn_gamma_wr_addr : R/W; bitpos: [3:0]; default: 0;
/** gamma_wr_addr : R/W; bitpos: [3:0]; default: 0;
* Ledc chn gamma ram write address.
*/
uint32_t chn_gamma_wr_addr:4;
uint32_t gamma_wr_addr:4;
uint32_t reserved_4:28;
};
uint32_t val;
@@ -970,10 +970,10 @@ typedef union {
*/
typedef union {
struct {
/** chn_gamma_rd_addr : R/W; bitpos: [3:0]; default: 0;
/** gamma_rd_addr : R/W; bitpos: [3:0]; default: 0;
* Ledc chn gamma ram read address.
*/
uint32_t chn_gamma_rd_addr:4;
uint32_t gamma_rd_addr:4;
uint32_t reserved_4:28;
};
uint32_t val;
@@ -984,10 +984,10 @@ typedef union {
*/
typedef union {
struct {
/** chn_gamma_rd_data : RO; bitpos: [30:0]; default: 0;
/** gamma_rd_data : RO; bitpos: [30:0]; default: 0;
* Ledc chn gamma ram read data.
*/
uint32_t chn_gamma_rd_data:31;
uint32_t gamma_rd_data:31;
uint32_t reserved_31:1;
};
uint32_t val;
@@ -1000,18 +1000,18 @@ typedef union {
*/
typedef union {
struct {
/** chn_gamma_entry_num : R/W; bitpos: [4:0]; default: 0;
/** gamma_entry_num : R/W; bitpos: [4:0]; default: 0;
* Ledc chn gamma entry num.
*/
uint32_t chn_gamma_entry_num:5;
/** chn_gamma_pause : WT; bitpos: [5]; default: 0;
uint32_t gamma_entry_num:5;
/** gamma_pause : WT; bitpos: [5]; default: 0;
* Ledc chn gamma pause, write 1 to pause.
*/
uint32_t chn_gamma_pause:1;
/** chn_gamma_resume : WT; bitpos: [6]; default: 0;
uint32_t gamma_pause:1;
/** gamma_resume : WT; bitpos: [6]; default: 0;
* Ledc chn gamma resume, write 1 to resume.
*/
uint32_t chn_gamma_resume:1;
uint32_t gamma_resume:1;
uint32_t reserved_7:25;
};
uint32_t val;
@@ -1035,83 +1035,69 @@ typedef union {
typedef struct {
volatile ledc_chn_conf0_reg_t ch0_conf0;
volatile ledc_chn_hpoint_reg_t ch0_hpoint;
volatile ledc_chn_duty_reg_t ch0_duty;
volatile ledc_chn_conf1_reg_t ch0_conf1;
volatile ledc_chn_duty_r_reg_t ch0_duty_r;
volatile ledc_chn_conf0_reg_t ch1_conf0;
volatile ledc_chn_hpoint_reg_t ch1_hpoint;
volatile ledc_chn_duty_reg_t ch1_duty;
volatile ledc_chn_conf1_reg_t ch1_conf1;
volatile ledc_chn_duty_r_reg_t ch1_duty_r;
volatile ledc_chn_conf0_reg_t ch2_conf0;
volatile ledc_chn_hpoint_reg_t ch2_hpoint;
volatile ledc_chn_duty_reg_t ch2_duty;
volatile ledc_chn_conf1_reg_t ch2_conf1;
volatile ledc_chn_duty_r_reg_t ch2_duty_r;
volatile ledc_chn_conf0_reg_t ch3_conf0;
volatile ledc_chn_hpoint_reg_t ch3_hpoint;
volatile ledc_chn_duty_reg_t ch3_duty;
volatile ledc_chn_conf1_reg_t ch3_conf1;
volatile ledc_chn_duty_r_reg_t ch3_duty_r;
volatile ledc_chn_conf0_reg_t ch4_conf0;
volatile ledc_chn_hpoint_reg_t ch4_hpoint;
volatile ledc_chn_duty_reg_t ch4_duty;
volatile ledc_chn_conf1_reg_t ch4_conf1;
volatile ledc_chn_duty_r_reg_t ch4_duty_r;
volatile ledc_chn_conf0_reg_t ch5_conf0;
volatile ledc_chn_hpoint_reg_t ch5_hpoint;
volatile ledc_chn_duty_reg_t ch5_duty;
volatile ledc_chn_conf1_reg_t ch5_conf1;
volatile ledc_chn_duty_r_reg_t ch5_duty_r;
volatile ledc_chn_conf0_reg_t conf0;
volatile ledc_chn_hpoint_reg_t hpoint;
volatile ledc_chn_duty_reg_t duty;
volatile ledc_chn_conf1_reg_t conf1;
volatile ledc_chn_duty_r_reg_t duty_rd;
} ledc_chn_reg_t;
typedef struct {
volatile ledc_chn_reg_t channel[6];
} ledc_ch_group_reg_t;
typedef struct {
volatile ledc_timerx_conf_reg_t conf;
volatile ledc_timerx_value_reg_t value;
} ledc_timerx_reg_t;
typedef struct {
volatile ledc_timerx_reg_t timer[4];
} ledc_timer_group_reg_t;
typedef struct {
volatile ledc_chn_gamma_wr_reg_t wr;
volatile ledc_chn_gamma_wr_addr_reg_t wr_addr;
volatile ledc_chn_gamma_rd_addr_reg_t rd_addr;
volatile ledc_chn_gamma_rd_data_reg_t rd_data;
} ledc_chn_gamma_reg_t;
typedef struct {
volatile ledc_chn_gamma_reg_t channel[6];
} ledc_ch_gamma_group_reg_t;
typedef struct {
volatile ledc_chn_gamma_conf_reg_t gamma_conf[6];
} ledc_ch_gamma_conf_group_reg_t;
typedef struct {
volatile ledc_timerx_cmp_reg_t cmp[4];
} ledc_timer_cmp_group_reg_t;
typedef struct {
volatile ledc_timerx_cnt_cap_reg_t cnt_cap[4];
} ledc_timer_cnt_cap_group_reg_t;
typedef struct ledc_dev_t {
volatile ledc_ch_group_reg_t channel_group[1];
uint32_t reserved_078[10];
volatile ledc_timern_conf_reg_t timer0_conf;
volatile ledc_timern_value_reg_t timer0_value;
volatile ledc_timern_conf_reg_t timer1_conf;
volatile ledc_timern_value_reg_t timer1_value;
volatile ledc_timern_conf_reg_t timer2_conf;
volatile ledc_timern_value_reg_t timer2_value;
volatile ledc_timern_conf_reg_t timer3_conf;
volatile ledc_timern_value_reg_t timer3_value;
volatile ledc_timer_group_reg_t timer_group[1];
volatile ledc_int_raw_reg_t int_raw;
volatile ledc_int_st_reg_t int_st;
volatile ledc_int_ena_reg_t int_ena;
volatile ledc_int_clr_reg_t int_clr;
uint32_t reserved_0d0[12];
volatile ledc_chn_gamma_wr_reg_t ch0_gamma_wr;
volatile ledc_chn_gamma_wr_addr_reg_t ch0_gamma_wr_addr;
volatile ledc_chn_gamma_rd_addr_reg_t ch0_gamma_rd_addr;
volatile ledc_chn_gamma_rd_data_reg_t ch0_gamma_rd_data;
volatile ledc_chn_gamma_wr_reg_t ch1_gamma_wr;
volatile ledc_chn_gamma_wr_addr_reg_t ch1_gamma_wr_addr;
volatile ledc_chn_gamma_rd_addr_reg_t ch1_gamma_rd_addr;
volatile ledc_chn_gamma_rd_data_reg_t ch1_gamma_rd_data;
volatile ledc_chn_gamma_wr_reg_t ch2_gamma_wr;
volatile ledc_chn_gamma_wr_addr_reg_t ch2_gamma_wr_addr;
volatile ledc_chn_gamma_rd_addr_reg_t ch2_gamma_rd_addr;
volatile ledc_chn_gamma_rd_data_reg_t ch2_gamma_rd_data;
volatile ledc_chn_gamma_wr_reg_t ch3_gamma_wr;
volatile ledc_chn_gamma_wr_addr_reg_t ch3_gamma_wr_addr;
volatile ledc_chn_gamma_rd_addr_reg_t ch3_gamma_rd_addr;
volatile ledc_chn_gamma_rd_data_reg_t ch3_gamma_rd_data;
volatile ledc_chn_gamma_wr_reg_t ch4_gamma_wr;
volatile ledc_chn_gamma_wr_addr_reg_t ch4_gamma_wr_addr;
volatile ledc_chn_gamma_rd_addr_reg_t ch4_gamma_rd_addr;
volatile ledc_chn_gamma_rd_data_reg_t ch4_gamma_rd_data;
volatile ledc_chn_gamma_wr_reg_t ch5_gamma_wr;
volatile ledc_chn_gamma_wr_addr_reg_t ch5_gamma_wr_addr;
volatile ledc_chn_gamma_rd_addr_reg_t ch5_gamma_rd_addr;
volatile ledc_chn_gamma_rd_data_reg_t ch5_gamma_rd_data;
volatile ledc_ch_gamma_group_reg_t channel_gamma_group[1];
uint32_t reserved_160[8];
volatile ledc_chn_gamma_conf_reg_t chn_gamma_conf[6];
volatile ledc_ch_gamma_conf_group_reg_t channel_gamma_conf_group[1];
uint32_t reserved_198[2];
volatile ledc_evt_task_en0_reg_t evt_task_en0;
volatile ledc_evt_task_en1_reg_t evt_task_en1;
volatile ledc_evt_task_en2_reg_t evt_task_en2;
uint32_t reserved_1ac;
volatile ledc_timern_cmp_reg_t timern_cmp[4];
volatile ledc_timern_cnt_cap_reg_t timern_cnt_cap[4];
volatile ledc_timer_cmp_group_reg_t timer_cmp_group[1];
volatile ledc_timer_cnt_cap_group_reg_t timer_cnt_cap_group[1];
uint32_t reserved_1d0[8];
volatile ledc_conf_reg_t conf;
uint32_t reserved_1f4[2];
components/soc/esp32h21/register/soc/pcr_reg.h
+2 -2
View File
@@ -493,8 +493,8 @@ extern "C" {
*/
#define PCR_LEDC_SCLK_CONF_REG (DR_REG_PCR_BASE + 0x40)
/** PCR_LEDC_SCLK_SEL : R/W; bitpos: [21:20]; default: 0;
* set this field to select clock-source. 0(default): do not select anyone clock, 1:
* 80MHz, 2: FOSC, 3: XTAL.
* set this field to select clock-source. 0(default): XTAL, 1:
* FOSC, 2: 96MHz.
*/
#define PCR_LEDC_SCLK_SEL 0x00000003U
#define PCR_LEDC_SCLK_SEL_M (PCR_LEDC_SCLK_SEL_V << PCR_LEDC_SCLK_SEL_S)
components/soc/esp32h21/register/soc/pcr_struct.h
+2 -2
View File
@@ -358,8 +358,8 @@ typedef union {
struct {
uint32_t reserved_0:20;
/** ledc_sclk_sel : R/W; bitpos: [21:20]; default: 0;
* set this field to select clock-source. 0(default): do not select anyone clock, 1:
* 80MHz, 2: FOSC, 3: XTAL.
* set this field to select clock-source. 0(default): XTAL, 1:
* FOSC, 2: 96MHz.
*/
uint32_t ledc_sclk_sel:2;
/** ledc_sclk_en : R/W; bitpos: [22]; default: 1;
components/soc/esp32h4/include/soc/Kconfig.soc_caps.in
+33 -1
View File
@@ -63,6 +63,10 @@ config SOC_GPSPI_SUPPORTED
bool
default y
config SOC_LEDC_SUPPORTED
bool
default y
config SOC_I2C_SUPPORTED
bool
default y
@@ -503,9 +507,37 @@ config SOC_I2S_SUPPORT_SLEEP_RETENTION
bool
default y
config SOC_LEDC_SUPPORT_PLL_DIV_CLOCK
bool
default y
config SOC_LEDC_SUPPORT_XTAL_CLOCK
bool
default y
config SOC_LEDC_TIMER_NUM
int
default 4
config SOC_LEDC_CHANNEL_NUM
int
default 6
default 8
config SOC_LEDC_TIMER_BIT_WIDTH
int
default 20
config SOC_LEDC_SUPPORT_FADE_STOP
bool
default y
config SOC_LEDC_FADE_PARAMS_BIT_WIDTH
int
default 10
config SOC_LEDC_SUPPORT_SLEEP_RETENTION
bool
default y
config SOC_MMU_PAGE_SIZE_CONFIGURABLE
bool
components/soc/esp32h4/include/soc/clk_tree_defs.h
+17
View File
@@ -338,6 +338,23 @@ typedef enum {
I2C_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the default clock choice */
} soc_periph_i2c_clk_src_t;
//////////////////////////////////////////////////LEDC/////////////////////////////////////////////////////////////////
/**
* @brief Array initializer for all supported clock sources of LEDC
*/
#define SOC_LEDC_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_PLL_F96M, SOC_MOD_CLK_RC_FAST}
/**
* @brief Type of LEDC clock source, reserved for the legacy LEDC driver
*/
typedef enum {
LEDC_AUTO_CLK = 0, /*!< LEDC source clock will be automatically selected based on the giving resolution and duty parameter when init the timer*/
LEDC_USE_PLL_DIV_CLK = SOC_MOD_CLK_PLL_F96M, /*!< Select PLL_F96M clock as the source clock */
LEDC_USE_RC_FAST_CLK = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */
LEDC_USE_XTAL_CLK = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
} soc_periph_ledc_clk_src_legacy_t;
///////////////////////////////////////////////////// I2S //////////////////////////////////////////////////////////////
/**
components/soc/esp32h4/include/soc/soc_caps.h
+12 -14
View File
@@ -58,7 +58,7 @@
#define SOC_RMT_SUPPORTED 1
#define SOC_SDM_SUPPORTED 1
#define SOC_GPSPI_SUPPORTED 1
// #define SOC_LEDC_SUPPORTED 1 // TODO: [ESP32H4] IDF-12343
#define SOC_LEDC_SUPPORTED 1
#define SOC_I2C_SUPPORTED 1
#define SOC_SYSTIMER_SUPPORTED 1 // TODO: [ESP32H4] IDF-12375 IDF-12377
// #define SOC_SUPPORT_COEXISTENCE 1 // TODO: [ESP32H4] IDF-12251 IDF-12252 IDF-12253
@@ -240,12 +240,10 @@
#define SOC_RTCIO_WAKE_SUPPORTED 1
#define SOC_RTCIO_EDGE_WAKE_SUPPORTED 1
/*-------------------------- Dedicated GPIO CAPS -----------------------------*/
// #define SOC_DEDIC_GPIO_OUT_CHANNELS_NUM (8) /*!< 8 outward channels on each CPU core */
// #define SOC_DEDIC_GPIO_IN_CHANNELS_NUM (8) /*!< 8 inward channels on each CPU core */
// #define SOC_DEDIC_PERIPH_ALWAYS_ENABLE (1) /*!< The dedicated GPIO (a.k.a. fast GPIO) is featured by some customized CPU instructions, which is always enabled */
/*-------------------------- Sigma Delta Modulator CAPS -----------------*/
#define SOC_SDM_SUPPORT_SLEEP_RETENTION 1
/*-------------------------- ETM CAPS -----------------------------------*/
#define SOC_ETM_SUPPORT_SLEEP_RETENTION 1
/*-------------------------- I2C CAPS ----------------------------------------*/
@@ -291,14 +289,14 @@
#define SOC_I2S_SUPPORT_SLEEP_RETENTION 1 /*!< The sleep retention feature can help back up I2S registers before sleep */
/*-------------------------- LEDC CAPS ---------------------------------------*/
// #define SOC_LEDC_SUPPORT_PLL_DIV_CLOCK (1)
// #define SOC_LEDC_SUPPORT_XTAL_CLOCK (1)
#define SOC_LEDC_CHANNEL_NUM (6) // TODO: [ESP32H4] IDF-12343
// #define SOC_LEDC_TIMER_BIT_WIDTH (20)
// #define SOC_LEDC_SUPPORT_FADE_STOP (1)
// #define SOC_LEDC_GAMMA_CURVE_FADE_SUPPORTED (1)
// #define SOC_LEDC_GAMMA_CURVE_FADE_RANGE_MAX (16)
// #define SOC_LEDC_FADE_PARAMS_BIT_WIDTH (10)
#define SOC_LEDC_SUPPORT_PLL_DIV_CLOCK (1)
#define SOC_LEDC_SUPPORT_XTAL_CLOCK (1)
#define SOC_LEDC_TIMER_NUM (4)
#define SOC_LEDC_CHANNEL_NUM (8)
#define SOC_LEDC_TIMER_BIT_WIDTH (20)
#define SOC_LEDC_SUPPORT_FADE_STOP (1)
#define SOC_LEDC_FADE_PARAMS_BIT_WIDTH (10)
#define SOC_LEDC_SUPPORT_SLEEP_RETENTION (1)
/*-------------------------- MMU CAPS ----------------------------------------*/
#define SOC_MMU_PAGE_SIZE_CONFIGURABLE (1)
components/soc/esp32h4/ledc_periph.c
+181
View File
@@ -0,0 +1,181 @@
/*
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/ledc_periph.h"
#include "soc/gpio_sig_map.h"
/*
Bunch of constants for every LEDC peripheral: GPIO signals
*/
const ledc_signal_conn_t ledc_periph_signal[1] = {
{
.sig_out0_idx = LEDC_LS_SIG_OUT0_IDX,
}
};
/**
* LEDC registers to be saved for sleep retention
*
* channel:
* LEDC_CHx_CONF0_REG, LEDC_CHx_HPOINT_REG, LEDC_CHx_DUTY_R_REG -> LEDC_CHx_DUTY_REG,
* LEDC_CHx_FADE_CONF_REG, LEDC_CHx_FADE_PARAM_REG
*
* timer:
* LEDC_TIMERn_CONF_REG, LEDC_TIMERn_CMP_REG,
*
* common:
* LEDC_INT_ENA_REG,
* LEDC_EVT_TASK_EN0_REG, LEDC_EVT_TASK_EN1_REG, LEDC_EVT_TASK_EN2_REG,
* LEDC_CONF_REG,
* LEDC_CH_POWER_UP_CONF_REG, LEDC_TIMER_POWER_UP_CONF_REG
*
* Note 1: Fade parameter registers are backuped and restored. But we won't start a fade automatically after wake-up.
* Instead, we will only start a PWM with a fixed duty cycle, the same value as before entering the sleep.
*
* Note 2: For timer/channel registers to get synced, update bits need to be set
*
* Note 3: Retention backup/restore does not rely on LEDC function clock enabled
*/
#define LEDC_COMMON_RETENTION_REGS_CNT 7
#define LEDC_COMMON_RETENTION_REGS_BASE (DR_REG_LEDC_BASE + 0xc8)
static const uint32_t ledc_common_regs_map[4] = {0x1c00001, 0x1c00, 0x0, 0x0};
static const regdma_entries_config_t ledc_common_regdma_entries[] = {
// If a fade is in process, the DUTY_CHNG_END_CHx intr bit is enabled, however, we don't want it to be restored after wake-up (no fade after wake-up).
// Therefore, we can set it to 0 before backup the LEDC_INT_ENA_REG.
[0] = {
.config = REGDMA_LINK_WRITE_INIT(REGDMA_LEDC_LINK(0x00),
LEDC_INT_ENA_REG, 0,
(LEDC_DUTY_CHNG_END_CH0_INT_ENA_M | LEDC_DUTY_CHNG_END_CH1_INT_ENA_M | LEDC_DUTY_CHNG_END_CH2_INT_ENA_M | LEDC_DUTY_CHNG_END_CH3_INT_ENA_M | LEDC_DUTY_CHNG_END_CH4_INT_ENA_M | LEDC_DUTY_CHNG_END_CH5_INT_ENA_M | LEDC_DUTY_CHNG_END_CH6_INT_ENA_M | LEDC_DUTY_CHNG_END_CH7_INT_ENA_M), 0, 1),
.owner = LEDC_RETENTION_ENTRY
},
[1] = {
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_LEDC_LINK(0x01),
LEDC_COMMON_RETENTION_REGS_BASE, LEDC_COMMON_RETENTION_REGS_BASE,
LEDC_COMMON_RETENTION_REGS_CNT, 0, 0,
ledc_common_regs_map[0], ledc_common_regs_map[1],
ledc_common_regs_map[2], ledc_common_regs_map[3]),
.owner = LEDC_RETENTION_ENTRY
},
};
#define LEDC_TIMER_RETENTION_ENTRIES(timer) { \
[0] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_LEDC_LINK(0x00), \
LEDC_TIMER##timer##_CONF_REG, LEDC_TIMER##timer##_CONF_REG, \
1, 0, 0), \
.owner = LEDC_RETENTION_ENTRY }, \
[1] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_LEDC_LINK(0x01), \
LEDC_TIMER##timer##_CMP_REG, LEDC_TIMER##timer##_CMP_REG, \
1, 0, 0), \
.owner = LEDC_RETENTION_ENTRY }, \
[2] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_LEDC_LINK(0x02), \
LEDC_TIMER##timer##_CONF_REG, LEDC_TIMER##timer##_PARA_UP, \
LEDC_TIMER##timer##_PARA_UP_M, 1, 0), \
.owner = LEDC_RETENTION_ENTRY }, \
}
#define LEDC_CHANNEL_RETENTION_REGS_CNT 2
static const uint32_t ledc_channel_regs_map[4] = {0x3, 0x0, 0x0, 0x0};
static const uint32_t ledc_channel_gamma_regs_map[4] = {0x1, 0x0, 0x0, 0x0};
#define LEDC_CHANNEL_RETENTION_ENTRIES(chan) { \
[0] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_LEDC_LINK(0x00), \
LEDC_CH##chan##_CONF0_REG, LEDC_CH##chan##_CONF0_REG, \
LEDC_CHANNEL_RETENTION_REGS_CNT, 0, 0, \
ledc_channel_regs_map[0], ledc_channel_regs_map[1], \
ledc_channel_regs_map[2], ledc_channel_regs_map[3]), \
.owner = LEDC_RETENTION_ENTRY }, \
[1] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_LEDC_LINK(0x01), \
LEDC_CH##chan##_DUTY_R_REG, LEDC_CH##chan##_DUTY_REG, \
1, 0, 0), \
.owner = LEDC_RETENTION_ENTRY }, \
[2] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_LEDC_LINK(0x02), \
LEDC_CH##chan##_CONF1_REG, LEDC_DUTY_START_CH##chan, \
LEDC_DUTY_START_CH##chan##_M, 1, 0), \
.owner = LEDC_RETENTION_ENTRY }, \
[3] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_LEDC_LINK(0x03), \
LEDC_CH##chan##_CONF0_REG, LEDC_PARA_UP_CH##chan, \
LEDC_PARA_UP_CH##chan##_M, 1, 0), \
.owner = LEDC_RETENTION_ENTRY }, \
[4] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_LEDC_LINK(0x04), \
LEDC_CH##chan##_FADE_CONF_REG, LEDC_CH##chan##_FADE_CONF_REG, \
1, 0, 0), \
.owner = LEDC_RETENTION_ENTRY }, \
[5] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_LEDC_LINK(0x05), \
LEDC_CH##chan##_FADE_PARAM_REG, LEDC_CH##chan##_FADE_PARAM_REG, \
1, 0, 0, \
ledc_channel_gamma_regs_map[0], ledc_channel_gamma_regs_map[1], \
ledc_channel_gamma_regs_map[2], ledc_channel_gamma_regs_map[3]), \
.owner = LEDC_RETENTION_ENTRY }, \
}
static const regdma_entries_config_t ledc_timer0_regdma_entries[] = LEDC_TIMER_RETENTION_ENTRIES(0);
static const regdma_entries_config_t ledc_timer1_regdma_entries[] = LEDC_TIMER_RETENTION_ENTRIES(1);
static const regdma_entries_config_t ledc_timer2_regdma_entries[] = LEDC_TIMER_RETENTION_ENTRIES(2);
static const regdma_entries_config_t ledc_timer3_regdma_entries[] = LEDC_TIMER_RETENTION_ENTRIES(3);
static const regdma_entries_config_t ledc_channel0_regdma_entries[] = LEDC_CHANNEL_RETENTION_ENTRIES(0);
static const regdma_entries_config_t ledc_channel1_regdma_entries[] = LEDC_CHANNEL_RETENTION_ENTRIES(1);
static const regdma_entries_config_t ledc_channel2_regdma_entries[] = LEDC_CHANNEL_RETENTION_ENTRIES(2);
static const regdma_entries_config_t ledc_channel3_regdma_entries[] = LEDC_CHANNEL_RETENTION_ENTRIES(3);
static const regdma_entries_config_t ledc_channel4_regdma_entries[] = LEDC_CHANNEL_RETENTION_ENTRIES(4);
static const regdma_entries_config_t ledc_channel5_regdma_entries[] = LEDC_CHANNEL_RETENTION_ENTRIES(5);
static const regdma_entries_config_t ledc_channel6_regdma_entries[] = LEDC_CHANNEL_RETENTION_ENTRIES(6);
static const regdma_entries_config_t ledc_channel7_regdma_entries[] = LEDC_CHANNEL_RETENTION_ENTRIES(7);
const ledc_reg_retention_info_t ledc_reg_retention_info = {
.common = {
.regdma_entry_array = ledc_common_regdma_entries,
.array_size = ARRAY_SIZE(ledc_common_regdma_entries),
},
.timer[0] = {
.regdma_entry_array = ledc_timer0_regdma_entries,
.array_size = ARRAY_SIZE(ledc_timer0_regdma_entries),
},
.timer[1] = {
.regdma_entry_array = ledc_timer1_regdma_entries,
.array_size = ARRAY_SIZE(ledc_timer1_regdma_entries),
},
.timer[2] = {
.regdma_entry_array = ledc_timer2_regdma_entries,
.array_size = ARRAY_SIZE(ledc_timer2_regdma_entries),
},
.timer[3] = {
.regdma_entry_array = ledc_timer3_regdma_entries,
.array_size = ARRAY_SIZE(ledc_timer3_regdma_entries),
},
.channel[0] = {
.regdma_entry_array = ledc_channel0_regdma_entries,
.array_size = ARRAY_SIZE(ledc_channel0_regdma_entries),
},
.channel[1] = {
.regdma_entry_array = ledc_channel1_regdma_entries,
.array_size = ARRAY_SIZE(ledc_channel1_regdma_entries),
},
.channel[2] = {
.regdma_entry_array = ledc_channel2_regdma_entries,
.array_size = ARRAY_SIZE(ledc_channel2_regdma_entries),
},
.channel[3] = {
.regdma_entry_array = ledc_channel3_regdma_entries,
.array_size = ARRAY_SIZE(ledc_channel3_regdma_entries),
},
.channel[4] = {
.regdma_entry_array = ledc_channel4_regdma_entries,
.array_size = ARRAY_SIZE(ledc_channel4_regdma_entries),
},
.channel[5] = {
.regdma_entry_array = ledc_channel5_regdma_entries,
.array_size = ARRAY_SIZE(ledc_channel5_regdma_entries),
},
.channel[6] = {
.regdma_entry_array = ledc_channel6_regdma_entries,
.array_size = ARRAY_SIZE(ledc_channel6_regdma_entries),
},
.channel[7] = {
.regdma_entry_array = ledc_channel7_regdma_entries,
.array_size = ARRAY_SIZE(ledc_channel7_regdma_entries),
},
.module_id = SLEEP_RETENTION_MODULE_LEDC,
};
components/soc/esp32h4/register/soc/ledc_reg.h
+186
View File
@@ -3194,6 +3194,192 @@ extern "C" {
#define LEDC_LEDC_DATE_V 0x0FFFFFFFU
#define LEDC_LEDC_DATE_S 0
/** LEDC fade parameter config registers
* 1 words (32bit) per channel * 8 channels
*/
#define LEDC_CH0_FADE_PARAM_REG (DR_REG_LEDC_BASE + 0x400)
/* LEDC_CH0_FADE_PARAM_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */
#define LEDC_CH0_FADE_PARAM_DUTY_NUM 0x000003FF
#define LEDC_CH0_FADE_PARAM_DUTY_NUM_M ((LEDC_CH0_FADE_PARAM_DUTY_NUM_V)<<(LEDC_CH0_FADE_PARAM_DUTY_NUM_S))
#define LEDC_CH0_FADE_PARAM_DUTY_NUM_V 0x3FF
#define LEDC_CH0_FADE_PARAM_DUTY_NUM_S 21
/* LEDC_CH0_FADE_PARAM_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */
#define LEDC_CH0_FADE_PARAM_SCALE 0x000003FF
#define LEDC_CH0_FADE_PARAM_SCALE_M ((LEDC_CH0_FADE_PARAM_SCALE_V)<<(LEDC_CH0_FADE_PARAM_SCALE_S))
#define LEDC_CH0_FADE_PARAM_SCALE_V 0x3FF
#define LEDC_CH0_FADE_PARAM_SCALE_S 11
/* LEDC_CH0_FADE_PARAM_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */
#define LEDC_CH0_FADE_PARAM_DUTY_CYCLE 0x000003FF
#define LEDC_CH0_FADE_PARAM_DUTY_CYCLE_M ((LEDC_CH0_FADE_PARAM_DUTY_CYCLE_V)<<(LEDC_CH0_FADE_PARAM_DUTY_CYCLE_S))
#define LEDC_CH0_FADE_PARAM_DUTY_CYCLE_V 0x3FF
#define LEDC_CH0_FADE_PARAM_DUTY_CYCLE_S 1
/* LEDC_CH0_FADE_PARAM_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */
#define LEDC_CH0_FADE_PARAM_DUTY_INC (BIT(0))
#define LEDC_CH0_FADE_PARAM_DUTY_INC_M (BIT(0))
#define LEDC_CH0_FADE_PARAM_DUTY_INC_V 0x1
#define LEDC_CH0_FADE_PARAM_DUTY_INC_S 0
#define LEDC_CH1_FADE_PARAM_REG (DR_REG_LEDC_BASE + 0x440)
/* LEDC_CH1_FADE_PARAM_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */
#define LEDC_CH1_FADE_PARAM_DUTY_NUM 0x000003FF
#define LEDC_CH1_FADE_PARAM_DUTY_NUM_M ((LEDC_CH1_FADE_PARAM_DUTY_NUM_V)<<(LEDC_CH1_FADE_PARAM_DUTY_NUM_S))
#define LEDC_CH1_FADE_PARAM_DUTY_NUM_V 0x3FF
#define LEDC_CH1_FADE_PARAM_DUTY_NUM_S 21
/* LEDC_CH1_FADE_PARAM_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */
#define LEDC_CH1_FADE_PARAM_SCALE 0x000003FF
#define LEDC_CH1_FADE_PARAM_SCALE_M ((LEDC_CH1_FADE_PARAM_SCALE_V)<<(LEDC_CH1_FADE_PARAM_SCALE_S))
#define LEDC_CH1_FADE_PARAM_SCALE_V 0x3FF
#define LEDC_CH1_FADE_PARAM_SCALE_S 11
/* LEDC_CH1_FADE_PARAM_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */
#define LEDC_CH1_FADE_PARAM_DUTY_CYCLE 0x000003FF
#define LEDC_CH1_FADE_PARAM_DUTY_CYCLE_M ((LEDC_CH1_FADE_PARAM_DUTY_CYCLE_V)<<(LEDC_CH1_FADE_PARAM_DUTY_CYCLE_S))
#define LEDC_CH1_FADE_PARAM_DUTY_CYCLE_V 0x3FF
#define LEDC_CH1_FADE_PARAM_DUTY_CYCLE_S 1
/* LEDC_CH1_FADE_PARAM_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */
#define LEDC_CH1_FADE_PARAM_DUTY_INC (BIT(0))
#define LEDC_CH1_FADE_PARAM_DUTY_INC_M (BIT(0))
#define LEDC_CH1_FADE_PARAM_DUTY_INC_V 0x1
#define LEDC_CH1_FADE_PARAM_DUTY_INC_S 0
#define LEDC_CH2_FADE_PARAM_REG (DR_REG_LEDC_BASE + 0x480)
/* LEDC_CH2_FADE_PARAM_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */
#define LEDC_CH2_FADE_PARAM_DUTY_NUM 0x000003FF
#define LEDC_CH2_FADE_PARAM_DUTY_NUM_M ((LEDC_CH2_FADE_PARAM_DUTY_NUM_V)<<(LEDC_CH2_FADE_PARAM_DUTY_NUM_S))
#define LEDC_CH2_FADE_PARAM_DUTY_NUM_V 0x3FF
#define LEDC_CH2_FADE_PARAM_DUTY_NUM_S 21
/* LEDC_CH2_FADE_PARAM_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */
#define LEDC_CH2_FADE_PARAM_SCALE 0x000003FF
#define LEDC_CH2_FADE_PARAM_SCALE_M ((LEDC_CH2_FADE_PARAM_SCALE_V)<<(LEDC_CH2_FADE_PARAM_SCALE_S))
#define LEDC_CH2_FADE_PARAM_SCALE_V 0x3FF
#define LEDC_CH2_FADE_PARAM_SCALE_S 11
/* LEDC_CH2_FADE_PARAM_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */
#define LEDC_CH2_FADE_PARAM_DUTY_CYCLE 0x000003FF
#define LEDC_CH2_FADE_PARAM_DUTY_CYCLE_M ((LEDC_CH2_FADE_PARAM_DUTY_CYCLE_V)<<(LEDC_CH2_FADE_PARAM_DUTY_CYCLE_S))
#define LEDC_CH2_FADE_PARAM_DUTY_CYCLE_V 0x3FF
#define LEDC_CH2_FADE_PARAM_DUTY_CYCLE_S 1
/* LEDC_CH2_FADE_PARAM_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */
#define LEDC_CH2_FADE_PARAM_DUTY_INC (BIT(0))
#define LEDC_CH2_FADE_PARAM_DUTY_INC_M (BIT(0))
#define LEDC_CH2_FADE_PARAM_DUTY_INC_V 0x1
#define LEDC_CH2_FADE_PARAM_DUTY_INC_S 0
#define LEDC_CH3_FADE_PARAM_REG (DR_REG_LEDC_BASE + 0x4c0)
/* LEDC_CH3_FADE_PARAM_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */
#define LEDC_CH3_FADE_PARAM_DUTY_NUM 0x000003FF
#define LEDC_CH3_FADE_PARAM_DUTY_NUM_M ((LEDC_CH3_FADE_PARAM_DUTY_NUM_V)<<(LEDC_CH3_FADE_PARAM_DUTY_NUM_S))
#define LEDC_CH3_FADE_PARAM_DUTY_NUM_V 0x3FF
#define LEDC_CH3_FADE_PARAM_DUTY_NUM_S 21
/* LEDC_CH3_FADE_PARAM_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */
#define LEDC_CH3_FADE_PARAM_SCALE 0x000003FF
#define LEDC_CH3_FADE_PARAM_SCALE_M ((LEDC_CH3_FADE_PARAM_SCALE_V)<<(LEDC_CH3_FADE_PARAM_SCALE_S))
#define LEDC_CH3_FADE_PARAM_SCALE_V 0x3FF
#define LEDC_CH3_FADE_PARAM_SCALE_S 11
/* LEDC_CH3_FADE_PARAM_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */
#define LEDC_CH3_FADE_PARAM_DUTY_CYCLE 0x000003FF
#define LEDC_CH3_FADE_PARAM_DUTY_CYCLE_M ((LEDC_CH3_FADE_PARAM_DUTY_CYCLE_V)<<(LEDC_CH3_FADE_PARAM_DUTY_CYCLE_S))
#define LEDC_CH3_FADE_PARAM_DUTY_CYCLE_V 0x3FF
#define LEDC_CH3_FADE_PARAM_DUTY_CYCLE_S 1
/* LEDC_CH3_FADE_PARAM_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */
#define LEDC_CH3_FADE_PARAM_DUTY_INC (BIT(0))
#define LEDC_CH3_FADE_PARAM_DUTY_INC_M (BIT(0))
#define LEDC_CH3_FADE_PARAM_DUTY_INC_V 0x1
#define LEDC_CH3_FADE_PARAM_DUTY_INC_S 0
#define LEDC_CH4_FADE_PARAM_REG (DR_REG_LEDC_BASE + 0x500)
/* LEDC_CH4_FADE_PARAM_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */
#define LEDC_CH4_FADE_PARAM_DUTY_NUM 0x000003FF
#define LEDC_CH4_FADE_PARAM_DUTY_NUM_M ((LEDC_CH4_FADE_PARAM_DUTY_NUM_V)<<(LEDC_CH4_FADE_PARAM_DUTY_NUM_S))
#define LEDC_CH4_FADE_PARAM_DUTY_NUM_V 0x3FF
#define LEDC_CH4_FADE_PARAM_DUTY_NUM_S 21
/* LEDC_CH4_FADE_PARAM_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */
#define LEDC_CH4_FADE_PARAM_SCALE 0x000003FF
#define LEDC_CH4_FADE_PARAM_SCALE_M ((LEDC_CH4_FADE_PARAM_SCALE_V)<<(LEDC_CH4_FADE_PARAM_SCALE_S))
#define LEDC_CH4_FADE_PARAM_SCALE_V 0x3FF
#define LEDC_CH4_FADE_PARAM_SCALE_S 11
/* LEDC_CH4_FADE_PARAM_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */
#define LEDC_CH4_FADE_PARAM_DUTY_CYCLE 0x000003FF
#define LEDC_CH4_FADE_PARAM_DUTY_CYCLE_M ((LEDC_CH4_FADE_PARAM_DUTY_CYCLE_V)<<(LEDC_CH4_FADE_PARAM_DUTY_CYCLE_S))
#define LEDC_CH4_FADE_PARAM_DUTY_CYCLE_V 0x3FF
#define LEDC_CH4_FADE_PARAM_DUTY_CYCLE_S 1
/* LEDC_CH4_FADE_PARAM_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */
#define LEDC_CH4_FADE_PARAM_DUTY_INC (BIT(0))
#define LEDC_CH4_FADE_PARAM_DUTY_INC_M (BIT(0))
#define LEDC_CH4_FADE_PARAM_DUTY_INC_V 0x1
#define LEDC_CH4_FADE_PARAM_DUTY_INC_S 0
#define LEDC_CH5_FADE_PARAM_REG (DR_REG_LEDC_BASE + 0x540)
/* LEDC_CH5_FADE_PARAM_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */
#define LEDC_CH5_FADE_PARAM_DUTY_NUM 0x000003FF
#define LEDC_CH5_FADE_PARAM_DUTY_NUM_M ((LEDC_CH5_FADE_PARAM_DUTY_NUM_V)<<(LEDC_CH5_FADE_PARAM_DUTY_NUM_S))
#define LEDC_CH5_FADE_PARAM_DUTY_NUM_V 0x3FF
#define LEDC_CH5_FADE_PARAM_DUTY_NUM_S 21
/* LEDC_CH5_FADE_PARAM_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */
#define LEDC_CH5_FADE_PARAM_SCALE 0x000003FF
#define LEDC_CH5_FADE_PARAM_SCALE_M ((LEDC_CH5_FADE_PARAM_SCALE_V)<<(LEDC_CH5_FADE_PARAM_SCALE_S))
#define LEDC_CH5_FADE_PARAM_SCALE_V 0x3FF
#define LEDC_CH5_FADE_PARAM_SCALE_S 11
/* LEDC_CH5_FADE_PARAM_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */
#define LEDC_CH5_FADE_PARAM_DUTY_CYCLE 0x000003FF
#define LEDC_CH5_FADE_PARAM_DUTY_CYCLE_M ((LEDC_CH5_FADE_PARAM_DUTY_CYCLE_V)<<(LEDC_CH5_FADE_PARAM_DUTY_CYCLE_S))
#define LEDC_CH5_FADE_PARAM_DUTY_CYCLE_V 0x3FF
#define LEDC_CH5_FADE_PARAM_DUTY_CYCLE_S 1
/* LEDC_CH5_FADE_PARAM_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */
#define LEDC_CH5_FADE_PARAM_DUTY_INC (BIT(0))
#define LEDC_CH5_FADE_PARAM_DUTY_INC_M (BIT(0))
#define LEDC_CH5_FADE_PARAM_DUTY_INC_V 0x1
#define LEDC_CH5_FADE_PARAM_DUTY_INC_S 0
#define LEDC_CH6_FADE_PARAM_REG (DR_REG_LEDC_BASE + 0x580)
/* LEDC_CH6_FADE_PARAM_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */
#define LEDC_CH6_FADE_PARAM_DUTY_NUM 0x000003FF
#define LEDC_CH6_FADE_PARAM_DUTY_NUM_M ((LEDC_CH6_FADE_PARAM_DUTY_NUM_V)<<(LEDC_CH6_FADE_PARAM_DUTY_NUM_S))
#define LEDC_CH6_FADE_PARAM_DUTY_NUM_V 0x3FF
#define LEDC_CH6_FADE_PARAM_DUTY_NUM_S 21
/* LEDC_CH6_FADE_PARAM_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */
#define LEDC_CH6_FADE_PARAM_SCALE 0x000003FF
#define LEDC_CH6_FADE_PARAM_SCALE_M ((LEDC_CH6_FADE_PARAM_SCALE_V)<<(LEDC_CH6_FADE_PARAM_SCALE_S))
#define LEDC_CH6_FADE_PARAM_SCALE_V 0x3FF
#define LEDC_CH6_FADE_PARAM_SCALE_S 11
/* LEDC_CH6_FADE_PARAM_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */
#define LEDC_CH6_FADE_PARAM_DUTY_CYCLE 0x000003FF
#define LEDC_CH6_FADE_PARAM_DUTY_CYCLE_M ((LEDC_CH6_FADE_PARAM_DUTY_CYCLE_V)<<(LEDC_CH6_FADE_PARAM_DUTY_CYCLE_S))
#define LEDC_CH6_FADE_PARAM_DUTY_CYCLE_V 0x3FF
#define LEDC_CH6_FADE_PARAM_DUTY_CYCLE_S 1
/* LEDC_CH6_FADE_PARAM_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */
#define LEDC_CH6_FADE_PARAM_DUTY_INC (BIT(0))
#define LEDC_CH6_FADE_PARAM_DUTY_INC_M (BIT(0))
#define LEDC_CH6_FADE_PARAM_DUTY_INC_V 0x1
#define LEDC_CH6_FADE_PARAM_DUTY_INC_S 0
#define LEDC_CH7_FADE_PARAM_REG (DR_REG_LEDC_BASE + 0x5c0)
/* LEDC_CH7_FADE_PARAM_DUTY_NUM : R/W ;bitpos:[30:21] ;default: 10'h0 ; */
#define LEDC_CH7_FADE_PARAM_DUTY_NUM 0x000003FF
#define LEDC_CH7_FADE_PARAM_DUTY_NUM_M ((LEDC_CH7_FADE_PARAM_DUTY_NUM_V)<<(LEDC_CH7_FADE_PARAM_DUTY_NUM_S))
#define LEDC_CH7_FADE_PARAM_DUTY_NUM_V 0x3FF
#define LEDC_CH7_FADE_PARAM_DUTY_NUM_S 21
/* LEDC_CH7_FADE_PARAM_SCALE : R/W ;bitpos:[20:11] ;default: 10'h0 ; */
#define LEDC_CH7_FADE_PARAM_SCALE 0x000003FF
#define LEDC_CH7_FADE_PARAM_SCALE_M ((LEDC_CH7_FADE_PARAM_SCALE_V)<<(LEDC_CH7_FADE_PARAM_SCALE_S))
#define LEDC_CH7_FADE_PARAM_SCALE_V 0x3FF
#define LEDC_CH7_FADE_PARAM_SCALE_S 11
/* LEDC_CH7_FADE_PARAM_DUTY_CYCLE : R/W ;bitpos:[10:1] ;default: 10'h0 ; */
#define LEDC_CH7_FADE_PARAM_DUTY_CYCLE 0x000003FF
#define LEDC_CH7_FADE_PARAM_DUTY_CYCLE_M ((LEDC_CH7_FADE_PARAM_DUTY_CYCLE_V)<<(LEDC_CH7_FADE_PARAM_DUTY_CYCLE_S))
#define LEDC_CH7_FADE_PARAM_DUTY_CYCLE_V 0x3FF
#define LEDC_CH7_FADE_PARAM_DUTY_CYCLE_S 1
/* LEDC_CH7_FADE_PARAM_DUTY_INC : R/W ;bitpos:[0] ;default: 1'h0 ; */
#define LEDC_CH7_FADE_PARAM_DUTY_INC (BIT(0))
#define LEDC_CH7_FADE_PARAM_DUTY_INC_M (BIT(0))
#define LEDC_CH7_FADE_PARAM_DUTY_INC_V 0x1
#define LEDC_CH7_FADE_PARAM_DUTY_INC_S 0
#ifdef __cplusplus
}
#endif
components/soc/esp32h4/register/soc/ledc_struct.h
+125 -113
View File
@@ -16,52 +16,52 @@ extern "C" {
*/
typedef union {
struct {
/** timer_sel_chn : R/W; bitpos: [1:0]; default: 0;
/** timer_sel : R/W; bitpos: [1:0]; default: 0;
* Configures which timer is channel n selected.
* 0: Select timer0
* 1: Select timer1
* 2: Select timer2
* 3: Select timer3
*/
uint32_t timer_sel_chn:2;
/** sig_out_en_chn : R/W; bitpos: [2]; default: 0;
uint32_t timer_sel:2;
/** sig_out_en : R/W; bitpos: [2]; default: 0;
* Configures whether or not to enable signal output on channel n.
* 0: Signal output disable
* 1: Signal output enable
*/
uint32_t sig_out_en_chn:1;
/** idle_lv_chn : R/W; bitpos: [3]; default: 0;
uint32_t sig_out_en:1;
/** idle_lv : R/W; bitpos: [3]; default: 0;
* Configures the output value when channel n is inactive. Valid only when
* LEDC_SIG_OUT_EN_CHn is 0.
* 0: Output level is low
* 1: Output level is high
*/
uint32_t idle_lv_chn:1;
/** para_up_chn : WT; bitpos: [4]; default: 0;
uint32_t idle_lv:1;
/** para_up : WT; bitpos: [4]; default: 0;
* Configures whether or not to update LEDC_HPOINT_CHn, LEDC_DUTY_START_CHn,
* LEDC_SIG_OUT_EN_CHn, LEDC_TIMER_SEL_CHn, LEDC_OVF_CNT_EN_CHn fields and duty cycle
* range configuration for channel n, and will be automatically cleared by hardware.
* 0: Invalid. No effect
* 1: Update
*/
uint32_t para_up_chn:1;
/** ovf_num_chn : R/W; bitpos: [14:5]; default: 0;
uint32_t para_up:1;
/** ovf_num : R/W; bitpos: [14:5]; default: 0;
* Configures the maximum times of overflow minus 1.The LEDC_OVF_CNT_CHn_INT interrupt
* will be triggered when channel n overflows for (LEDC_OVF_NUM_CHn + 1) times.
*/
uint32_t ovf_num_chn:10;
/** ovf_cnt_en_chn : R/W; bitpos: [15]; default: 0;
uint32_t ovf_num:10;
/** ovf_cnt_en : R/W; bitpos: [15]; default: 0;
* Configures whether or not to enable the ovf_cnt of channel n.
* 0: Disable
* 1: Enable
*/
uint32_t ovf_cnt_en_chn:1;
/** ovf_cnt_reset_chn : WT; bitpos: [16]; default: 0;
uint32_t ovf_cnt_en:1;
/** ovf_cnt_reset : WT; bitpos: [16]; default: 0;
* Configures whether or not to reset the ovf_cnt of channel n.
* 0: Invalid. No effect
* 1: Reset the ovf_cnt
*/
uint32_t ovf_cnt_reset_chn:1;
uint32_t ovf_cnt_reset:1;
uint32_t reserved_17:15;
};
uint32_t val;
@@ -72,11 +72,11 @@ typedef union {
*/
typedef union {
struct {
/** hpoint_chn : R/W; bitpos: [19:0]; default: 0;
/** hpoint : R/W; bitpos: [19:0]; default: 0;
* Configures high point of signal output on channel n. The output value changes to
* high when the selected timers has reached the value specified by this register.
*/
uint32_t hpoint_chn:20;
uint32_t hpoint:20;
uint32_t reserved_20:12;
};
uint32_t val;
@@ -87,10 +87,10 @@ typedef union {
*/
typedef union {
struct {
/** duty_chn : R/W; bitpos: [24:0]; default: 0;
/** duty : R/W; bitpos: [24:0]; default: 0;
* Configures the duty of signal output on channel n.
*/
uint32_t duty_chn:25;
uint32_t duty:25;
uint32_t reserved_25:7;
};
uint32_t val;
@@ -102,53 +102,53 @@ typedef union {
typedef union {
struct {
uint32_t reserved_0:31;
/** duty_start_chn : R/W/SC; bitpos: [31]; default: 0;
/** duty_start : R/W/SC; bitpos: [31]; default: 0;
* Configures whether the duty cycle fading configurations take effect.
* 0: Not take effect
* 1: Take effect
*/
uint32_t duty_start_chn:1;
uint32_t duty_start:1;
};
uint32_t val;
} ledc_chn_conf1_reg_t;
/** Type of timern_conf register
* Timer n configuration register
/** Type of timerx_conf register
* Timer x configuration register
*/
typedef union {
struct {
/** timern_duty_res : R/W; bitpos: [4:0]; default: 0;
* Configures the bit width of the counter in timer n. Valid values are 1 to 20.
/** duty_res : R/W; bitpos: [4:0]; default: 0;
* Configures the bit width of the counter in timer x. Valid values are 1 to 20.
*/
uint32_t timern_duty_res:5;
/** clk_div_timern : R/W; bitpos: [22:5]; default: 0;
* Configures the divisor for the divider in timer n.The least significant eight bits
uint32_t duty_res:5;
/** clk_div : R/W; bitpos: [22:5]; default: 0;
* Configures the divisor for the divider in timer x.The least significant eight bits
* represent the fractional part.
*/
uint32_t clk_div_timern:18;
/** timern_pause : R/W; bitpos: [23]; default: 0;
* Configures whether or not to pause the counter in timer n.
uint32_t clk_div:18;
/** pause : R/W; bitpos: [23]; default: 0;
* Configures whether or not to pause the counter in timer x.
* 0: Normal
* 1: Pause
*/
uint32_t timern_pause:1;
/** timern_rst : R/W; bitpos: [24]; default: 1;
* Configures whether or not to reset timer n. The counter will show 0 after reset.
uint32_t pause:1;
/** rst : R/W; bitpos: [24]; default: 1;
* Configures whether or not to reset timer x. The counter will show 0 after reset.
* 0: Not reset
* 1: Reset
*/
uint32_t timern_rst:1;
uint32_t rst:1;
uint32_t reserved_25:1;
/** timern_para_up : WT; bitpos: [26]; default: 0;
/** para_up : WT; bitpos: [26]; default: 0;
* Configures whether or not to update LEDC_CLK_DIV_TIMERn and LEDC_TIMERn_DUTY_RES.
* 0: Invalid. No effect
* 1: Update
*/
uint32_t timern_para_up:1;
uint32_t para_up:1;
uint32_t reserved_27:5;
};
uint32_t val;
} ledc_timern_conf_reg_t;
} ledc_timerx_conf_reg_t;
/** Type of chn_fade_conf register
* Ledc chn fade config register.
@@ -156,18 +156,18 @@ typedef union {
typedef union {
struct {
uint32_t reserved_0:5;
/** chn_fade_pause : WT; bitpos: [5]; default: 0;
/** fade_pause : WT; bitpos: [5]; default: 0;
* Configures whether or not to pause duty cycle fading of LEDC chn.
* 0: Invalid. No effect
* 1: Pause
*/
uint32_t chn_fade_pause:1;
/** chn_fade_resume : WT; bitpos: [6]; default: 0;
uint32_t fade_pause:1;
/** fade_resume : WT; bitpos: [6]; default: 0;
* Configures whether or nor to resume duty cycle fading of LEDC chn.
* 0: Invalid. No effect
* 1: Resume
*/
uint32_t chn_fade_resume:1;
uint32_t fade_resume:1;
uint32_t reserved_7:25;
};
uint32_t val;
@@ -733,19 +733,19 @@ typedef union {
uint32_t val;
} ledc_evt_task_en2_reg_t;
/** Type of timern_cmp register
* Ledc timern compare value register.
/** Type of timerx_cmp register
* Ledc timer x compare value register.
*/
typedef union {
struct {
/** timern_cmp : R/W; bitpos: [19:0]; default: 0;
* Configures the comparison value for LEDC timern.
/** cmp : R/W; bitpos: [19:0]; default: 0;
* Configures the comparison value for LEDC timer x.
*/
uint32_t timern_cmp:20;
uint32_t cmp:20;
uint32_t reserved_20:12;
};
uint32_t val;
} ledc_timern_cmp_reg_t;
} ledc_timerx_cmp_reg_t;
/** Type of conf register
* LEDC global configuration register
@@ -934,42 +934,42 @@ typedef union {
*/
typedef union {
struct {
/** duty_chn_r : RO; bitpos: [24:0]; default: 0;
/** duty_r : RO; bitpos: [24:0]; default: 0;
* Represents the current duty of output signal on channel n.
*/
uint32_t duty_chn_r:25;
uint32_t duty_r:25;
uint32_t reserved_25:7;
};
uint32_t val;
} ledc_chn_duty_r_reg_t;
/** Type of timern_value register
* Timer n current counter value register
/** Type of timerx_value register
* Timer x current counter value register
*/
typedef union {
struct {
/** timern_cnt : RO; bitpos: [19:0]; default: 0;
* Represents the current counter value of timer n.
/** cnt : RO; bitpos: [19:0]; default: 0;
* Represents the current counter value of timer x.
*/
uint32_t timern_cnt:20;
uint32_t cnt:20;
uint32_t reserved_20:12;
};
uint32_t val;
} ledc_timern_value_reg_t;
} ledc_timerx_value_reg_t;
/** Type of timern_cnt_cap register
* Ledc timern captured count value register.
/** Type of timerx_cnt_cap register
* Ledc timer x captured count value register.
*/
typedef union {
struct {
/** timern_cnt_cap : RO; bitpos: [19:0]; default: 0;
* Represents the captured LEDC timern count value.
/** cnt_cap : RO; bitpos: [19:0]; default: 0;
* Represents the captured LEDC timer x count value.
*/
uint32_t timern_cnt_cap:20;
uint32_t cnt_cap:20;
uint32_t reserved_20:12;
};
uint32_t val;
} ledc_timern_cnt_cap_reg_t;
} ledc_timerx_cnt_cap_reg_t;
/** Group: Interrupt Register */
@@ -1391,77 +1391,89 @@ typedef union {
typedef struct {
volatile ledc_chn_conf0_reg_t ch0_conf0;
volatile ledc_chn_hpoint_reg_t ch0_hpoint;
volatile ledc_chn_duty_reg_t ch0_duty;
volatile ledc_chn_conf1_reg_t ch0_conf1;
volatile ledc_chn_duty_r_reg_t ch0_duty_r;
volatile ledc_chn_conf0_reg_t ch1_conf0;
volatile ledc_chn_hpoint_reg_t ch1_hpoint;
volatile ledc_chn_duty_reg_t ch1_duty;
volatile ledc_chn_conf1_reg_t ch1_conf1;
volatile ledc_chn_duty_r_reg_t ch1_duty_r;
volatile ledc_chn_conf0_reg_t ch2_conf0;
volatile ledc_chn_hpoint_reg_t ch2_hpoint;
volatile ledc_chn_duty_reg_t ch2_duty;
volatile ledc_chn_conf1_reg_t ch2_conf1;
volatile ledc_chn_duty_r_reg_t ch2_duty_r;
volatile ledc_chn_conf0_reg_t ch3_conf0;
volatile ledc_chn_hpoint_reg_t ch3_hpoint;
volatile ledc_chn_duty_reg_t ch3_duty;
volatile ledc_chn_conf1_reg_t ch3_conf1;
volatile ledc_chn_duty_r_reg_t ch3_duty_r;
volatile ledc_chn_conf0_reg_t ch4_conf0;
volatile ledc_chn_hpoint_reg_t ch4_hpoint;
volatile ledc_chn_duty_reg_t ch4_duty;
volatile ledc_chn_conf1_reg_t ch4_conf1;
volatile ledc_chn_duty_r_reg_t ch4_duty_r;
volatile ledc_chn_conf0_reg_t ch5_conf0;
volatile ledc_chn_hpoint_reg_t ch5_hpoint;
volatile ledc_chn_duty_reg_t ch5_duty;
volatile ledc_chn_conf1_reg_t ch5_conf1;
volatile ledc_chn_duty_r_reg_t ch5_duty_r;
volatile ledc_chn_conf0_reg_t ch6_conf0;
volatile ledc_chn_hpoint_reg_t ch6_hpoint;
volatile ledc_chn_duty_reg_t ch6_duty;
volatile ledc_chn_conf1_reg_t ch6_conf1;
volatile ledc_chn_duty_r_reg_t ch6_duty_r;
volatile ledc_chn_conf0_reg_t ch7_conf0;
volatile ledc_chn_hpoint_reg_t ch7_hpoint;
volatile ledc_chn_duty_reg_t ch7_duty;
volatile ledc_chn_conf1_reg_t ch7_conf1;
volatile ledc_chn_duty_r_reg_t ch7_duty_r;
volatile ledc_timern_conf_reg_t timer0_conf;
volatile ledc_timern_value_reg_t timer0_value;
volatile ledc_timern_conf_reg_t timer1_conf;
volatile ledc_timern_value_reg_t timer1_value;
volatile ledc_timern_conf_reg_t timer2_conf;
volatile ledc_timern_value_reg_t timer2_value;
volatile ledc_timern_conf_reg_t timer3_conf;
volatile ledc_timern_value_reg_t timer3_value;
volatile ledc_chn_conf0_reg_t conf0;
volatile ledc_chn_hpoint_reg_t hpoint;
volatile ledc_chn_duty_reg_t duty_init;
volatile ledc_chn_conf1_reg_t conf1;
volatile ledc_chn_duty_r_reg_t duty_r;
} ledc_chn_reg_t;
typedef struct {
volatile ledc_chn_reg_t channel[8];
} ledc_ch_group_reg_t;
typedef struct {
volatile ledc_timerx_conf_reg_t conf;
volatile ledc_timerx_value_reg_t value;
} ledc_timerx_reg_t;
typedef struct {
volatile ledc_timerx_reg_t timer[4];
} ledc_timer_group_reg_t;
typedef struct {
volatile ledc_chn_fade_conf_reg_t fade_conf[8];
} ledc_ch_fade_conf_group_reg_t;
typedef struct {
volatile ledc_timerx_cmp_reg_t cmp[4];
} ledc_timer_cmp_group_reg_t;
typedef struct {
volatile ledc_timerx_cnt_cap_reg_t cnt_cap[4];
} ledc_timer_cnt_cap_group_reg_t;
/**
* Fade param register type
*/
typedef union {
struct {
uint32_t duty_inc :1;
uint32_t duty_cycle :10;
uint32_t scale :10;
uint32_t duty_num :10;
uint32_t reserved :1;
};
uint32_t val;
} ledc_chn_fade_param_reg_t;
typedef struct {
volatile ledc_chn_fade_param_reg_t fade_param;
uint32_t reserved[15];
} ledc_chn_fade_param_t;
typedef struct {
volatile ledc_chn_fade_param_t channel[8];
} ledc_ch_fade_param_group_t;
typedef struct ledc_dev_t {
volatile ledc_ch_group_reg_t channel_group[1];
volatile ledc_timer_group_reg_t timer_group[1];
volatile ledc_int_raw_reg_t int_raw;
volatile ledc_int_st_reg_t int_st;
volatile ledc_int_ena_reg_t int_ena;
volatile ledc_int_clr_reg_t int_clr;
uint32_t reserved_0d0[12];
volatile ledc_chn_fade_conf_reg_t chn_fade_conf[8];
volatile ledc_ch_fade_conf_group_reg_t channel_fade_conf_group[1];
volatile ledc_evt_task_en0_reg_t evt_task_en0;
volatile ledc_evt_task_en1_reg_t evt_task_en1;
volatile ledc_evt_task_en2_reg_t evt_task_en2;
uint32_t reserved_12c[5];
volatile ledc_timern_cmp_reg_t timern_cmp[4];
volatile ledc_timern_cnt_cap_reg_t timern_cnt_cap[4];
volatile ledc_timer_cmp_group_reg_t timer_cmp_group[1];
volatile ledc_timer_cnt_cap_group_reg_t timer_cnt_cap_group[1];
uint32_t reserved_160[4];
volatile ledc_conf_reg_t conf;
volatile ledc_ch_power_up_conf_reg_t ch_power_up_conf;
volatile ledc_timer_power_up_conf_reg_t timer_power_up_conf;
volatile ledc_date_reg_t date;
uint32_t reserved_180[160];
volatile ledc_ch_fade_param_group_t channel_fade_param_group[1];
} ledc_dev_t;
extern ledc_dev_t LEDC;
#ifndef __cplusplus
_Static_assert(sizeof(ledc_dev_t) == 0x180, "Invalid size of ledc_dev_t structure");
_Static_assert(sizeof(ledc_dev_t) == 0x600, "Invalid size of ledc_dev_t structure");
#endif
#ifdef __cplusplus
components/soc/esp32h4/register/soc/pcr_reg.h
+1 -1
View File
@@ -571,7 +571,7 @@ extern "C" {
* Configures the clock source of LEDC.
* 0 (default): XTAL_CLK
* 1: RC_FAST_CLK
* 2: PLL_F80M_CLK
* 2: PLL_F96M_CLK
*/
#define PCR_LEDC_SCLK_SEL 0x00000003U
#define PCR_LEDC_SCLK_SEL_M (PCR_LEDC_SCLK_SEL_V << PCR_LEDC_SCLK_SEL_S)
components/soc/esp32h4/register/soc/pcr_struct.h
+1 -1
View File
@@ -482,7 +482,7 @@ typedef union {
* Configures the clock source of LEDC.
* 0 (default): XTAL_CLK
* 1: RC_FAST_CLK
* 2: PLL_F48M_CLK
* 2: PLL_F96M_CLK
*/
uint32_t ledc_sclk_sel:2;
/** ledc_sclk_en : R/W; bitpos: [22]; default: 0;
components/soc/esp32p4/include/soc/Kconfig.soc_caps.in
-12
View File
@@ -747,18 +747,6 @@ config SOC_RTCIO_EDGE_WAKE_SUPPORTED
bool
default y
config SOC_DEDIC_GPIO_OUT_CHANNELS_NUM
int
default 8
config SOC_DEDIC_GPIO_IN_CHANNELS_NUM
int
default 8
config SOC_DEDIC_PERIPH_ALWAYS_ENABLE
bool
default y
config SOC_SDM_SUPPORT_SLEEP_RETENTION
bool
default y
components/soc/esp32p4/include/soc/soc_caps.h
+3 -5
View File
@@ -289,12 +289,10 @@
#define SOC_RTCIO_WAKE_SUPPORTED 1
#define SOC_RTCIO_EDGE_WAKE_SUPPORTED 1
/*-------------------------- Dedicated GPIO CAPS -----------------------------*/
#define SOC_DEDIC_GPIO_OUT_CHANNELS_NUM (8) /*!< 8 outward channels on each CPU core */
#define SOC_DEDIC_GPIO_IN_CHANNELS_NUM (8) /*!< 8 inward channels on each CPU core */
#define SOC_DEDIC_PERIPH_ALWAYS_ENABLE (1) /*!< The dedicated GPIO (a.k.a. fast GPIO) is featured by some customized CPU instructions, which is always enabled */
/*-------------------------- Sigma Delta Modulator CAPS -----------------*/
#define SOC_SDM_SUPPORT_SLEEP_RETENTION 1
/*-------------------------- ETM CAPS -----------------------------------*/
#define SOC_ETM_SUPPORT_SLEEP_RETENTION 1
/*------------------------- Analog Comparator CAPS ---------------------------*/
components/soc/esp32p4/include/soc/soc_caps_full.h
+4
View File
@@ -20,6 +20,10 @@
/*--------------------------- Watch Dog ------------------------------------------*/
#define _SOC_CAPS_WDT_MWDTS_PER_TIMG 1 // Number of main watchdog timers in each Timer Group
/*------------------------------- Dedicated GPIO ------------------------------*/
#define _SOC_CAPS_DEDIC_GPIO_OUT_CHANS_PER_CPU 8 /*!< 8 outward channels on each CPU core */
#define _SOC_CAPS_DEDIC_GPIO_IN_CHANS_PER_CPU 8 /*!< 8 inward channels on each CPU core */
/*--------------------------- SDM (Sigma-Delta Modulator) ------------------------*/
#define _SOC_CAPS_SDM_INST_NUM 1 // Number of SDM instances
#define _SOC_CAPS_SDM_CHANS_PER_INST 8 // Number of channels in each SDM instance
components/soc/esp32s2/include/soc/Kconfig.soc_caps.in
-16
View File
@@ -411,26 +411,10 @@ config SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP
bool
default y
config SOC_DEDIC_GPIO_OUT_CHANNELS_NUM
int
default 8
config SOC_DEDIC_GPIO_IN_CHANNELS_NUM
int
default 8
config SOC_DEDIC_GPIO_ALLOW_REG_ACCESS
bool
default y
config SOC_DEDIC_GPIO_HAS_INTERRUPT
bool
default y
config SOC_DEDIC_GPIO_OUT_AUTO_ENABLE
bool
default y
config SOC_I2C_NUM
int
default 2
components/soc/esp32s2/include/soc/soc_caps.h
-4
View File
@@ -192,11 +192,7 @@
#define SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP (1)
/*-------------------------- Dedicated GPIO CAPS ---------------------------------------*/
#define SOC_DEDIC_GPIO_OUT_CHANNELS_NUM (8) /*!< 8 outward channels on each CPU core */
#define SOC_DEDIC_GPIO_IN_CHANNELS_NUM (8) /*!< 8 inward channels on each CPU core */
#define SOC_DEDIC_GPIO_ALLOW_REG_ACCESS (1) /*!< Allow access dedicated GPIO channel by register */
#define SOC_DEDIC_GPIO_HAS_INTERRUPT (1) /*!< Dedicated GPIO has its own interrupt source */
#define SOC_DEDIC_GPIO_OUT_AUTO_ENABLE (1) /*!< Dedicated GPIO output attribution is enabled automatically */
/*-------------------------- I2C CAPS ----------------------------------------*/
// ESP32-S2 has 2 I2C
components/soc/esp32s2/include/soc/soc_caps_full.h
+4
View File
@@ -29,3 +29,7 @@
#define _SOC_CAPS_PCNT_UNITS_PER_INST 4 // Number of units in each PCNT instance
#define _SOC_CAPS_PCNT_CHANS_PER_UNIT 2 // Number of channels in each PCNT unit
#define _SOC_CAPS_PCNT_THRES_POINT_PER_UNIT 2 // Number of threshold points in each PCNT unit
/*------------------------------- Dedicated GPIO ------------------------------*/
#define _SOC_CAPS_DEDIC_GPIO_OUT_CHANS_PER_CPU 8 /*!< 8 outward channels on each CPU core */
#define _SOC_CAPS_DEDIC_GPIO_IN_CHANS_PER_CPU 8 /*!< 8 inward channels on each CPU core */
components/soc/esp32s3/include/soc/Kconfig.soc_caps.in
-12
View File
@@ -495,18 +495,6 @@ config SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP
bool
default y
config SOC_DEDIC_GPIO_OUT_CHANNELS_NUM
int
default 8
config SOC_DEDIC_GPIO_IN_CHANNELS_NUM
int
default 8
config SOC_DEDIC_GPIO_OUT_AUTO_ENABLE
bool
default y
config SOC_I2C_NUM
int
default 2
components/soc/esp32s3/include/soc/soc_caps.h
-5
View File
@@ -207,11 +207,6 @@
// RTC_IOs and DIG_IOs can be hold during deep sleep and after waking up
#define SOC_GPIO_SUPPORT_HOLD_IO_IN_DSLP (1)
/*-------------------------- Dedicated GPIO CAPS -----------------------------*/
#define SOC_DEDIC_GPIO_OUT_CHANNELS_NUM (8) /*!< 8 outward channels on each CPU core */
#define SOC_DEDIC_GPIO_IN_CHANNELS_NUM (8) /*!< 8 inward channels on each CPU core */
#define SOC_DEDIC_GPIO_OUT_AUTO_ENABLE (1) /*!< Dedicated GPIO output attribution is enabled automatically */
/*-------------------------- I2C CAPS ----------------------------------------*/
// ESP32-S3 has 2 I2C
#define SOC_I2C_NUM (2U)
components/soc/esp32s3/include/soc/soc_caps_full.h
+4
View File
@@ -29,3 +29,7 @@
#define _SOC_CAPS_PCNT_UNITS_PER_INST 4 // Number of units in each PCNT instance
#define _SOC_CAPS_PCNT_CHANS_PER_UNIT 2 // Number of channels in each PCNT unit
#define _SOC_CAPS_PCNT_THRES_POINT_PER_UNIT 2 // Number of threshold points in each PCNT unit
/*------------------------------- Dedicated GPIO ------------------------------*/
#define _SOC_CAPS_DEDIC_GPIO_OUT_CHANS_PER_CPU 8 /*!< 8 outward channels on each CPU core */
#define _SOC_CAPS_DEDIC_GPIO_IN_CHANS_PER_CPU 8 /*!< 8 inward channels on each CPU core */
components/soc/include/soc/dedic_gpio_periph.h
+10 -8
View File
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2020-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -7,25 +7,27 @@
#pragma once
#include <stdint.h>
#include "soc/soc.h"
#include "soc/soc_caps.h"
#include "soc/periph_defs.h"
#include "soc/interrupts.h"
#include "soc/soc_caps_full.h"
#ifdef __cplusplus
extern "C" {
#endif
#if SOC_DEDICATED_GPIO_SUPPORTED
#if SOC_HAS(DEDICATED_GPIO)
// helper macros to access module attributes
#define SOC_DEDIC_GPIO_ATTR(_attr) SOC_MODULE_ATTR(DEDIC_GPIO, _attr)
typedef struct {
const int irq; // Interrupt resource (-1 means no interrupt supported)
struct {
const int in_sig_per_channel[SOC_DEDIC_GPIO_IN_CHANNELS_NUM];
const int out_sig_per_channel[SOC_DEDIC_GPIO_OUT_CHANNELS_NUM];
const int in_sig_per_channel[SOC_DEDIC_GPIO_ATTR(IN_CHANS_PER_CPU)];
const int out_sig_per_channel[SOC_DEDIC_GPIO_ATTR(OUT_CHANS_PER_CPU)];
} cores[SOC_CPU_CORES_NUM]; // Signals routed to/from GPIO matrix
} dedic_gpio_signal_conn_t;
extern const dedic_gpio_signal_conn_t dedic_gpio_periph_signals;
#endif // SOC_DEDICATED_GPIO_SUPPORTED
#endif // SOC_HAS(DEDICATED_GPIO)
#ifdef __cplusplus
}