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feat(pcnt): support pcnt on esp32h4

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This commit is contained in:
Chen Jichang
2025-09-01 10:50:55 +08:00
parent 04b934951e
commit ad5bdc83a7
30 changed files with 997 additions and 115 deletions
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components/soc/esp32/include/soc/clk_tree_defs.h
+15
View File
@@ -218,6 +218,21 @@ typedef enum {
RMT_BASECLK_DEFAULT = SOC_MOD_CLK_APB, /*!< RMT source clock default choice is APB */
} soc_periph_rmt_clk_src_legacy_t;
//////////////////////////////////////////////////PCNT//////////////////////////////////////////////////////////////////
/**
* @brief Array initializer for all supported clock sources of PCNT
*/
#define SOC_PCNT_CLKS {SOC_MOD_CLK_APB}
/**
* @brief Type of PCNT clock source
*/
typedef enum {
PCNT_CLK_SRC_APB = SOC_MOD_CLK_APB, /*!< Select APB as the source clock */
PCNT_CLK_SRC_DEFAULT = SOC_MOD_CLK_APB, /*!< Select APB as the default choice */
} soc_periph_pcnt_clk_src_t;
///////////////////////////////////////////////////UART/////////////////////////////////////////////////////////////////
/**
components/soc/esp32c5/include/soc/clk_tree_defs.h
+16
View File
@@ -87,6 +87,7 @@ typedef enum {
SOC_MOD_CLK_RTC_FAST, /*!< RTC_FAST_CLK can be sourced from XTAL_D2 or RC_FAST by configuring soc_rtc_fast_clk_src_t */
SOC_MOD_CLK_RTC_SLOW, /*!< RTC_SLOW_CLK can be sourced from RC_SLOW, XTAL32K, or OSC_SLOW by configuring soc_rtc_slow_clk_src_t */
// For digital domain: peripherals, WIFI, BLE
SOC_MOD_CLK_APB, /*!< APB_CLK is highly dependent on the CPU_CLK source */
SOC_MOD_CLK_PLL_F12M, /*!< PLL_F12M_CLK is derived from SPLL (clock gating + fixed divider of 40), it has a fixed frequency of 12MHz */
SOC_MOD_CLK_PLL_F20M, /*!< PLL_F20M_CLK is derived from SPLL (clock gating + fixed divider of 24), it has a fixed frequency of 20MHz */
SOC_MOD_CLK_PLL_F40M, /*!< PLL_F40M_CLK is derived from SPLL (clock gating + fixed divider of 12), it has a fixed frequency of 40MHz */
@@ -218,6 +219,21 @@ typedef enum {
RMT_BASECLK_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< RMT source clock default choice is PLL_F80M */
} soc_periph_rmt_clk_src_legacy_t;
//////////////////////////////////////////////////PCNT//////////////////////////////////////////////////////////////////
/**
* @brief Array initializer for all supported clock sources of PCNT
*/
#define SOC_PCNT_CLKS {SOC_MOD_CLK_APB}
/**
* @brief Type of PCNT clock source
*/
typedef enum {
PCNT_CLK_SRC_APB = SOC_MOD_CLK_APB, /*!< Select APB as the source clock */
PCNT_CLK_SRC_DEFAULT = SOC_MOD_CLK_APB, /*!< Select APB as the default choice */
} soc_periph_pcnt_clk_src_t;
//////////////////////////////////////////////////Temp Sensor///////////////////////////////////////////////////////////
/**
components/soc/esp32c6/include/soc/clk_tree_defs.h
+16
View File
@@ -140,6 +140,7 @@ typedef enum {
SOC_MOD_CLK_RTC_FAST, /*!< RTC_FAST_CLK can be sourced from XTAL_D2 or RC_FAST by configuring soc_rtc_fast_clk_src_t */
SOC_MOD_CLK_RTC_SLOW, /*!< RTC_SLOW_CLK can be sourced from RC_SLOW, XTAL32K, RC32K, or OSC_SLOW by configuring soc_rtc_slow_clk_src_t */
// For digital domain: peripherals, WIFI, BLE
SOC_MOD_CLK_APB, /*!< APB_CLK is highly dependent on the CPU_CLK source */
SOC_MOD_CLK_PLL_F80M, /*!< PLL_F80M_CLK is derived from PLL (clock gating + fixed divider of 6), it has a fixed frequency of 80MHz */
SOC_MOD_CLK_PLL_F160M, /*!< PLL_F160M_CLK is derived from PLL (clock gating + fixed divider of 3), it has a fixed frequency of 160MHz */
SOC_MOD_CLK_PLL_F240M, /*!< PLL_F240M_CLK is derived from PLL (clock gating + fixed divider of 2), it has a fixed frequency of 240MHz */
@@ -215,6 +216,21 @@ typedef enum {
RMT_BASECLK_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< RMT source clock default choice is PLL_F80M */
} soc_periph_rmt_clk_src_legacy_t;
//////////////////////////////////////////////////PCNT//////////////////////////////////////////////////////////////////
/**
* @brief Array initializer for all supported clock sources of PCNT
*/
#define SOC_PCNT_CLKS {SOC_MOD_CLK_APB}
/**
* @brief Type of PCNT clock source
*/
typedef enum {
PCNT_CLK_SRC_APB = SOC_MOD_CLK_APB, /*!< Select APB as the source clock */
PCNT_CLK_SRC_DEFAULT = SOC_MOD_CLK_APB, /*!< Select APB as the default choice */
} soc_periph_pcnt_clk_src_t;
//////////////////////////////////////////////////Temp Sensor///////////////////////////////////////////////////////////
/**
components/soc/esp32h2/include/soc/clk_tree_defs.h
+16
View File
@@ -152,6 +152,7 @@ typedef enum {
SOC_MOD_CLK_RTC_FAST, /*!< RTC_FAST_CLK can be sourced from XTAL_D2, RC_FAST, or LP_PLL by configuring soc_rtc_fast_clk_src_t */
SOC_MOD_CLK_RTC_SLOW, /*!< RTC_SLOW_CLK can be sourced from RC_SLOW, XTAL32K, OSC_SLOW, or RC32K by configuring soc_rtc_slow_clk_src_t */
// For digital domain: peripherals, WIFI, BLE
SOC_MOD_CLK_APB, /*!< APB_CLK is highly dependent on the CPU_CLK source */
SOC_MOD_CLK_PLL_F48M, /*!< PLL_F48M_CLK is derived from PLL (clock gating + fixed divider of 2), it has a fixed frequency of 48MHz */
SOC_MOD_CLK_PLL_F64M, /*!< PLL_F64M_CLK is derived from FLASH_PLL (clock gating), it has a fixed frequency of 64MHz */
SOC_MOD_CLK_PLL_F96M, /*!< PLL_F96M_CLK is derived from PLL (clock gating), it has a fixed frequency of 96MHz */
@@ -222,6 +223,21 @@ typedef enum {
RMT_BASECLK_DEFAULT = SOC_MOD_CLK_XTAL, /*!< RMT source clock default choice is XTAL */
} soc_periph_rmt_clk_src_legacy_t;
//////////////////////////////////////////////////PCNT//////////////////////////////////////////////////////////////////
/**
* @brief Array initializer for all supported clock sources of PCNT
*/
#define SOC_PCNT_CLKS {SOC_MOD_CLK_APB}
/**
* @brief Type of PCNT clock source
*/
typedef enum {
PCNT_CLK_SRC_APB = SOC_MOD_CLK_APB, /*!< Select APB as the source clock */
PCNT_CLK_SRC_DEFAULT = SOC_MOD_CLK_APB, /*!< Select APB as the default choice */
} soc_periph_pcnt_clk_src_t;
//////////////////////////////////////////////////Temp Sensor///////////////////////////////////////////////////////////
/**
components/soc/esp32h21/include/soc/clk_tree_defs.h
+16
View File
@@ -133,6 +133,7 @@ typedef enum {
SOC_MOD_CLK_RTC_FAST, /*!< RTC_FAST_CLK can be sourced from XTAL_D2, RC_FAST, or LP_PLL by configuring soc_rtc_fast_clk_src_t */
SOC_MOD_CLK_RTC_SLOW, /*!< RTC_SLOW_CLK can be sourced from RC_SLOW, XTAL32K, OSC_SLOW, or RC32K by configuring soc_rtc_slow_clk_src_t */
// For digital domain: peripherals, BLE
SOC_MOD_CLK_APB, /*!< APB_CLK is highly dependent on the CPU_CLK source */
SOC_MOD_CLK_PLL_F48M, /*!< PLL_F48M_CLK is derived from PLL (clock gating + fixed divider of 2), it has a fixed frequency of 48MHz */
// SOC_MOD_CLK_XTAL_X2_F64M, /*!< XTAL_X2_F64M_CLK is derived from XTAL_X2 (clock gating), it has a fixed frequency of 64MHz */
SOC_MOD_CLK_PLL_F96M, /*!< PLL_F96M_CLK is derived from PLL (clock gating), it has a fixed frequency of 96MHz */
@@ -211,6 +212,21 @@ typedef enum {
RMT_BASECLK_DEFAULT = SOC_MOD_CLK_XTAL, /*!< RMT source clock default choice is XTAL */
} soc_periph_rmt_clk_src_legacy_t;
//////////////////////////////////////////////////PCNT//////////////////////////////////////////////////////////////////
/**
* @brief Array initializer for all supported clock sources of PCNT
*/
#define SOC_PCNT_CLKS {SOC_MOD_CLK_APB}
/**
* @brief Type of PCNT clock source
*/
typedef enum {
PCNT_CLK_SRC_APB = SOC_MOD_CLK_APB, /*!< Select APB as the source clock */
PCNT_CLK_SRC_DEFAULT = SOC_MOD_CLK_APB, /*!< Select APB as the default choice */
} soc_periph_pcnt_clk_src_t;
///////////////////////////////////////////////////UART/////////////////////////////////////////////////////////////////
/**
components/soc/esp32h4/include/soc/Kconfig.soc_caps.in
+16
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@@ -19,6 +19,10 @@ config SOC_GPTIMER_SUPPORTED
bool
default y
config SOC_PCNT_SUPPORTED
bool
default y
config SOC_TWAI_SUPPORTED
bool
default y
@@ -519,6 +523,18 @@ config SOC_MMU_DI_VADDR_SHARED
bool
default y
config SOC_PCNT_SUPPORT_RUNTIME_THRES_UPDATE
bool
default y
config SOC_PCNT_SUPPORT_CLEAR_SIGNAL
bool
default y
config SOC_PCNT_SUPPORT_STEP_NOTIFY
bool
default y
config SOC_RMT_GROUPS
int
default 1
components/soc/esp32h4/include/soc/clk_tree_defs.h
+17
View File
@@ -214,6 +214,23 @@ typedef enum {
RMT_BASECLK_DEFAULT = SOC_MOD_CLK_XTAL, /*!< RMT source clock default choice is XTAL */
} soc_periph_rmt_clk_src_legacy_t;
//////////////////////////////////////////////////PCNT//////////////////////////////////////////////////////////////////
/**
* @brief Array initializer for all supported clock sources of PCNT
*/
#define SOC_PCNT_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_RC_FAST}
/**
* @brief Type of PCNT clock source
*/
typedef enum {
PCNT_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
PCNT_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */
// PCNT_CLK_SRC_XTAL_X2_F32M = SOC_MOD_CLK_XTAL_X2_F32M, /*!< Select XTAL_X2_F32M as the source clock */
PCNT_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the default choice */
} soc_periph_pcnt_clk_src_t;
///////////////////////////////////////////////////UART/////////////////////////////////////////////////////////////////
/**
components/soc/esp32h4/include/soc/soc_caps.h
+4 -6
View File
@@ -38,7 +38,7 @@
#define SOC_GDMA_SUPPORTED 1
#define SOC_AHB_GDMA_SUPPORTED 1
#define SOC_GPTIMER_SUPPORTED 1
// #define SOC_PCNT_SUPPORTED 1 // TODO: [ESP32H4] IDF-12338
#define SOC_PCNT_SUPPORTED 1
// #define SOC_MCPWM_SUPPORTED 1 // TODO: [ESP32H4] IDF-12380
#define SOC_TWAI_SUPPORTED 1
#define SOC_ETM_SUPPORTED 1
@@ -315,11 +315,9 @@
// #define SOC_MPU_REGION_WO_SUPPORTED 0
/*-------------------------- PCNT CAPS ---------------------------------------*/
// #define SOC_PCNT_GROUPS 1U
// #define SOC_PCNT_UNITS_PER_GROUP 4
// #define SOC_PCNT_CHANNELS_PER_UNIT 2
// #define SOC_PCNT_THRES_POINT_PER_UNIT 2
// #define SOC_PCNT_SUPPORT_RUNTIME_THRES_UPDATE 1
#define SOC_PCNT_SUPPORT_RUNTIME_THRES_UPDATE 1
#define SOC_PCNT_SUPPORT_CLEAR_SIGNAL 1
#define SOC_PCNT_SUPPORT_STEP_NOTIFY 1
/*--------------------------- RMT CAPS ---------------------------------------*/
#define SOC_RMT_GROUPS 1U /*!< One RMT group */
components/soc/esp32h4/include/soc/soc_caps_full.h
+6
View File
@@ -24,6 +24,12 @@
#define _SOC_CAPS_SDM_INST_NUM 1 // Number of SDM instances
#define _SOC_CAPS_SDM_CHANS_PER_INST 4 // Number of channels in each SDM instance
/*--------------------------- PCNT (Pulse Counter) ------------------------*/
#define _SOC_CAPS_PCNT_INST_NUM 1 // Number of PCNT instances
#define _SOC_CAPS_PCNT_UNITS_PER_INST 4 // Number of units in each PCNT instance
#define _SOC_CAPS_PCNT_CHANS_PER_UNIT 2 // Number of channels in each PCNT unit
#define _SOC_CAPS_PCNT_THRES_POINT_PER_UNIT 2 // Number of threshold points in each PCNT unit
/*--------------------------- ETM (Event Task Matrix) ----------------------------*/
#define _SOC_CAPS_ETM_INST_NUM 1 // Number of ETM instances
#define _SOC_CAPS_ETM_CHANS_PER_INST 50 // Number of channels in each ETM instance
components/soc/esp32h4/pcnt_periph.c
+70
View File
@@ -0,0 +1,70 @@
/*
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/pcnt_periph.h"
#include "soc/gpio_sig_map.h"
#include "soc/pcnt_reg.h"
const soc_pcnt_signal_desc_t soc_pcnt_signals[1] = {
[0] = {
.irq_id = ETS_PCNT_INTR_SOURCE,
.module_name = "pcnt0",
.units = {
[0] = {
.channels = {
[0] = {
.ctl_sig_id_matrix = PCNT_CTRL_CH0_IN0_IDX,
.pulse_sig_id_matrix = PCNT_SIG_CH0_IN0_IDX
},
[1] = {
.ctl_sig_id_matrix = PCNT_CTRL_CH1_IN0_IDX,
.pulse_sig_id_matrix = PCNT_SIG_CH1_IN0_IDX
}
},
.clear_sig_id_matrix = PCNT_RST_IN0_IDX
},
[1] = {
.channels = {
[0] = {
.ctl_sig_id_matrix = PCNT_CTRL_CH0_IN1_IDX,
.pulse_sig_id_matrix = PCNT_SIG_CH0_IN1_IDX,
},
[1] = {
.ctl_sig_id_matrix = PCNT_CTRL_CH1_IN1_IDX,
.pulse_sig_id_matrix = PCNT_SIG_CH1_IN1_IDX
}
},
.clear_sig_id_matrix = PCNT_RST_IN1_IDX
},
[2] = {
.channels = {
[0] = {
.ctl_sig_id_matrix = PCNT_CTRL_CH0_IN2_IDX,
.pulse_sig_id_matrix = PCNT_SIG_CH0_IN2_IDX,
},
[1] = {
.ctl_sig_id_matrix = PCNT_CTRL_CH1_IN2_IDX,
.pulse_sig_id_matrix = PCNT_SIG_CH1_IN2_IDX
}
},
.clear_sig_id_matrix = PCNT_RST_IN2_IDX
},
[3] = {
.channels = {
[0] = {
.ctl_sig_id_matrix = PCNT_CTRL_CH0_IN3_IDX,
.pulse_sig_id_matrix = PCNT_SIG_CH0_IN3_IDX,
},
[1] = {
.ctl_sig_id_matrix = PCNT_CTRL_CH1_IN3_IDX,
.pulse_sig_id_matrix = PCNT_SIG_CH1_IN3_IDX
}
},
.clear_sig_id_matrix = PCNT_RST_IN3_IDX
}
}
}
};
components/soc/esp32h4/register/soc/pcnt_struct.h
+18 -79
View File
@@ -148,73 +148,22 @@ typedef union {
uint32_t val;
} pcnt_un_conf2_reg_t;
/** Type of u0_conf3 register
* Configuration register for unit $n's step value.
/** Type of un_conf3 register
* Configuration register for unit n's step value.
*/
typedef union {
struct {
/** cnt_h_step_u0 : R/W; bitpos: [15:0]; default: 0;
* Configures the forward rotation step value for unit 0.
/** cnt_h_step_un : R/W; bitpos: [15:0]; default: 0;
* Configures the forward rotation step value for unit n.
*/
uint32_t cnt_h_step_u0:16;
/** cnt_l_step_u0 : R/W; bitpos: [31:16]; default: 0;
* Configures the reverse rotation step value for unit 0.
uint32_t cnt_h_step_un:16;
/** cnt_l_step_un : R/W; bitpos: [31:16]; default: 0;
* Configures the reverse rotation step value for unit n.
*/
uint32_t cnt_l_step_u0:16;
uint32_t cnt_l_step_un:16;
};
uint32_t val;
} pcnt_u0_conf3_reg_t;
/** Type of u1_conf3 register
* Configuration register for unit $n's step value.
*/
typedef union {
struct {
/** cnt_h_step_u1 : R/W; bitpos: [15:0]; default: 0;
* Configures the forward rotation step value for unit 1.
*/
uint32_t cnt_h_step_u1:16;
/** cnt_l_step_u1 : R/W; bitpos: [31:16]; default: 0;
* Configures the reverse rotation step value for unit 1.
*/
uint32_t cnt_l_step_u1:16;
};
uint32_t val;
} pcnt_u1_conf3_reg_t;
/** Type of u2_conf3 register
* Configuration register for unit $n's step value.
*/
typedef union {
struct {
/** cnt_h_step_u2 : R/W; bitpos: [15:0]; default: 0;
* Configures the forward rotation step value for unit 2.
*/
uint32_t cnt_h_step_u2:16;
/** cnt_l_step_u2 : R/W; bitpos: [31:16]; default: 0;
* Configures the reverse rotation step value for unit 2.
*/
uint32_t cnt_l_step_u2:16;
};
uint32_t val;
} pcnt_u2_conf3_reg_t;
/** Type of u3_conf3 register
* Configuration register for unit $n's step value.
*/
typedef union {
struct {
/** cnt_h_step_u3 : R/W; bitpos: [15:0]; default: 0;
* Configures the forward rotation step value for unit 3.
*/
uint32_t cnt_h_step_u3:16;
/** cnt_l_step_u3 : R/W; bitpos: [31:16]; default: 0;
* Configures the reverse rotation step value for unit 3.
*/
uint32_t cnt_l_step_u3:16;
};
uint32_t val;
} pcnt_u3_conf3_reg_t;
} pcnt_un_conf3_reg_t;
/** Type of ctrl register
* Control register for all counters
@@ -484,29 +433,19 @@ typedef union {
} pcnt_date_reg_t;
typedef struct {
volatile pcnt_un_conf0_reg_t u0_conf0;
volatile pcnt_un_conf1_reg_t u0_conf1;
volatile pcnt_un_conf2_reg_t u0_conf2;
volatile pcnt_u0_conf3_reg_t u0_conf3;
volatile pcnt_un_conf0_reg_t u1_conf0;
volatile pcnt_un_conf1_reg_t u1_conf1;
volatile pcnt_un_conf2_reg_t u1_conf2;
volatile pcnt_u1_conf3_reg_t u1_conf3;
volatile pcnt_un_conf0_reg_t u2_conf0;
volatile pcnt_un_conf1_reg_t u2_conf1;
volatile pcnt_un_conf2_reg_t u2_conf2;
volatile pcnt_u2_conf3_reg_t u2_conf3;
volatile pcnt_un_conf0_reg_t u3_conf0;
volatile pcnt_un_conf1_reg_t u3_conf1;
volatile pcnt_un_conf2_reg_t u3_conf2;
volatile pcnt_u3_conf3_reg_t u3_conf3;
volatile pcnt_un_cnt_reg_t un_cnt[4];
typedef struct pcnt_dev_t {
volatile struct {
pcnt_un_conf0_reg_t conf0;
pcnt_un_conf1_reg_t conf1;
pcnt_un_conf2_reg_t conf2;
pcnt_un_conf3_reg_t conf3;
} conf_unit[4];
volatile pcnt_un_cnt_reg_t cnt_unit[4];
volatile pcnt_int_raw_reg_t int_raw;
volatile pcnt_int_st_reg_t int_st;
volatile pcnt_int_ena_reg_t int_ena;
volatile pcnt_int_clr_reg_t int_clr;
volatile pcnt_un_status_reg_t un_status[4];
volatile pcnt_un_status_reg_t status_unit[4];
volatile pcnt_ctrl_reg_t ctrl;
uint32_t reserved_074[34];
volatile pcnt_date_reg_t date;
components/soc/esp32p4/include/soc/clk_tree_defs.h
+16
View File
@@ -160,6 +160,7 @@ typedef enum {
SOC_MOD_CLK_RTC_FAST, /*!< RTC_FAST_CLK can be sourced from XTAL, RC_FAST, or LP_PLL by configuring soc_rtc_fast_clk_src_t */
SOC_MOD_CLK_RTC_SLOW, /*!< RTC_SLOW_CLK can be sourced from RC_SLOW, XTAL32K, or RC32K by configuring soc_rtc_slow_clk_src_t */
// For digital domain: peripherals
SOC_MOD_CLK_APB, /*!< APB_CLK is highly dependent on the CPU_CLK source */
SOC_MOD_CLK_PLL_F20M, /*!< PLL_F20M_CLK is derived from SPLL (clock gating + default divider 24), its default frequency is 20MHz */
SOC_MOD_CLK_PLL_F25M, /*!< PLL_F25M_CLK is derived from MPLL (clock gating + configurable divider), it will have a frequency of 25MHz */
SOC_MOD_CLK_PLL_F50M, /*!< PLL_F50M_CLK is derived from MPLL (clock gating + configurable divider 10), it will have a frequency of 50MHz */
@@ -256,6 +257,21 @@ typedef enum {
RMT_BASECLK_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< RMT source clock default choice is PLL_F80M */
} soc_periph_rmt_clk_src_legacy_t;
//////////////////////////////////////////////////PCNT//////////////////////////////////////////////////////////////////
/**
* @brief Array initializer for all supported clock sources of PCNT
*/
#define SOC_PCNT_CLKS {SOC_MOD_CLK_APB}
/**
* @brief Type of PCNT clock source
*/
typedef enum {
PCNT_CLK_SRC_APB = SOC_MOD_CLK_APB, /*!< Select APB as the source clock */
PCNT_CLK_SRC_DEFAULT = SOC_MOD_CLK_APB, /*!< Select APB as the default choice */
} soc_periph_pcnt_clk_src_t;
///////////////////////////////////////////////////UART/////////////////////////////////////////////////////////////////
/**
components/soc/esp32s2/include/soc/clk_tree_defs.h
+15
View File
@@ -214,6 +214,21 @@ typedef enum {
RMT_BASECLK_DEFAULT = SOC_MOD_CLK_APB, /*!< RMT source clock default choice is APB */
} soc_periph_rmt_clk_src_legacy_t;
//////////////////////////////////////////////////PCNT//////////////////////////////////////////////////////////////////
/**
* @brief Array initializer for all supported clock sources of PCNT
*/
#define SOC_PCNT_CLKS {SOC_MOD_CLK_APB}
/**
* @brief Type of PCNT clock source
*/
typedef enum {
PCNT_CLK_SRC_APB = SOC_MOD_CLK_APB, /*!< Select APB as the source clock */
PCNT_CLK_SRC_DEFAULT = SOC_MOD_CLK_APB, /*!< Select APB as the default choice */
} soc_periph_pcnt_clk_src_t;
//////////////////////////////////////////////////Temp Sensor///////////////////////////////////////////////////////////
/**
components/soc/esp32s3/include/soc/clk_tree_defs.h
+15
View File
@@ -233,6 +233,21 @@ typedef enum {
RMT_BASECLK_DEFAULT = SOC_MOD_CLK_APB, /*!< RMT source clock default choice is APB */
} soc_periph_rmt_clk_src_legacy_t;
//////////////////////////////////////////////////PCNT//////////////////////////////////////////////////////////////////
/**
* @brief Array initializer for all supported clock sources of PCNT
*/
#define SOC_PCNT_CLKS {SOC_MOD_CLK_APB}
/**
* @brief Type of PCNT clock source
*/
typedef enum {
PCNT_CLK_SRC_APB = SOC_MOD_CLK_APB, /*!< Select APB as the source clock */
PCNT_CLK_SRC_DEFAULT = SOC_MOD_CLK_APB, /*!< Select APB as the default choice */
} soc_periph_pcnt_clk_src_t;
//////////////////////////////////////////////////Temp Sensor///////////////////////////////////////////////////////////
/**
components/soc/include/soc/pcnt_periph.h
+1 -1
View File
@@ -9,7 +9,7 @@
#include <stdint.h>
#include <stddef.h>
#include "soc/soc_caps_full.h"
#include "soc/periph_defs.h"
#include "soc/interrupts.h"
// helper macros to access module attributes
#define SOC_PCNT_ATTR(_attr) SOC_MODULE_ATTR(PCNT, _attr)