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Merge branch 'feature/support_touch_on_p4_eco5' into 'master'

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feat(touch): support touch sensor on p4 eco5

Closes IDF-13423 and IDF-13424

See merge request espressif/esp-idf!41802
This commit is contained in:
Kevin (Lao Kaiyao)
2025-09-16 10:06:44 +08:00
parent e8ea973d50 87b19c10ad
commit ac24f96a87
11 changed files with 204 additions and 59 deletions
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components/soc/esp32p4/register/hw_ver3/soc/lp_analog_peri_reg.h
+40 -5
View File
@@ -11,8 +11,6 @@
extern "C" {
#endif
// TODO: IDF-13424
/** LP_ANALOG_PERI_BOD_MODE0_CNTL_REG register
* need_des
*/
@@ -199,6 +197,18 @@ extern "C" {
#define LP_ANALOG_PERI_VDDBAT_CHARGE_UNDERVOLTAGE_TARGET_V 0x000003FFU
#define LP_ANALOG_PERI_VDDBAT_CHARGE_UNDERVOLTAGE_TARGET_S 22
/** LP_ANALOG_PERI_CK_GLITCH_CNTL_REG register
* need_des
*/
#define LP_ANALOG_PERI_CK_GLITCH_CNTL_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x14)
/** LP_ANALOG_PERI_CK_GLITCH_RESET_ENA : R/W; bitpos: [31]; default: 0;
* need_des
*/
#define LP_ANALOG_PERI_CK_GLITCH_RESET_ENA (BIT(31))
#define LP_ANALOG_PERI_CK_GLITCH_RESET_ENA_M (LP_ANALOG_PERI_CK_GLITCH_RESET_ENA_V << LP_ANALOG_PERI_CK_GLITCH_RESET_ENA_S)
#define LP_ANALOG_PERI_CK_GLITCH_RESET_ENA_V 0x00000001U
#define LP_ANALOG_PERI_CK_GLITCH_RESET_ENA_S 31
/** LP_ANALOG_PERI_PG_GLITCH_CNTL_REG register
* need_des
*/
@@ -223,8 +233,6 @@ extern "C" {
#define LP_ANALOG_PERI_ANA_FIB_ENA_V 0xFFFFFFFFU
#define LP_ANALOG_PERI_ANA_FIB_ENA_S 0
#define LP_ANALOG_PERI_LP_ANA_FIB_BOD_RST BIT(1)
/** LP_ANALOG_PERI_INT_RAW_REG register
* need_des
*/
@@ -1595,11 +1603,38 @@ extern "C" {
#define LP_ANALOG_PERI_TOUCH_PAD14_TH2_V 0x0000FFFFU
#define LP_ANALOG_PERI_TOUCH_PAD14_TH2_S 16
/** LP_ANALOG_PERI_TOUCH_CTRL_REG register
* Touch Control Register
*/
#define LP_ANALOG_PERI_TOUCH_CTRL_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x1fc)
/** LP_ANALOG_PERI_TOUCH_UPDATE_BENCHMARK_FREQ_SEL : R/W; bitpos: [1:0]; default: 0;
* Configure the frequency point for software to update the baseline
*/
#define LP_ANALOG_PERI_TOUCH_UPDATE_BENCHMARK_FREQ_SEL 0x00000003U
#define LP_ANALOG_PERI_TOUCH_UPDATE_BENCHMARK_FREQ_SEL_M (LP_ANALOG_PERI_TOUCH_UPDATE_BENCHMARK_FREQ_SEL_V << LP_ANALOG_PERI_TOUCH_UPDATE_BENCHMARK_FREQ_SEL_S)
#define LP_ANALOG_PERI_TOUCH_UPDATE_BENCHMARK_FREQ_SEL_V 0x00000003U
#define LP_ANALOG_PERI_TOUCH_UPDATE_BENCHMARK_FREQ_SEL_S 0
/** LP_ANALOG_PERI_TOUCH_UPDATE_BENCHMARK_PAD_SEL : R/W; bitpos: [5:2]; default: 0;
* Configure the channel for software to update the baseline.
*/
#define LP_ANALOG_PERI_TOUCH_UPDATE_BENCHMARK_PAD_SEL 0x0000000FU
#define LP_ANALOG_PERI_TOUCH_UPDATE_BENCHMARK_PAD_SEL_M (LP_ANALOG_PERI_TOUCH_UPDATE_BENCHMARK_PAD_SEL_V << LP_ANALOG_PERI_TOUCH_UPDATE_BENCHMARK_PAD_SEL_S)
#define LP_ANALOG_PERI_TOUCH_UPDATE_BENCHMARK_PAD_SEL_V 0x0000000FU
#define LP_ANALOG_PERI_TOUCH_UPDATE_BENCHMARK_PAD_SEL_S 2
/** LP_ANALOG_PERI_FREQ_SCAN_CNT_RISE : R/W; bitpos: [7:6]; default: 1;
* Configure the number of hit frequency points that need to be determined for touch
* in frequency hopping mode.
*/
#define LP_ANALOG_PERI_FREQ_SCAN_CNT_RISE 0x00000003U
#define LP_ANALOG_PERI_FREQ_SCAN_CNT_RISE_M (LP_ANALOG_PERI_FREQ_SCAN_CNT_RISE_V << LP_ANALOG_PERI_FREQ_SCAN_CNT_RISE_S)
#define LP_ANALOG_PERI_FREQ_SCAN_CNT_RISE_V 0x00000003U
#define LP_ANALOG_PERI_FREQ_SCAN_CNT_RISE_S 6
/** LP_ANALOG_PERI_DATE_REG register
* need_des
*/
#define LP_ANALOG_PERI_DATE_REG (DR_REG_LP_ANALOG_PERI_BASE + 0x3fc)
/** LP_ANALOG_PERI_LP_ANALOG_PERI_DATE : R/W; bitpos: [30:0]; default: 2294816;
/** LP_ANALOG_PERI_LP_ANALOG_PERI_DATE : R/W; bitpos: [30:0]; default: 2425376;
* need_des
*/
#define LP_ANALOG_PERI_LP_ANALOG_PERI_DATE 0x7FFFFFFFU
components/soc/esp32p4/register/hw_ver3/soc/lp_analog_peri_struct.h
+45 -12
View File
@@ -10,8 +10,6 @@
extern "C" {
#endif
// TODO: IDF-13424
/** Group: configure_register */
/** Type of bod_mode0_cntl register
* need_des
@@ -154,6 +152,20 @@ typedef union {
uint32_t val;
} lp_analog_peri_vddbat_charge_cntl_reg_t;
/** Type of ck_glitch_cntl register
* need_des
*/
typedef union {
struct {
uint32_t reserved_0:31;
/** ck_glitch_reset_ena : R/W; bitpos: [31]; default: 0;
* need_des
*/
uint32_t ck_glitch_reset_ena:1;
};
uint32_t val;
} lp_analog_peri_ck_glitch_cntl_reg_t;
/** Type of pg_glitch_cntl register
* need_des
*/
@@ -692,14 +704,10 @@ typedef union {
* High speed touch driver
*/
uint32_t touch_freq_drv_hs:5;
/** touch_bypass_shield : R/W; bitpos: [18]; default: 0;
* bypass the shield channel output (only available since ECO1)
*/
uint32_t touch_bypass_shield:1;
/** touch_freq_dbias : R/W; bitpos: [22:19]; default: 0;
/** touch_freq_dbias : R/W; bitpos: [22:18]; default: 0;
* Internal LDO voltage
*/
uint32_t touch_freq_dbias:4;
uint32_t touch_freq_dbias:5;
uint32_t reserved_23:9;
};
uint32_t val;
@@ -799,7 +807,7 @@ typedef union {
uint32_t val;
} lp_analog_peri_touch_mux1_reg_t;
/** Type of touch_pad0_th0 register
/** Type of touch_pad_thn register
* need_des
*/
typedef union {
@@ -813,12 +821,35 @@ typedef union {
uint32_t val;
} lp_analog_peri_touch_pad_thn_reg_t;
/** Type of touch_ctrl register
* Touch Control Register
*/
typedef union {
struct {
/** touch_update_benchmark_freq_sel : R/W; bitpos: [1:0]; default: 0;
* Configure the frequency point for software to update the benchmark
*/
uint32_t touch_update_benchmark_freq_sel:2;
/** touch_update_benchmark_pad_sel : R/W; bitpos: [5:2]; default: 0;
* Configure the channel for software to update the benchmark.
*/
uint32_t touch_update_benchmark_pad_sel:4;
/** freq_scan_cnt_rise : R/W; bitpos: [7:6]; default: 1;
* Configure the number of hit frequency points that need to be determined for touch
* in frequency hopping mode.
*/
uint32_t freq_scan_cnt_rise:2;
uint32_t reserved_8:24;
};
uint32_t val;
} lp_analog_peri_touch_ctrl_reg_t;
/** Type of date register
* need_des
*/
typedef union {
struct {
/** lp_analog_peri_date : R/W; bitpos: [30:0]; default: 2294816;
/** lp_analog_peri_date : R/W; bitpos: [30:0]; default: 2425376;
* need_des
*/
uint32_t lp_analog_peri_date:31;
@@ -841,7 +872,7 @@ typedef struct {
volatile lp_analog_peri_vdd_source_cntl_reg_t vdd_source_cntl;
volatile lp_analog_peri_vddbat_bod_cntl_reg_t vddbat_bod_cntl;
volatile lp_analog_peri_vddbat_charge_cntl_reg_t vddbat_charge_cntl;
uint32_t reserved_014;
volatile lp_analog_peri_ck_glitch_cntl_reg_t ck_glitch_cntl;
volatile lp_analog_peri_pg_glitch_cntl_reg_t pg_glitch_cntl;
volatile lp_analog_peri_fib_enable_reg_t fib_enable;
volatile lp_analog_peri_int_raw_reg_t int_raw;
@@ -870,7 +901,9 @@ typedef struct {
volatile lp_analog_peri_touch_mux0_reg_t touch_mux0;
volatile lp_analog_peri_touch_mux1_reg_t touch_mux1;
volatile lp_analog_peri_touch_padx_thn_reg_t touch_padx_thn[15];
uint32_t reserved_1f8[129];
uint32_t reserved_1f8;
volatile lp_analog_peri_touch_ctrl_reg_t touch_ctrl;
uint32_t reserved_200[127];
volatile lp_analog_peri_date_reg_t date;
} lp_analog_peri_dev_t;
components/soc/esp32p4/register/hw_ver3/soc/touch_reg.h
+29 -10
View File
@@ -11,8 +11,6 @@
extern "C" {
#endif
// TODO: IDF-13423
/** RTC_TOUCH_INT_RAW_REG register
* need_des
*/
@@ -59,6 +57,13 @@ extern "C" {
#define RTC_TOUCH_APPROACH_LOOP_DONE_INT_RAW_M (RTC_TOUCH_APPROACH_LOOP_DONE_INT_RAW_V << RTC_TOUCH_APPROACH_LOOP_DONE_INT_RAW_S)
#define RTC_TOUCH_APPROACH_LOOP_DONE_INT_RAW_V 0x00000001U
#define RTC_TOUCH_APPROACH_LOOP_DONE_INT_RAW_S 5
/** RTC_TOUCH_BENCHMARK_UPDATE_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0;
* need_des
*/
#define RTC_TOUCH_BENCHMARK_UPDATE_INT_RAW (BIT(6))
#define RTC_TOUCH_BENCHMARK_UPDATE_INT_RAW_M (RTC_TOUCH_BENCHMARK_UPDATE_INT_RAW_V << RTC_TOUCH_BENCHMARK_UPDATE_INT_RAW_S)
#define RTC_TOUCH_BENCHMARK_UPDATE_INT_RAW_V 0x00000001U
#define RTC_TOUCH_BENCHMARK_UPDATE_INT_RAW_S 6
/** RTC_TOUCH_INT_ST_REG register
* need_des
@@ -106,6 +111,13 @@ extern "C" {
#define RTC_TOUCH_APPROACH_LOOP_DONE_INT_ST_M (RTC_TOUCH_APPROACH_LOOP_DONE_INT_ST_V << RTC_TOUCH_APPROACH_LOOP_DONE_INT_ST_S)
#define RTC_TOUCH_APPROACH_LOOP_DONE_INT_ST_V 0x00000001U
#define RTC_TOUCH_APPROACH_LOOP_DONE_INT_ST_S 5
/** RTC_TOUCH_BENCHMARK_UPDATE_INT_ST : RO; bitpos: [6]; default: 0;
* need_des
*/
#define RTC_TOUCH_BENCHMARK_UPDATE_INT_ST (BIT(6))
#define RTC_TOUCH_BENCHMARK_UPDATE_INT_ST_M (RTC_TOUCH_BENCHMARK_UPDATE_INT_ST_V << RTC_TOUCH_BENCHMARK_UPDATE_INT_ST_S)
#define RTC_TOUCH_BENCHMARK_UPDATE_INT_ST_V 0x00000001U
#define RTC_TOUCH_BENCHMARK_UPDATE_INT_ST_S 6
/** RTC_TOUCH_INT_ENA_REG register
* need_des
@@ -153,6 +165,13 @@ extern "C" {
#define RTC_TOUCH_APPROACH_LOOP_DONE_INT_ENA_M (RTC_TOUCH_APPROACH_LOOP_DONE_INT_ENA_V << RTC_TOUCH_APPROACH_LOOP_DONE_INT_ENA_S)
#define RTC_TOUCH_APPROACH_LOOP_DONE_INT_ENA_V 0x00000001U
#define RTC_TOUCH_APPROACH_LOOP_DONE_INT_ENA_S 5
/** RTC_TOUCH_BENCHMARK_UPDATE_INT_ENA : R/W; bitpos: [6]; default: 0;
* need_des
*/
#define RTC_TOUCH_BENCHMARK_UPDATE_INT_ENA (BIT(6))
#define RTC_TOUCH_BENCHMARK_UPDATE_INT_ENA_M (RTC_TOUCH_BENCHMARK_UPDATE_INT_ENA_V << RTC_TOUCH_BENCHMARK_UPDATE_INT_ENA_S)
#define RTC_TOUCH_BENCHMARK_UPDATE_INT_ENA_V 0x00000001U
#define RTC_TOUCH_BENCHMARK_UPDATE_INT_ENA_S 6
/** RTC_TOUCH_INT_CLR_REG register
* need_des
@@ -200,6 +219,13 @@ extern "C" {
#define RTC_TOUCH_APPROACH_LOOP_DONE_INT_CLR_M (RTC_TOUCH_APPROACH_LOOP_DONE_INT_CLR_V << RTC_TOUCH_APPROACH_LOOP_DONE_INT_CLR_S)
#define RTC_TOUCH_APPROACH_LOOP_DONE_INT_CLR_V 0x00000001U
#define RTC_TOUCH_APPROACH_LOOP_DONE_INT_CLR_S 5
/** RTC_TOUCH_BENCHMARK_UPDATE_INT_CLR : WT; bitpos: [6]; default: 0;
* need_des
*/
#define RTC_TOUCH_BENCHMARK_UPDATE_INT_CLR (BIT(6))
#define RTC_TOUCH_BENCHMARK_UPDATE_INT_CLR_M (RTC_TOUCH_BENCHMARK_UPDATE_INT_CLR_V << RTC_TOUCH_BENCHMARK_UPDATE_INT_CLR_S)
#define RTC_TOUCH_BENCHMARK_UPDATE_INT_CLR_V 0x00000001U
#define RTC_TOUCH_BENCHMARK_UPDATE_INT_CLR_S 6
/** RTC_TOUCH_CHN_STATUS_REG register
* need_des
@@ -219,7 +245,7 @@ extern "C" {
#define RTC_TOUCH_MEAS_DONE_M (RTC_TOUCH_MEAS_DONE_V << RTC_TOUCH_MEAS_DONE_S)
#define RTC_TOUCH_MEAS_DONE_V 0x00000001U
#define RTC_TOUCH_MEAS_DONE_S 15
/** RTC_TOUCH_SCAN_CURR : RO; bitpos: [19:16]; default: 0;
/** RTC_TOUCH_SCAN_CURR : RO; bitpos: [19:16]; default: 15;
* need_des
*/
#define RTC_TOUCH_SCAN_CURR 0x0000000FU
@@ -746,13 +772,6 @@ extern "C" {
* need_des
*/
#define RTC_TOUCH_DATE_REG (DR_REG_LP_TOUCH_BASE + 0x100)
/** RTC_TOUCH_DATE : R/W; bitpos: [27:0]; default: 2294548;
* need_des
*/
#define RTC_TOUCH_DATE 0x0FFFFFFFU
#define RTC_TOUCH_DATE_M (RTC_TOUCH_DATE_V << RTC_TOUCH_DATE_S)
#define RTC_TOUCH_DATE_V 0x0FFFFFFFU
#define RTC_TOUCH_DATE_S 0
/** RTC_TOUCH_CLK_EN : R/W; bitpos: [31]; default: 0;
* need_des
*/
components/soc/esp32p4/register/hw_ver3/soc/touch_struct.h
+22 -12
View File
@@ -10,8 +10,6 @@
extern "C" {
#endif
// TODO: IDF-13423
/** Group: configure_register */
/** Type of int_raw register
* need_des
@@ -42,7 +40,11 @@ typedef union {
* need_des
*/
uint32_t approach_loop_done_int_raw:1;
uint32_t reserved_6:26;
/** benchmark_update_int_raw : R/WTC/SS; bitpos: [6]; default: 0;
* need_des
*/
uint32_t benchmark_update_int_raw:1;
uint32_t reserved_7:25;
};
uint32_t val;
} rtc_touch_int_raw_reg_t;
@@ -76,7 +78,11 @@ typedef union {
* need_des
*/
uint32_t approach_loop_done_int_st:1;
uint32_t reserved_6:26;
/** benchmark_update_int_st : RO; bitpos: [6]; default: 0;
* need_des
*/
uint32_t benchmark_update_int_st:1;
uint32_t reserved_7:25;
};
uint32_t val;
} rtc_touch_int_st_reg_t;
@@ -110,7 +116,11 @@ typedef union {
* need_des
*/
uint32_t approach_loop_done_int_ena:1;
uint32_t reserved_6:26;
/** benchmark_update_int_ena : R/W; bitpos: [6]; default: 0;
* need_des
*/
uint32_t benchmark_update_int_ena:1;
uint32_t reserved_7:25;
};
uint32_t val;
} rtc_touch_int_ena_reg_t;
@@ -144,7 +154,11 @@ typedef union {
* need_des
*/
uint32_t approach_loop_done_int_clr:1;
uint32_t reserved_6:26;
/** benchmark_update_int_clr : WT; bitpos: [6]; default: 0;
* need_des
*/
uint32_t benchmark_update_int_clr:1;
uint32_t reserved_7:25;
};
uint32_t val;
} rtc_touch_int_clr_reg_t;
@@ -162,7 +176,7 @@ typedef union {
* need_des
*/
uint32_t meas_done:1;
/** scan_curr : RO; bitpos: [19:16]; default: 0;
/** scan_curr : RO; bitpos: [19:16]; default: 15;
* need_des
*/
uint32_t scan_curr:4;
@@ -299,11 +313,7 @@ typedef union {
*/
typedef union {
struct {
/** date : R/W; bitpos: [27:0]; default: 2294548;
* need_des
*/
uint32_t date:28;
uint32_t reserved_28:3;
uint32_t reserved_0:31;
/** clk_en : R/W; bitpos: [31]; default: 0;
* need_des
*/