diff --git a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32s31.c b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32s31.c index a71f8acdb72..f602074bb63 100644 --- a/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32s31.c +++ b/components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32s31.c @@ -23,6 +23,7 @@ #include "hal/mspi_ll.h" #include "hal/cache_hal.h" #include "hal/cache_ll.h" +#include "hal/clk_tree_ll.h" #include "esp_private/bootloader_flash_internal.h" void IRAM_ATTR bootloader_flash_update_id(void) @@ -46,6 +47,7 @@ void IRAM_ATTR bootloader_flash_cs_timing_config(void) void IRAM_ATTR bootloader_init_mspi_clock(void) { cache_hal_disable(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_ALL); + clk_ll_bbpll_enable(); _mspi_timing_ll_set_flash_core_clock(0, 80); _mspi_timing_ll_set_flash_clk_src(0, FLASH_CLK_SRC_BBPLL); cache_hal_enable(CACHE_LL_LEVEL_EXT_MEM, CACHE_TYPE_ALL); diff --git a/components/bootloader_support/src/esp32s31/bootloader_esp32s31.c b/components/bootloader_support/src/esp32s31/bootloader_esp32s31.c index 2ab911c88c1..965af764f03 100644 --- a/components/bootloader_support/src/esp32s31/bootloader_esp32s31.c +++ b/components/bootloader_support/src/esp32s31/bootloader_esp32s31.c @@ -34,7 +34,6 @@ #include "esp_rom_sys.h" #include "soc/regi2c_bias.h" #include "hal/regi2c_ctrl.h" -#include "hal/clk_tree_ll.h" #include "hal/psram_ctrlr_ll.h" ESP_LOG_ATTR_TAG(TAG, "boot.esp32s31"); @@ -61,11 +60,11 @@ static inline void bootloader_hardware_init(void) REGI2C_WRITE_MASK(I2C_BIAS, I2C_BIAS_DREG_1P1, 10); REGI2C_WRITE_MASK(I2C_BIAS, I2C_BIAS_DREG_1P1_PVT, 10); - /* Disable MPLL by default, during mmu_hal_init, a valid clock source is required for the PSRAM, - so before shutting down mpll, the PSRAM clock source should be selected to an always-on source. */ + /* During mmu_hal_init, a valid clock source is required for the PSRAM, + so before shutting down MPLL in rtc_clk_init, the PSRAM clock source + should be selected to an always-on source. */ _psram_ctrlr_ll_select_clk_source(PSRAM_CTRLR_LL_MSPI_ID_2, PSRAM_CLK_SRC_XTAL); _psram_ctrlr_ll_select_clk_source(PSRAM_CTRLR_LL_MSPI_ID_3, PSRAM_CLK_SRC_XTAL); - clk_ll_mpll_disable(); } void bootloader_enable_cpu_reset_info(void) diff --git a/components/esp_adc/linker.lf b/components/esp_adc/linker.lf index e3c1ea4ee25..c189a1f9bbb 100644 --- a/components/esp_adc/linker.lf +++ b/components/esp_adc/linker.lf @@ -9,6 +9,8 @@ archive: libesp_hw_support.a entries: if ADC_ONESHOT_CTRL_FUNC_IN_IRAM = y: esp_clk_tree: esp_clk_tree_enable_src (noflash) + if IDF_TARGET_ESP32P4 || IDF_TARGET_ESP32S31 = y: + esp_clk_tree: s_gated_ref_clks (noflash) [mapping:adc_hal] archive: libesp_hal_ana_conv.a diff --git a/components/esp_driver_cam/dvp/src/esp_cam_ctlr_dvp_cam.c b/components/esp_driver_cam/dvp/src/esp_cam_ctlr_dvp_cam.c index 3d8c36300ab..56a6252185f 100644 --- a/components/esp_driver_cam/dvp/src/esp_cam_ctlr_dvp_cam.c +++ b/components/esp_driver_cam/dvp/src/esp_cam_ctlr_dvp_cam.c @@ -65,6 +65,7 @@ typedef struct dvp_platform { static dvp_platform_t s_platform; static const char *TAG = "dvp_cam"; +static soc_module_clk_t s_dvp_clk_src[CAP_DVP_PERIPH_NUM]; /** * @brief Claim DVP controller @@ -345,6 +346,11 @@ esp_err_t esp_cam_ctlr_dvp_init(int ctlr_id, cam_clock_source_t clk_src, const e esp_rom_gpio_connect_out_signal(pin->xclk_io, cam_periph_signals.buses[ctlr_id].clk_sig, false, false); } +#if CONFIG_IDF_TARGET_ESP32S31 + // PLL 120M was selected in esp_perip_clk_init on esp32s31. + ESP_ERROR_CHECK(esp_clk_tree_enable_src((soc_module_clk_t)SOC_MOD_CLK_PLL_F120M, true)); +#endif + PERIPH_RCC_ACQUIRE_ATOMIC(cam_periph_signals.buses[ctlr_id].module, ref_count) { if (ref_count == 0) { cam_ll_enable_bus_clock(ctlr_id, true); @@ -353,6 +359,7 @@ esp_err_t esp_cam_ctlr_dvp_init(int ctlr_id, cam_clock_source_t clk_src, const e } ESP_ERROR_CHECK(esp_clk_tree_enable_src((soc_module_clk_t)clk_src, true)); + s_dvp_clk_src[ctlr_id] = (soc_module_clk_t)clk_src; PERIPH_RCC_ATOMIC() { cam_ll_enable_clk(ctlr_id, true); cam_ll_select_clk_src(ctlr_id, clk_src); @@ -457,6 +464,15 @@ esp_err_t esp_cam_ctlr_dvp_deinit(int ctlr_id) } } + if (s_dvp_clk_src[ctlr_id]) { + esp_clk_tree_enable_src(s_dvp_clk_src[ctlr_id], false); + s_dvp_clk_src[ctlr_id] = 0; + } + +#if CONFIG_IDF_TARGET_ESP32S31 + esp_clk_tree_enable_src((soc_module_clk_t)SOC_MOD_CLK_PLL_F120M, false); +#endif + return ESP_OK; } diff --git a/components/esp_driver_gptimer/test_apps/gptimer/main/test_gptimer_sleep.c b/components/esp_driver_gptimer/test_apps/gptimer/main/test_gptimer_sleep.c index 49f7637cb1c..788ef809946 100644 --- a/components/esp_driver_gptimer/test_apps/gptimer/main/test_gptimer_sleep.c +++ b/components/esp_driver_gptimer/test_apps/gptimer/main/test_gptimer_sleep.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -18,7 +18,13 @@ #include "esp_private/esp_sleep_internal.h" #include "esp_private/esp_pmu.h" -static bool test_gptimer_alarm_stop_callback(gptimer_handle_t timer, const gptimer_alarm_event_data_t *edata, void *user_data) +#if CONFIG_GPTIMER_ISR_CACHE_SAFE +#define TEST_ALARM_CALLBACK_ATTR IRAM_ATTR +#else +#define TEST_ALARM_CALLBACK_ATTR +#endif // CONFIG_GPTIMER_ISR_CACHE_SAFE + +TEST_ALARM_CALLBACK_ATTR static bool test_gptimer_alarm_stop_callback(gptimer_handle_t timer, const gptimer_alarm_event_data_t *edata, void *user_data) { TaskHandle_t task_handle = (TaskHandle_t)user_data; BaseType_t high_task_wakeup; diff --git a/components/esp_hal_ana_cmpr/esp32s31/include/hal/ana_cmpr_ll.h b/components/esp_hal_ana_cmpr/esp32s31/include/hal/ana_cmpr_ll.h index a57fbd83733..aee64445668 100644 --- a/components/esp_hal_ana_cmpr/esp32s31/include/hal/ana_cmpr_ll.h +++ b/components/esp_hal_ana_cmpr/esp32s31/include/hal/ana_cmpr_ll.h @@ -105,7 +105,7 @@ static inline void analog_cmpr_ll_set_clk_src(int unit_id, ana_cmpr_clk_src_t cl case ANA_CMPR_CLK_SRC_RC_FAST: HP_SYS_CLKRST.zero_det_ctrl0.reg_zero_det_clk_src_sel = 1; break; - case ANA_CMPR_CLK_SRC_PLL_F80M: + case ANA_CMPR_CLK_SRC_REF_F80M: HP_SYS_CLKRST.zero_det_ctrl0.reg_zero_det_clk_src_sel = 2; break; default: diff --git a/components/esp_hal_clock/esp32s31/include/hal/clk_gate_ll.h b/components/esp_hal_clock/esp32s31/include/hal/clk_gate_ll.h index 4f2f2f723fc..a7be7133f3e 100644 --- a/components/esp_hal_clock/esp32s31/include/hal/clk_gate_ll.h +++ b/components/esp_hal_clock/esp32s31/include/hal/clk_gate_ll.h @@ -271,6 +271,19 @@ FORCE_INLINE_ATTR void _clk_gate_ll_ref_50m_clk_en(bool enable) _clk_gate_ll_ref_50m_clk_en(__VA_ARGS__); \ } while(0) +/** + * Enable or disable the clock gate for ref_60m. + * @param enable Enable / disable + */ +FORCE_INLINE_ATTR void _clk_gate_ll_ref_60m_clk_en(bool enable) +{ + HP_SYS_CLKRST.ref_60m_ctrl0.reg_ref_60m_clk_en = enable; +} +#define clk_gate_ll_ref_60m_clk_en(...) do { \ + (void)__DECLARE_RCC_ATOMIC_ENV; \ + _clk_gate_ll_ref_60m_clk_en(__VA_ARGS__); \ + } while (0) + /** * Enable or disable the clock gate for ref_80m (derived from BBPLL). * @param enable Enable / disable @@ -286,6 +299,32 @@ FORCE_INLINE_ATTR void _clk_gate_ll_ref_80m_clk_en(bool enable) _clk_gate_ll_ref_80m_clk_en(__VA_ARGS__); \ } while(0) +/** + * Enable or disable the ref_80m mux clock gate. + * @param en 0: disable 1: enable + */ +FORCE_INLINE_ATTR void _clk_gate_ll_ref_80m_mux_clk_en(bool en) +{ + HP_SYS_CLKRST.ref_80m_ctrl0.reg_ref_80m_mux_clk_en = en; +} +#define clk_gate_ll_ref_80m_mux_clk_en(...) do { \ + (void)__DECLARE_RCC_ATOMIC_ENV; \ + _clk_gate_ll_ref_80m_mux_clk_en(__VA_ARGS__); \ + } while (0) + +/** + * Enable or disable the clock gate for ref_120m. + * @param enable Enable / disable + */ +FORCE_INLINE_ATTR void _clk_gate_ll_ref_120m_clk_en(bool enable) +{ + HP_SYS_CLKRST.ref_120m_ctrl0.reg_ref_120m_clk_en = enable; +} +#define clk_gate_ll_ref_120m_clk_en(...) do { \ + (void)__DECLARE_RCC_ATOMIC_ENV; \ + _clk_gate_ll_ref_120m_clk_en(__VA_ARGS__); \ + } while (0) + /** * Enable or disable the clock gate for ref_160m (derived from BBPLL). * @param enable Enable / disable diff --git a/components/esp_hal_clock/esp32s31/include/hal/clk_tree_ll.h b/components/esp_hal_clock/esp32s31/include/hal/clk_tree_ll.h index a8d8839e49a..9bf7a1bd0aa 100644 --- a/components/esp_hal_clock/esp32s31/include/hal/clk_tree_ll.h +++ b/components/esp_hal_clock/esp32s31/include/hal/clk_tree_ll.h @@ -29,7 +29,9 @@ #define CLK_LL_PLL_8M_FREQ_MHZ (8) +#define CLK_LL_PLL_60M_FREQ_MHZ (60) #define CLK_LL_PLL_80M_FREQ_MHZ (80) +#define CLK_LL_PLL_120M_FREQ_MHZ (120) #define CLK_LL_PLL_160M_FREQ_MHZ (160) #define CLK_LL_PLL_240M_FREQ_MHZ (240) #define CLK_LL_PLL_320M_FREQ_MHZ (320) @@ -105,6 +107,47 @@ static inline __attribute__((always_inline)) void clk_ll_cpll_disable(void) CLEAR_PERI_REG_MASK(HP_ALIVE_SYS_HP_CLK_CTRL_REG, HP_ALIVE_SYS_HP_CPLL_300M_CLK_EN); } +/** + * @brief Power up XTALX2 circuit + */ +static inline __attribute__((always_inline)) void clk_ll_xtalx2_enable(void) +{ + SET_PERI_REG_MASK(PMU_IMM_HP_CK_POWER_0_REG, PMU_TIE_HIGH_XPD_XTALX2); + SET_PERI_REG_MASK(PMU_IMM_HP_CK_POWER_0_REG, PMU_TIE_HIGH_GLOBAL_XTALX2_ICG); + SET_PERI_REG_MASK(HP_ALIVE_SYS_HP_CLK_CTRL_REG, HP_ALIVE_SYS_HP_XTALX2_80M_CLK_EN); +} + +/** + * @brief Power down XTALX2 circuit + */ +static inline __attribute__((always_inline)) void clk_ll_xtalx2_disable(void) +{ + CLEAR_PERI_REG_MASK(HP_ALIVE_SYS_HP_CLK_CTRL_REG, HP_ALIVE_SYS_HP_XTALX2_80M_CLK_EN); + SET_PERI_REG_MASK(PMU_IMM_HP_CK_POWER_0_REG, PMU_TIE_LOW_GLOBAL_XTALX2_ICG); + SET_PERI_REG_MASK(PMU_IMM_HP_CK_POWER_0_REG, PMU_TIE_LOW_XPD_XTALX2); +} + +/** + * @brief Get ref_80m clock source mux selection + * + * @return false: BBPLL divided path, true: XTALx2 80MHz (`clk_xtalx2_80m`) + */ +static inline __attribute__((always_inline)) bool clk_ll_ref_80m_get_src(void) +{ + return (bool)HP_SYS_CLKRST.ref_80m_ctrl0.reg_ref_80m_sel; +} + +/** + * @brief Select REF_80M_CLK source + * + * @param in_sel 0 selects BBPLL divided 80MHz, 1 selects XTALx2 80MHz. + */ +static inline __attribute__((always_inline)) void clk_ll_ref_80m_set_src(uint8_t in_sel) +{ + HAL_ASSERT(in_sel == 0 || in_sel == 1); + HP_SYS_CLKRST.ref_80m_ctrl0.reg_ref_80m_sel = in_sel; +} + /** * @brief Power up BBPLL circuit */ @@ -710,6 +753,16 @@ static inline __attribute__((always_inline)) void clk_ll_ref_500m_set_src(uint8_ HP_SYS_CLKRST.ref_500m_ctrl0.reg_ref_500m_sel = in_sel; } +/** + * @brief Get ref_500m clock source mux selection + * + * @return false: CPLL (320MHz), true: MPLL (500MHz) + */ +static inline __attribute__((always_inline)) bool clk_ll_ref_500m_get_src(void) +{ + return (bool)HP_SYS_CLKRST.ref_500m_ctrl0.reg_ref_500m_sel; +} + /** * @brief Set PLL_F50M_CLK divider. freq of PLL_F50M_CLK = freq of MPLL_CLK / divider * @@ -753,6 +806,26 @@ static inline __attribute__((always_inline)) uint32_t clk_ll_pll_f20m_get_divide return HAL_FORCE_READ_U32_REG_FIELD(HP_SYS_CLKRST.ref_20m_ctrl0, reg_ref_20m_clk_div_num) + 1; } +/** + * @brief Get PLL_F50M_CLK divider + * + * @return Divider. Divider = (CLK_DIV_NUM + 1). + */ +static inline __attribute__((always_inline)) uint32_t clk_ll_pll_f50m_get_divider(void) +{ + return HAL_FORCE_READ_U32_REG_FIELD(HP_SYS_CLKRST.ref_50m_ctrl0, reg_ref_50m_clk_div_num) + 1; +} + +/** + * @brief Get PLL_F25M_CLK divider + * + * @return Divider. Divider = (CLK_DIV_NUM + 1). + */ +static inline __attribute__((always_inline)) uint32_t clk_ll_pll_f25m_get_divider(void) +{ + return HAL_FORCE_READ_U32_REG_FIELD(HP_SYS_CLKRST.ref_25m_ctrl0, reg_ref_25m_clk_div_num) + 1; +} + /** * @brief Select the frequency calculation clock source for timergroup0 * diff --git a/components/esp_hal_emac/esp32s31/include/hal/emac_ll.h b/components/esp_hal_emac/esp32s31/include/hal/emac_ll.h index f2c798d6520..24a2220ee7a 100644 --- a/components/esp_hal_emac/esp32s31/include/hal/emac_ll.h +++ b/components/esp_hal_emac/esp32s31/include/hal/emac_ll.h @@ -1086,7 +1086,7 @@ static inline void emac_ll_clock_enable_ptp(void *ext_regs, soc_periph_emac_ptp_ case EMAC_PTP_CLK_SRC_XTAL: clk_src_val = 0; break; - case EMAC_PTP_CLK_SRC_PLL_F80M: + case EMAC_PTP_CLK_SRC_REF_F80M: clk_src_val = 1; break; default: diff --git a/components/esp_hal_gpio/esp32s31/include/hal/gpio_ll.h b/components/esp_hal_gpio/esp32s31/include/hal/gpio_ll.h index cad4bdeffe5..d151fa5f0ae 100644 --- a/components/esp_hal_gpio/esp32s31/include/hal/gpio_ll.h +++ b/components/esp_hal_gpio/esp32s31/include/hal/gpio_ll.h @@ -712,7 +712,7 @@ static inline void gpio_ll_iomux_set_clk_src(soc_module_clk_t src) case SOC_MOD_CLK_XTAL: HP_SYS_CLKRST.iomux_ctrl0.reg_iomux_clk_src_sel = 0; break; - case SOC_MOD_CLK_PLL_F80M: + case SOC_MOD_CLK_REF_F80M: HP_SYS_CLKRST.iomux_ctrl0.reg_iomux_clk_src_sel = 1; break; default: diff --git a/components/esp_hal_rmt/esp32s31/include/hal/rmt_ll.h b/components/esp_hal_rmt/esp32s31/include/hal/rmt_ll.h index 49b1d2fa949..cf3b484bf9f 100644 --- a/components/esp_hal_rmt/esp32s31/include/hal/rmt_ll.h +++ b/components/esp_hal_rmt/esp32s31/include/hal/rmt_ll.h @@ -173,7 +173,7 @@ static inline void rmt_ll_set_group_clock_src(rmt_dev_t *dev, uint32_t channel, HAL_FORCE_MODIFY_U32_REG_FIELD(HP_SYS_CLKRST.rmt_ctrl0, reg_rmt_clk_div_numerator, divider_numerator); HAL_FORCE_MODIFY_U32_REG_FIELD(HP_SYS_CLKRST.rmt_ctrl0, reg_rmt_clk_div_denominator, divider_denominator); switch (src) { - case RMT_CLK_SRC_PLL_F80M: + case RMT_CLK_SRC_REF_F80M: HP_SYS_CLKRST.rmt_ctrl0.reg_rmt_clk_src_sel = 2; break; case RMT_CLK_SRC_RC_FAST: diff --git a/components/esp_hal_security/esp32/include/hal/sec_ll.h b/components/esp_hal_security/esp32/include/hal/sec_ll.h new file mode 100644 index 00000000000..626e6ecefac --- /dev/null +++ b/components/esp_hal_security/esp32/include/hal/sec_ll.h @@ -0,0 +1,26 @@ +/* + * SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include "soc/clk_tree_defs.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Select crypto clock source + * + * @note Not supported. No-op. + */ +static inline __attribute__((always_inline)) void sec_ll_crypto_clk_src_sel(soc_module_clk_t src) +{ + (void)src; +} + +#ifdef __cplusplus +} +#endif diff --git a/components/esp_hal_security/esp32c2/include/hal/sec_ll.h b/components/esp_hal_security/esp32c2/include/hal/sec_ll.h new file mode 100644 index 00000000000..626e6ecefac --- /dev/null +++ b/components/esp_hal_security/esp32c2/include/hal/sec_ll.h @@ -0,0 +1,26 @@ +/* + * SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include "soc/clk_tree_defs.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Select crypto clock source + * + * @note Not supported. No-op. + */ +static inline __attribute__((always_inline)) void sec_ll_crypto_clk_src_sel(soc_module_clk_t src) +{ + (void)src; +} + +#ifdef __cplusplus +} +#endif diff --git a/components/esp_hal_security/esp32c3/include/hal/sec_ll.h b/components/esp_hal_security/esp32c3/include/hal/sec_ll.h new file mode 100644 index 00000000000..626e6ecefac --- /dev/null +++ b/components/esp_hal_security/esp32c3/include/hal/sec_ll.h @@ -0,0 +1,26 @@ +/* + * SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include "soc/clk_tree_defs.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Select crypto clock source + * + * @note Not supported. No-op. + */ +static inline __attribute__((always_inline)) void sec_ll_crypto_clk_src_sel(soc_module_clk_t src) +{ + (void)src; +} + +#ifdef __cplusplus +} +#endif diff --git a/components/esp_hal_security/esp32c5/include/hal/sec_ll.h b/components/esp_hal_security/esp32c5/include/hal/sec_ll.h new file mode 100644 index 00000000000..343bf94582b --- /dev/null +++ b/components/esp_hal_security/esp32c5/include/hal/sec_ll.h @@ -0,0 +1,39 @@ +/* + * SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/clk_tree_defs.h" +#include "soc/pcr_struct.h" +#include "hal/assert.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Select crypto clock source. + * + * @param src Clock source (SOC_MOD_CLK_XTAL, SOC_MOD_CLK_RC_FAST, or SOC_MOD_CLK_SPLL) + */ +static inline __attribute__((always_inline)) void sec_ll_crypto_clk_src_sel(soc_module_clk_t src) +{ + uint32_t reg_val = 3; + if (src == SOC_MOD_CLK_XTAL) { + reg_val = 0; + } else if (src == SOC_MOD_CLK_RC_FAST) { + reg_val = 1; + } else if (src == SOC_MOD_CLK_SPLL) { + reg_val = 2; + } else { + HAL_ASSERT(false); + } + PCR.sec_conf.sec_clk_sel = reg_val; +} + +#ifdef __cplusplus +} +#endif diff --git a/components/esp_hal_security/esp32c6/include/hal/sec_ll.h b/components/esp_hal_security/esp32c6/include/hal/sec_ll.h new file mode 100644 index 00000000000..626e6ecefac --- /dev/null +++ b/components/esp_hal_security/esp32c6/include/hal/sec_ll.h @@ -0,0 +1,26 @@ +/* + * SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include "soc/clk_tree_defs.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Select crypto clock source + * + * @note Not supported. No-op. + */ +static inline __attribute__((always_inline)) void sec_ll_crypto_clk_src_sel(soc_module_clk_t src) +{ + (void)src; +} + +#ifdef __cplusplus +} +#endif diff --git a/components/esp_hal_security/esp32c61/include/hal/sec_ll.h b/components/esp_hal_security/esp32c61/include/hal/sec_ll.h new file mode 100644 index 00000000000..343bf94582b --- /dev/null +++ b/components/esp_hal_security/esp32c61/include/hal/sec_ll.h @@ -0,0 +1,39 @@ +/* + * SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/clk_tree_defs.h" +#include "soc/pcr_struct.h" +#include "hal/assert.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Select crypto clock source. + * + * @param src Clock source (SOC_MOD_CLK_XTAL, SOC_MOD_CLK_RC_FAST, or SOC_MOD_CLK_SPLL) + */ +static inline __attribute__((always_inline)) void sec_ll_crypto_clk_src_sel(soc_module_clk_t src) +{ + uint32_t reg_val = 3; + if (src == SOC_MOD_CLK_XTAL) { + reg_val = 0; + } else if (src == SOC_MOD_CLK_RC_FAST) { + reg_val = 1; + } else if (src == SOC_MOD_CLK_SPLL) { + reg_val = 2; + } else { + HAL_ASSERT(false); + } + PCR.sec_conf.sec_clk_sel = reg_val; +} + +#ifdef __cplusplus +} +#endif diff --git a/components/esp_hal_security/esp32h2/include/hal/sec_ll.h b/components/esp_hal_security/esp32h2/include/hal/sec_ll.h new file mode 100644 index 00000000000..bc91058af56 --- /dev/null +++ b/components/esp_hal_security/esp32h2/include/hal/sec_ll.h @@ -0,0 +1,41 @@ +/* + * SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/clk_tree_defs.h" +#include "soc/pcr_struct.h" +#include "hal/assert.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Select crypto clock source. + * + * @param src Clock source (SOC_MOD_CLK_XTAL, SOC_MOD_CLK_RC_FAST, SOC_MOD_CLK_PLL_F64M, or SOC_MOD_CLK_PLL_F96M) + */ +static inline __attribute__((always_inline)) void sec_ll_crypto_clk_src_sel(soc_module_clk_t src) +{ + uint32_t reg_val = 3; + if (src == SOC_MOD_CLK_XTAL) { + reg_val = 0; + } else if (src == SOC_MOD_CLK_RC_FAST) { + reg_val = 1; + } else if (src == SOC_MOD_CLK_PLL_F64M) { + reg_val = 2; + } else if (src == SOC_MOD_CLK_PLL_F96M) { + reg_val = 3; + } else { + HAL_ASSERT(false); + } + PCR.sec_conf.sec_clk_sel = reg_val; +} + +#ifdef __cplusplus +} +#endif diff --git a/components/esp_hal_security/esp32h21/include/hal/sec_ll.h b/components/esp_hal_security/esp32h21/include/hal/sec_ll.h new file mode 100644 index 00000000000..6d6512bada3 --- /dev/null +++ b/components/esp_hal_security/esp32h21/include/hal/sec_ll.h @@ -0,0 +1,41 @@ +/* + * SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/clk_tree_defs.h" +#include "soc/pcr_struct.h" +#include "hal/assert.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Select crypto clock source. + * + * @param src Clock source (SOC_MOD_CLK_XTAL, SOC_MOD_CLK_RC_FAST, SOC_MOD_CLK_XTAL_X2_F64M, or SOC_MOD_CLK_PLL_F96M) + */ +static inline __attribute__((always_inline)) void sec_ll_crypto_clk_src_sel(soc_module_clk_t src) +{ + uint32_t reg_val = 3; + if (src == SOC_MOD_CLK_XTAL) { + reg_val = 0; + } else if (src == SOC_MOD_CLK_RC_FAST) { + reg_val = 1; + } else if (src == SOC_MOD_CLK_XTAL_X2_F64M) { + reg_val = 2; + } else if (src == SOC_MOD_CLK_PLL_F96M) { + reg_val = 3; + } else { + HAL_ASSERT(false); + } + PCR.sec_conf.sec_clk_sel = reg_val; +} + +#ifdef __cplusplus +} +#endif diff --git a/components/esp_hal_security/esp32h4/include/hal/sec_ll.h b/components/esp_hal_security/esp32h4/include/hal/sec_ll.h new file mode 100644 index 00000000000..6d6512bada3 --- /dev/null +++ b/components/esp_hal_security/esp32h4/include/hal/sec_ll.h @@ -0,0 +1,41 @@ +/* + * SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/clk_tree_defs.h" +#include "soc/pcr_struct.h" +#include "hal/assert.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Select crypto clock source. + * + * @param src Clock source (SOC_MOD_CLK_XTAL, SOC_MOD_CLK_RC_FAST, SOC_MOD_CLK_XTAL_X2_F64M, or SOC_MOD_CLK_PLL_F96M) + */ +static inline __attribute__((always_inline)) void sec_ll_crypto_clk_src_sel(soc_module_clk_t src) +{ + uint32_t reg_val = 3; + if (src == SOC_MOD_CLK_XTAL) { + reg_val = 0; + } else if (src == SOC_MOD_CLK_RC_FAST) { + reg_val = 1; + } else if (src == SOC_MOD_CLK_XTAL_X2_F64M) { + reg_val = 2; + } else if (src == SOC_MOD_CLK_PLL_F96M) { + reg_val = 3; + } else { + HAL_ASSERT(false); + } + PCR.sec_conf.sec_clk_sel = reg_val; +} + +#ifdef __cplusplus +} +#endif diff --git a/components/esp_hal_security/esp32p4/include/hal/sec_ll.h b/components/esp_hal_security/esp32p4/include/hal/sec_ll.h new file mode 100644 index 00000000000..a48e5a2d4c7 --- /dev/null +++ b/components/esp_hal_security/esp32p4/include/hal/sec_ll.h @@ -0,0 +1,41 @@ +/* + * SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/clk_tree_defs.h" +#include "soc/hp_sys_clkrst_struct.h" +#include "hal/assert.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Select crypto clock source. + * + * @param src Clock source (SOC_MOD_CLK_XTAL, SOC_MOD_CLK_RC_FAST, SOC_MOD_CLK_PLL_F240M, or SOC_MOD_CLK_PLL_F160M) + */ +static inline __attribute__((always_inline)) void sec_ll_crypto_clk_src_sel(soc_module_clk_t src) +{ + uint32_t reg_val = 3; + if (src == SOC_MOD_CLK_XTAL) { + reg_val = 0; + } else if (src == SOC_MOD_CLK_RC_FAST) { + reg_val = 1; + } else if (src == SOC_MOD_CLK_PLL_F240M) { + reg_val = 2; + } else if (src == SOC_MOD_CLK_PLL_F160M) { + reg_val = 3; + } else { + HAL_ASSERT(false); + } + HP_SYS_CLKRST.peri_clk_ctrl25.reg_crypto_clk_src_sel = reg_val; +} + +#ifdef __cplusplus +} +#endif diff --git a/components/esp_hal_security/esp32s2/include/hal/sec_ll.h b/components/esp_hal_security/esp32s2/include/hal/sec_ll.h new file mode 100644 index 00000000000..626e6ecefac --- /dev/null +++ b/components/esp_hal_security/esp32s2/include/hal/sec_ll.h @@ -0,0 +1,26 @@ +/* + * SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include "soc/clk_tree_defs.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Select crypto clock source + * + * @note Not supported. No-op. + */ +static inline __attribute__((always_inline)) void sec_ll_crypto_clk_src_sel(soc_module_clk_t src) +{ + (void)src; +} + +#ifdef __cplusplus +} +#endif diff --git a/components/esp_hal_security/esp32s3/include/hal/sec_ll.h b/components/esp_hal_security/esp32s3/include/hal/sec_ll.h new file mode 100644 index 00000000000..626e6ecefac --- /dev/null +++ b/components/esp_hal_security/esp32s3/include/hal/sec_ll.h @@ -0,0 +1,26 @@ +/* + * SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include "soc/clk_tree_defs.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Select crypto clock source + * + * @note Not supported. No-op. + */ +static inline __attribute__((always_inline)) void sec_ll_crypto_clk_src_sel(soc_module_clk_t src) +{ + (void)src; +} + +#ifdef __cplusplus +} +#endif diff --git a/components/esp_hal_security/esp32s31/include/hal/sec_ll.h b/components/esp_hal_security/esp32s31/include/hal/sec_ll.h new file mode 100644 index 00000000000..dcbc400fe34 --- /dev/null +++ b/components/esp_hal_security/esp32s31/include/hal/sec_ll.h @@ -0,0 +1,39 @@ +/* + * SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#pragma once + +#include +#include "soc/clk_tree_defs.h" +#include "soc/hp_sys_clkrst_struct.h" +#include "hal/assert.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Select crypto clock source. + * + * @param src Clock source (SOC_MOD_CLK_XTAL, SOC_MOD_CLK_RC_FAST, or SOC_MOD_CLK_PLL_F240M) + */ +static inline __attribute__((always_inline)) void sec_ll_crypto_clk_src_sel(soc_module_clk_t src) +{ + uint32_t reg_val = 3; + if (src == SOC_MOD_CLK_XTAL) { + reg_val = 0; + } else if (src == SOC_MOD_CLK_RC_FAST) { + reg_val = 1; + } else if (src == SOC_MOD_CLK_PLL_F240M) { + reg_val = 2; + } else { + HAL_ASSERT(false); + } + HP_SYS_CLKRST.crypto_ctrl0.reg_crypto_clk_src_sel = reg_val; +} + +#ifdef __cplusplus +} +#endif diff --git a/components/esp_hal_timg/esp32s31/include/hal/timer_ll.h b/components/esp_hal_timg/esp32s31/include/hal/timer_ll.h index 54b07254130..010417360b8 100644 --- a/components/esp_hal_timg/esp32s31/include/hal/timer_ll.h +++ b/components/esp_hal_timg/esp32s31/include/hal/timer_ll.h @@ -104,7 +104,7 @@ static inline void _timer_ll_set_clock_source(int group_id, uint32_t timer_num, case GPTIMER_CLK_SRC_XTAL: clk_id = 0; break; - case GPTIMER_CLK_SRC_PLL_F80M: + case GPTIMER_CLK_SRC_REF_F80M: clk_id = 2; break; case GPTIMER_CLK_SRC_RC_FAST: diff --git a/components/esp_hal_twai/esp32s31/include/hal/twai_ll.h b/components/esp_hal_twai/esp32s31/include/hal/twai_ll.h index 541f75a3d19..5c77f76551b 100644 --- a/components/esp_hal_twai/esp32s31/include/hal/twai_ll.h +++ b/components/esp_hal_twai/esp32s31/include/hal/twai_ll.h @@ -167,7 +167,7 @@ static inline void twai_ll_set_clock_source(uint8_t twai_id, twai_clock_source_t case TWAI_CLK_SRC_XTAL: clk_sel = 0; break; - case TWAI_CLK_SRC_PLL_F80M: + case TWAI_CLK_SRC_REF_F80M: clk_sel = 2; break; default: diff --git a/components/esp_hal_uart/esp32s31/include/hal/uart_ll.h b/components/esp_hal_uart/esp32s31/include/hal/uart_ll.h index 381fb94f5d7..9a3ba9f486d 100644 --- a/components/esp_hal_uart/esp32s31/include/hal/uart_ll.h +++ b/components/esp_hal_uart/esp32s31/include/hal/uart_ll.h @@ -433,7 +433,7 @@ FORCE_INLINE_ATTR void uart_ll_set_sclk(uart_dev_t *hw, soc_module_clk_t source_ case UART_SCLK_RTC: sel_value = 1; break; - case UART_SCLK_PLL_F80M: + case UART_SCLK_REF_F80M: sel_value = 2; break; default: @@ -484,7 +484,7 @@ FORCE_INLINE_ATTR void uart_ll_get_sclk(uart_dev_t *hw, soc_module_clk_t *source *source_clk = (soc_module_clk_t)UART_SCLK_XTAL; break; case 2: - *source_clk = (soc_module_clk_t)UART_SCLK_PLL_F80M; + *source_clk = (soc_module_clk_t)UART_SCLK_REF_F80M; break; } } else { diff --git a/components/esp_hw_support/etm/esp_etm.c b/components/esp_hw_support/etm/esp_etm.c index 87a14f608ab..d09aba82cf2 100644 --- a/components/esp_hw_support/etm/esp_etm.c +++ b/components/esp_hw_support/etm/esp_etm.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2022-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -27,6 +27,7 @@ #include "esp_private/etm_interface.h" #include "esp_private/sleep_retention.h" #include "esp_private/critical_section.h" +#include "esp_private/esp_clk_tree_common.h" #define ETM_MEM_ALLOC_CAPS MALLOC_CAP_DEFAULT @@ -63,6 +64,9 @@ struct esp_etm_channel_t { _Atomic etm_chan_fsm_t fsm; // record ETM channel's driver state esp_etm_event_handle_t event; // which event is connect to the channel esp_etm_task_handle_t task; // which task is connect to the channel +#if ETM_LL_SUPPORT(CLOCK_SRC) + etm_clock_source_t clk_src; // function clock source enabled for this channel +#endif }; // ETM driver platform, it's always a singleton @@ -272,6 +276,8 @@ esp_err_t esp_etm_new_channel(const esp_etm_channel_config_t *config, esp_etm_ch if (clk_src == 0) { clk_src = ETM_CLK_SRC_DEFAULT; } + ESP_GOTO_ON_ERROR(esp_clk_tree_enable_src((soc_module_clk_t)clk_src, true), err, TAG, "clock source enable failed"); + chan->clk_src = clk_src; etm_ll_set_clock_source(group_id, clk_src); #endif @@ -290,6 +296,11 @@ esp_err_t esp_etm_new_channel(const esp_etm_channel_config_t *config, esp_etm_ch err: if (chan) { +#if ETM_LL_SUPPORT(CLOCK_SRC) + if (chan->clk_src != 0) { + esp_clk_tree_enable_src((soc_module_clk_t)chan->clk_src, false); + } +#endif etm_chan_destroy(chan); } return ret; @@ -310,6 +321,11 @@ esp_err_t esp_etm_del_channel(esp_etm_channel_handle_t chan) etm_ll_channel_set_task(group->hal.regs, chan_id, 0); ESP_LOGD(TAG, "del etm channel (%d,%d)", group_id, chan_id); +#if ETM_LL_SUPPORT(CLOCK_SRC) + // Back to hardware default clock selection, otherwise it might get stuck when stopping the bus during sleep process. + etm_ll_set_clock_source(group_id, ETM_CLK_SRC_XTAL); + ESP_RETURN_ON_ERROR(esp_clk_tree_enable_src((soc_module_clk_t)chan->clk_src, false), TAG, "clock source disable failed"); +#endif // recycle memory resource ESP_RETURN_ON_ERROR(etm_chan_destroy(chan), TAG, "destroy etm channel failed"); return ESP_OK; diff --git a/components/esp_hw_support/include/esp_private/esp_clk_tree_common.h b/components/esp_hw_support/include/esp_private/esp_clk_tree_common.h index c7b2a724341..f555b0ba801 100644 --- a/components/esp_hw_support/include/esp_private/esp_clk_tree_common.h +++ b/components/esp_hw_support/include/esp_private/esp_clk_tree_common.h @@ -124,6 +124,13 @@ bool esp_clk_tree_enable_power(soc_root_clk_circuit_t clk_circuit, bool enable); */ bool esp_clk_tree_is_power_on(soc_root_clk_circuit_t clk_circuit); +/** + * @brief Chip-specific root clock circuit power status (port/esp_clk_tree.c per target). + * + * Handles all soc_root_clk_circuit_t values except MPLL/APLL (those are in esp_clk_tree_common.c). + */ +bool esp_clk_tree_port_is_power_on(soc_root_clk_circuit_t clk_circuit); + #if SOC_CLK_APLL_SUPPORTED /** * @brief Enable APLL power if it has not enabled diff --git a/components/esp_hw_support/include/esp_private/esp_clk_tree_derived.h b/components/esp_hw_support/include/esp_private/esp_clk_tree_derived.h index b95db4df21f..63276638644 100644 --- a/components/esp_hw_support/include/esp_private/esp_clk_tree_derived.h +++ b/components/esp_hw_support/include/esp_private/esp_clk_tree_derived.h @@ -60,11 +60,13 @@ typedef struct { typedef struct { soc_module_clk_t clk_id; /*!< Module clock id this descriptor belongs to */ void (*set_src)(uint8_t mux_sel); /*!< Optional: program the upstream PLL mux. NULL when the clock has no mux (e.g. ESP32-P4 PLL_F50M is fixed to MPLL). */ - void (*set_divider)(uint32_t divider); /*!< Required: program the divider register (divider value, not the raw "div_num - 1" form). */ + void (*set_divider)(uint32_t divider); /*!< Optional: program the divider register (divider value, not div_num - 1). NULL when HW divider is fixed. */ void (*set_gate)(bool enable); /*!< Required: enable/disable the clock gate. */ const esp_clk_tree_derived_upstream_t *upstreams; /*!< Required: candidate upstream PLLs in preference order (used by both auto-pick and explicit-upstream paths). */ size_t upstream_count; /*!< Required: number of entries in `upstreams[]`. */ esp_clk_tree_derived_clk_state_t *state; /*!< Required: pointer to a statically-allocated mutable state slot owned by the target. Engine reads/writes ref_cnt / cur_upstream / cur_divider through this pointer. */ + esp_err_t (*acquire_parent)(void); /*!< Optional: power upstream (first acquire or after mux/div commit). Called with s_derived_clk_spinlock held.*/ + esp_err_t (*release_parent)(void); /*!< Optional: release upstream on last release. Called with s_derived_clk_spinlock held.*/ } esp_clk_tree_derived_clk_desc_t; /** diff --git a/components/esp_hw_support/linker.lf b/components/esp_hw_support/linker.lf index b374b643d5a..f9d16a2af72 100644 --- a/components/esp_hw_support/linker.lf +++ b/components/esp_hw_support/linker.lf @@ -13,12 +13,15 @@ entries: cpu: esp_cpu_compare_and_set (noflash) esp_memory_utils (noflash) clk_utils (noflash) - # TODO: PM-630 - if IDF_TARGET_ESP32S31 != y: - esp_clk_tree: esp_clk_tree_enable_src (noflash) - esp_clk_tree: esp_clk_tree_enable_power (noflash) - esp_clk_tree: esp_clk_tree_is_power_on (noflash) + esp_clk_tree: esp_clk_tree_enable_src (noflash) if RTC_CLK_FUNC_IN_IRAM = y: + esp_clk_tree: esp_clk_tree_enable_power (noflash) + esp_clk_tree_common:esp_clk_tree_is_power_on (noflash) + if SOC_CLK_MPLL_SUPPORTED = y: + esp_clk_tree_common:esp_clk_tree_mpll_release (noflash) + if SOC_CLK_APLL_SUPPORTED = y: + esp_clk_tree_common:esp_clk_tree_apll_acquire (noflash) + esp_clk_tree_common:esp_clk_tree_apll_release (noflash) rtc_clk (noflash) if IDF_TARGET_ESP32 = y: rtc_clk:rtc_clk_cpu_freq_to_pll_mhz (noflash) diff --git a/components/esp_hw_support/modem/port/esp32s31/modem_clock_impl.c b/components/esp_hw_support/modem/port/esp32s31/modem_clock_impl.c index 4a72739ce40..1ba77278696 100644 --- a/components/esp_hw_support/modem/port/esp32s31/modem_clock_impl.c +++ b/components/esp_hw_support/modem/port/esp32s31/modem_clock_impl.c @@ -6,6 +6,8 @@ #include "sdkconfig.h" #include "esp_attr.h" +#include "esp_check.h" +#include "esp_clk_tree.h" #include "soc/soc_caps.h" #include "modem/modem_clock_impl.h" #include "esp_private/regi2c_ctrl.h" @@ -212,7 +214,13 @@ static void IRAM_ATTR modem_clock_coex_configure(modem_clock_context_t *ctx, boo #if SOC_MODEM_CLOCK_SOC_PLL_SOURCE_CG_SUPPORTED static void IRAM_ATTR modem_clock_soc_pll_source_cg_configure(modem_clock_context_t *ctx, bool enable) { + if (enable) { + ESP_ERROR_CHECK(esp_clk_tree_enable_src(SOC_MOD_CLK_PLL_F160M, true)); + } modem_clock_hal_enable_soc_pll_source_cg(ctx->hal, enable); + if (!enable) { + ESP_ERROR_CHECK(esp_clk_tree_enable_src(SOC_MOD_CLK_PLL_F160M, false)); + } } #endif diff --git a/components/esp_hw_support/port/esp32/esp_clk_tree.c b/components/esp_hw_support/port/esp32/esp_clk_tree.c index 73eec5531e0..5bbdbee70f1 100644 --- a/components/esp_hw_support/port/esp32/esp_clk_tree.c +++ b/components/esp_hw_support/port/esp32/esp_clk_tree.c @@ -99,7 +99,7 @@ void esp_clk_tree_initialize(void) { } -bool esp_clk_tree_is_power_on(soc_root_clk_circuit_t clk_circuit) +bool esp_clk_tree_port_is_power_on(soc_root_clk_circuit_t clk_circuit) { (void)clk_circuit; return false; diff --git a/components/esp_hw_support/port/esp32c2/esp_clk_tree.c b/components/esp_hw_support/port/esp32c2/esp_clk_tree.c index d6919477c02..d1193434511 100644 --- a/components/esp_hw_support/port/esp32c2/esp_clk_tree.c +++ b/components/esp_hw_support/port/esp32c2/esp_clk_tree.c @@ -79,7 +79,7 @@ void esp_clk_tree_initialize(void) { } -bool esp_clk_tree_is_power_on(soc_root_clk_circuit_t clk_circuit) +bool esp_clk_tree_port_is_power_on(soc_root_clk_circuit_t clk_circuit) { (void)clk_circuit; return false; diff --git a/components/esp_hw_support/port/esp32c3/esp_clk_tree.c b/components/esp_hw_support/port/esp32c3/esp_clk_tree.c index 66e8d506f82..96db21dea84 100644 --- a/components/esp_hw_support/port/esp32c3/esp_clk_tree.c +++ b/components/esp_hw_support/port/esp32c3/esp_clk_tree.c @@ -79,7 +79,7 @@ void esp_clk_tree_initialize(void) { } -bool esp_clk_tree_is_power_on(soc_root_clk_circuit_t clk_circuit) +bool esp_clk_tree_port_is_power_on(soc_root_clk_circuit_t clk_circuit) { (void)clk_circuit; return false; diff --git a/components/esp_hw_support/port/esp32c5/esp_clk_tree.c b/components/esp_hw_support/port/esp32c5/esp_clk_tree.c index 8d602463923..83aba77a904 100644 --- a/components/esp_hw_support/port/esp32c5/esp_clk_tree.c +++ b/components/esp_hw_support/port/esp32c5/esp_clk_tree.c @@ -112,7 +112,7 @@ void esp_clk_tree_initialize(void) esp_clk_tree_initialized = true; } -bool esp_clk_tree_is_power_on(soc_root_clk_circuit_t clk_circuit) +bool esp_clk_tree_port_is_power_on(soc_root_clk_circuit_t clk_circuit) { (void)clk_circuit; return false; diff --git a/components/esp_hw_support/port/esp32c6/esp_clk_tree.c b/components/esp_hw_support/port/esp32c6/esp_clk_tree.c index 4aa62f33762..d4edaf63742 100644 --- a/components/esp_hw_support/port/esp32c6/esp_clk_tree.c +++ b/components/esp_hw_support/port/esp32c6/esp_clk_tree.c @@ -79,7 +79,7 @@ void esp_clk_tree_initialize(void) { } -bool esp_clk_tree_is_power_on(soc_root_clk_circuit_t clk_circuit) +bool esp_clk_tree_port_is_power_on(soc_root_clk_circuit_t clk_circuit) { (void)clk_circuit; return false; diff --git a/components/esp_hw_support/port/esp32c61/esp_clk_tree.c b/components/esp_hw_support/port/esp32c61/esp_clk_tree.c index a2f9f86f430..01a6ae4d324 100644 --- a/components/esp_hw_support/port/esp32c61/esp_clk_tree.c +++ b/components/esp_hw_support/port/esp32c61/esp_clk_tree.c @@ -79,7 +79,7 @@ void esp_clk_tree_initialize(void) { } -bool esp_clk_tree_is_power_on(soc_root_clk_circuit_t clk_circuit) +bool esp_clk_tree_port_is_power_on(soc_root_clk_circuit_t clk_circuit) { (void)clk_circuit; return false; diff --git a/components/esp_hw_support/port/esp32h2/esp_clk_tree.c b/components/esp_hw_support/port/esp32h2/esp_clk_tree.c index dd3a800d919..74e372b0811 100644 --- a/components/esp_hw_support/port/esp32h2/esp_clk_tree.c +++ b/components/esp_hw_support/port/esp32h2/esp_clk_tree.c @@ -76,7 +76,7 @@ void esp_clk_tree_initialize(void) { } -bool esp_clk_tree_is_power_on(soc_root_clk_circuit_t clk_circuit) +bool esp_clk_tree_port_is_power_on(soc_root_clk_circuit_t clk_circuit) { (void)clk_circuit; return false; diff --git a/components/esp_hw_support/port/esp32h21/esp_clk_tree.c b/components/esp_hw_support/port/esp32h21/esp_clk_tree.c index 3e4fe553c07..b06f0bb66db 100644 --- a/components/esp_hw_support/port/esp32h21/esp_clk_tree.c +++ b/components/esp_hw_support/port/esp32h21/esp_clk_tree.c @@ -90,15 +90,13 @@ void esp_clk_tree_initialize(void) // PLL_F64M ++ for MSPI } -bool esp_clk_tree_is_power_on(soc_root_clk_circuit_t clk_circuit) +bool esp_clk_tree_port_is_power_on(soc_root_clk_circuit_t clk_circuit) { - switch (clk_circuit) { - case SOC_ROOT_CIRCUIT_CLK_XTAL_X2: + if (clk_circuit == SOC_ROOT_CIRCUIT_CLK_XTAL_X2) { return s_xtal_x2_ref_cnt > 0; - case SOC_ROOT_CIRCUIT_CLK_BBPLL: + } + if (clk_circuit == SOC_ROOT_CIRCUIT_CLK_BBPLL) { return s_bbpll_ref_cnt > 0; - default: - break; } return false; } diff --git a/components/esp_hw_support/port/esp32h4/esp_clk_tree.c b/components/esp_hw_support/port/esp32h4/esp_clk_tree.c index 638531c833f..c58a183f8b6 100644 --- a/components/esp_hw_support/port/esp32h4/esp_clk_tree.c +++ b/components/esp_hw_support/port/esp32h4/esp_clk_tree.c @@ -92,15 +92,13 @@ void esp_clk_tree_initialize(void) // PLL_F64M ++ for MSPI } -bool esp_clk_tree_is_power_on(soc_root_clk_circuit_t clk_circuit) +bool esp_clk_tree_port_is_power_on(soc_root_clk_circuit_t clk_circuit) { - switch (clk_circuit) { - case SOC_ROOT_CIRCUIT_CLK_XTAL_X2: + if (clk_circuit == SOC_ROOT_CIRCUIT_CLK_XTAL_X2) { return s_xtal_x2_ref_cnt > 0; - case SOC_ROOT_CIRCUIT_CLK_BBPLL: + } + if (clk_circuit == SOC_ROOT_CIRCUIT_CLK_BBPLL) { return s_bbpll_ref_cnt > 0; - default: - break; } return false; } diff --git a/components/esp_hw_support/port/esp32p4/esp_clk_tree.c b/components/esp_hw_support/port/esp32p4/esp_clk_tree.c index 8a4016cbd0d..9e202c67802 100644 --- a/components/esp_hw_support/port/esp32p4/esp_clk_tree.c +++ b/components/esp_hw_support/port/esp32p4/esp_clk_tree.c @@ -5,9 +5,9 @@ */ #include -#include #include "sdkconfig.h" #include "esp_clk_tree.h" +#include "esp_attr.h" #include "esp_err.h" #include "esp_check.h" #include "esp_log.h" @@ -21,6 +21,7 @@ #include "esp_private/esp_clk_tree_common.h" #include "esp_private/esp_clk_tree_derived.h" #include "esp_private/periph_ctrl.h" +#include "esp_private/critical_section.h" ESP_LOG_ATTR_TAG(TAG, "esp_clk_tree"); @@ -166,8 +167,12 @@ esp_err_t esp_clk_tree_src_set_freq_hz(soc_module_clk_t clk_src, uint32_t expt_f return ret; } -static _Atomic int16_t s_pll_src_cg_ref_cnt[SOC_MOD_CLK_INVALID] = { 0 }; -static bool esp_clk_tree_initialized = false; +DEFINE_CRIT_SECTION_LOCK_STATIC(s_clk_tree_spinlock); + +/** Per soc_module_clk_t: record clock gate consumers */ +static int16_t s_mod_clk_gate_ref_cnt[SOC_MOD_CLK_INVALID] = { 0 }; + +static bool s_clk_tree_initialized = false; void esp_clk_tree_initialize(void) { @@ -175,7 +180,7 @@ void esp_clk_tree_initialize(void) if ((rst_reason == RESET_REASON_CPU_SW) || (rst_reason == RESET_REASON_CPU_MWDT) \ || (rst_reason == RESET_REASON_CPU_RWDT) || (rst_reason == RESET_REASON_CPU_JTAG) \ || (rst_reason == RESET_REASON_CPU_LOCKUP)) { - esp_clk_tree_initialized = true; + s_clk_tree_initialized = true; return; } @@ -186,10 +191,10 @@ void esp_clk_tree_initialize(void) _clk_gate_ll_ref_120m_clk_en(false); _clk_gate_ll_ref_160m_clk_en(false); _clk_gate_ll_ref_240m_clk_en(false); - esp_clk_tree_initialized = true; + s_clk_tree_initialized = true; } -bool esp_clk_tree_is_power_on(soc_root_clk_circuit_t clk_circuit) +bool esp_clk_tree_port_is_power_on(soc_root_clk_circuit_t clk_circuit) { (void)clk_circuit; return false; @@ -201,74 +206,126 @@ bool esp_clk_tree_enable_power(soc_root_clk_circuit_t clk_circuit, bool enable) return false; // TODO: PM-653 } -#define ENABLE_CLK_GATE(clk_src_en_func, enable) \ - PERIPH_RCC_ATOMIC() { \ - clk_src_en_func(enable); \ +/* -------------------------------------------------------------------------- */ +/* Fixed ref clocks: gate only (no parent power management on ESP32-P4) */ +/* -------------------------------------------------------------------------- */ + +typedef void (*esp_clk_tree_gate_fn_t)(bool enable); + +typedef struct { + soc_module_clk_t clk_id; + esp_clk_tree_gate_fn_t set_gate; +} esp_clk_tree_gated_clk_t; + +static void esp_clk_tree_gate_rc_fast(bool enable) +{ + if (enable) { + rtc_dig_clk8m_enable(); + } else { + rtc_dig_clk8m_disable(); } +} + +typedef enum { + ESP_CLK_TREE_GATED_CLK_RC_FAST, + ESP_CLK_TREE_GATED_CLK_PLL_F20M, + ESP_CLK_TREE_GATED_CLK_PLL_F25M, + ESP_CLK_TREE_GATED_CLK_PLL_F80M, + ESP_CLK_TREE_GATED_CLK_PLL_F120M, + ESP_CLK_TREE_GATED_CLK_PLL_F160M, + ESP_CLK_TREE_GATED_CLK_PLL_F240M, + ESP_CLK_TREE_GATED_CLK_NUM, +} esp_clk_tree_gated_clk_id_t; + +static const esp_clk_tree_gated_clk_t s_gated_ref_clks[] = { + [ESP_CLK_TREE_GATED_CLK_RC_FAST] = { SOC_MOD_CLK_RC_FAST, esp_clk_tree_gate_rc_fast }, + [ESP_CLK_TREE_GATED_CLK_PLL_F20M] = { SOC_MOD_CLK_PLL_F20M, _clk_gate_ll_ref_20m_clk_en }, + [ESP_CLK_TREE_GATED_CLK_PLL_F25M] = { SOC_MOD_CLK_PLL_F25M, _clk_gate_ll_ref_25m_clk_en }, + [ESP_CLK_TREE_GATED_CLK_PLL_F80M] = { SOC_MOD_CLK_PLL_F80M, _clk_gate_ll_ref_80m_clk_en }, + [ESP_CLK_TREE_GATED_CLK_PLL_F120M] = { SOC_MOD_CLK_PLL_F120M, _clk_gate_ll_ref_120m_clk_en }, + [ESP_CLK_TREE_GATED_CLK_PLL_F160M] = { SOC_MOD_CLK_PLL_F160M, _clk_gate_ll_ref_160m_clk_en }, + [ESP_CLK_TREE_GATED_CLK_PLL_F240M] = { SOC_MOD_CLK_PLL_F240M, _clk_gate_ll_ref_240m_clk_en }, +}; + +#define ENABLE_CLK_GATE(clk_src_en_func, enable) \ + do { \ + if ((clk_src_en_func) != NULL) { \ + PERIPH_RCC_ATOMIC() { \ + (clk_src_en_func)(enable); \ + }; \ + } \ + } while (0) + +FORCE_INLINE_ATTR esp_err_t esp_clk_tree_enable_gated_clk(const esp_clk_tree_gated_clk_t *entry, bool enable) +{ + int16_t prev_ref_cnt; + + esp_os_enter_critical(&s_clk_tree_spinlock); + if (enable) { + prev_ref_cnt = s_mod_clk_gate_ref_cnt[entry->clk_id]++; + } else { + prev_ref_cnt = s_mod_clk_gate_ref_cnt[entry->clk_id]--; + if (prev_ref_cnt <= 0) { + s_mod_clk_gate_ref_cnt[entry->clk_id] = 0; + esp_os_exit_critical(&s_clk_tree_spinlock); + ESP_EARLY_LOGW(TAG, "soc_module_clk_t %d disabled multiple times!!", entry->clk_id); + return ESP_OK; + } + } + esp_os_exit_critical(&s_clk_tree_spinlock); + + if (prev_ref_cnt == 0 && enable) { + ENABLE_CLK_GATE(entry->set_gate, true); + } else if (prev_ref_cnt == 1 && !enable) { + ENABLE_CLK_GATE(entry->set_gate, false); + } + return ESP_OK; +} esp_err_t esp_clk_tree_enable_src(soc_module_clk_t clk_src, bool enable) { - if (clk_src < 1 || clk_src >= SOC_MOD_CLK_INVALID) { - // some conditions is legal, e.g. -1 means external clock source + if (clk_src < 1 || clk_src >= SOC_MOD_CLK_INVALID || clk_src == SOC_MOD_CLK_XTAL) { + /* Not managed by esp_clk_tree */ return ESP_OK; } - if (!esp_clk_tree_initialized) { + if (!s_clk_tree_initialized) { return ESP_OK; } - // Derived PLL clocks (PLL_F50M, ...) that participate in the shared - // refcount/lock engine route through that engine instead of the - // global s_pll_src_cg_ref_cnt array below. - if (esp_clk_tree_get_derived_clk_desc(clk_src) != NULL) { - return enable ? esp_clk_tree_derived_clk_acquire(clk_src) - : esp_clk_tree_derived_clk_release(clk_src); - } - + esp_clk_tree_gated_clk_id_t gated_clk_id; // these clock sources have their own reference counting switch (clk_src) { - case SOC_MOD_CLK_APLL: - if (enable) { - esp_clk_tree_apll_acquire(); - } else { - esp_clk_tree_apll_release(); - } - return ESP_OK; - case SOC_MOD_CLK_MPLL: - if (enable) { - return esp_clk_tree_mpll_acquire(); - } else { - esp_clk_tree_mpll_release(); - } - return ESP_OK; - default: - break; - } - - // other clock sources use the global reference counting - int16_t prev_ref_cnt = 0; - if (enable) { - prev_ref_cnt = atomic_fetch_add(&s_pll_src_cg_ref_cnt[clk_src], 1); - } else { - prev_ref_cnt = atomic_fetch_sub(&s_pll_src_cg_ref_cnt[clk_src], 1); - if (prev_ref_cnt <= 0) { - ESP_EARLY_LOGW(TAG, "soc_module_clk_t %d disabled multiple times!!", clk_src); - atomic_store(&s_pll_src_cg_ref_cnt[clk_src], 0); + case SOC_MOD_CLK_APLL: + if (enable) { + esp_clk_tree_apll_acquire(); + } else { + esp_clk_tree_apll_release(); + } + return ESP_OK; + case SOC_MOD_CLK_MPLL: + if (enable) { + return esp_clk_tree_mpll_acquire(); + } else { + esp_clk_tree_mpll_release(); return ESP_OK; } - } - if ((prev_ref_cnt == 0 && enable) || (prev_ref_cnt == 1 && !enable)) { - switch (clk_src) { - case SOC_MOD_CLK_RC_FAST: enable ? rtc_dig_clk8m_enable() : rtc_dig_clk8m_disable(); break; - case SOC_MOD_CLK_PLL_F20M: ENABLE_CLK_GATE(clk_gate_ll_ref_20m_clk_en, enable); break; - case SOC_MOD_CLK_PLL_F25M: ENABLE_CLK_GATE(clk_gate_ll_ref_25m_clk_en, enable); break; - case SOC_MOD_CLK_PLL_F80M: ENABLE_CLK_GATE(clk_gate_ll_ref_80m_clk_en, enable); break; - case SOC_MOD_CLK_PLL_F120M: ENABLE_CLK_GATE(clk_gate_ll_ref_120m_clk_en, enable); break; - case SOC_MOD_CLK_PLL_F160M: ENABLE_CLK_GATE(clk_gate_ll_ref_160m_clk_en, enable); break; - case SOC_MOD_CLK_PLL_F240M: ENABLE_CLK_GATE(clk_gate_ll_ref_240m_clk_en, enable); break; - default: break; + case SOC_MOD_CLK_RC_FAST: gated_clk_id = ESP_CLK_TREE_GATED_CLK_RC_FAST; break; + case SOC_MOD_CLK_PLL_F20M: gated_clk_id = ESP_CLK_TREE_GATED_CLK_PLL_F20M; break; + case SOC_MOD_CLK_PLL_F25M: gated_clk_id = ESP_CLK_TREE_GATED_CLK_PLL_F25M; break; + case SOC_MOD_CLK_PLL_F80M: gated_clk_id = ESP_CLK_TREE_GATED_CLK_PLL_F80M; break; + case SOC_MOD_CLK_PLL_F120M: gated_clk_id = ESP_CLK_TREE_GATED_CLK_PLL_F120M; break; + case SOC_MOD_CLK_PLL_F160M: gated_clk_id = ESP_CLK_TREE_GATED_CLK_PLL_F160M; break; + case SOC_MOD_CLK_PLL_F240M: gated_clk_id = ESP_CLK_TREE_GATED_CLK_PLL_F240M; break; + default: + // Derived PLL clocks (PLL_F50M, ...) that participate in the shared + // refcount/lock engine route through that engine instead of the + // global s_pll_src_cg_ref_cnt array below. + if (esp_clk_tree_get_derived_clk_desc(clk_src) != NULL) { + return enable ? esp_clk_tree_derived_clk_acquire(clk_src) + : esp_clk_tree_derived_clk_release(clk_src); } + return ESP_OK; } - - return ESP_OK; + return esp_clk_tree_enable_gated_clk(&s_gated_ref_clks[gated_clk_id], enable); } diff --git a/components/esp_hw_support/port/esp32s2/esp_clk_tree.c b/components/esp_hw_support/port/esp32s2/esp_clk_tree.c index 6bb4ec4f122..a6633e5e6da 100644 --- a/components/esp_hw_support/port/esp32s2/esp_clk_tree.c +++ b/components/esp_hw_support/port/esp32s2/esp_clk_tree.c @@ -97,7 +97,7 @@ void esp_clk_tree_initialize(void) { } -bool esp_clk_tree_is_power_on(soc_root_clk_circuit_t clk_circuit) +bool esp_clk_tree_port_is_power_on(soc_root_clk_circuit_t clk_circuit) { (void)clk_circuit; return false; diff --git a/components/esp_hw_support/port/esp32s3/esp_clk_tree.c b/components/esp_hw_support/port/esp32s3/esp_clk_tree.c index efe7430ea6c..c756d99e6d8 100644 --- a/components/esp_hw_support/port/esp32s3/esp_clk_tree.c +++ b/components/esp_hw_support/port/esp32s3/esp_clk_tree.c @@ -89,7 +89,7 @@ void esp_clk_tree_initialize(void) { } -bool esp_clk_tree_is_power_on(soc_root_clk_circuit_t clk_circuit) +bool esp_clk_tree_port_is_power_on(soc_root_clk_circuit_t clk_circuit) { (void)clk_circuit; return false; diff --git a/components/esp_hw_support/port/esp32s31/esp_clk_tree.c b/components/esp_hw_support/port/esp32s31/esp_clk_tree.c index fb95c7c93e9..6387311983b 100644 --- a/components/esp_hw_support/port/esp32s31/esp_clk_tree.c +++ b/components/esp_hw_support/port/esp32s31/esp_clk_tree.c @@ -5,59 +5,316 @@ */ #include -#include -#include "sdkconfig.h" +#include #include "esp_clk_tree.h" +#include "esp_attr.h" #include "esp_err.h" #include "esp_check.h" #include "esp_log.h" -#include "soc/clk_tree_defs.h" +#include "esp_rom_sys.h" #include "soc/rtc.h" #include "soc/reset_reasons.h" -#include "soc/soc_caps.h" #include "hal/clk_gate_ll.h" #include "hal/clk_tree_hal.h" #include "hal/clk_tree_ll.h" #include "esp_private/esp_clk_tree_common.h" #include "esp_private/esp_clk_tree_derived.h" #include "esp_private/periph_ctrl.h" +#include "esp_private/critical_section.h" ESP_LOG_ATTR_TAG(TAG, "esp_clk_tree"); +/* -------------------------------------------------------------------------- */ +/* Derived clocks: configurable divider and/or upstream mux + multi-user lock */ +/* -------------------------------------------------------------------------- */ + +enum { + ESP_CLK_TREE_DERIVED_PLL_F25M = 0, + ESP_CLK_TREE_DERIVED_PLL_F50M, + ESP_CLK_TREE_DERIVED_REF_F80M, + ESP_CLK_TREE_DERIVED_PLL_NUM, +}; + +static esp_clk_tree_derived_clk_state_t s_derived_pll_states[ESP_CLK_TREE_DERIVED_PLL_NUM]; + +static int8_t s_ref_500m_committed_mux = -1; + +/** + * Power ref_25m/ref_50m shared upstream (ref_500m_sel: 0 = CPLL, 1 = MPLL). + * @param mux_sel 0 or 1; values < 0 are ignored. + */ +static esp_err_t esp_clk_tree_ref_500m_parent_power(int8_t mux_sel, bool enable) +{ + if (mux_sel < 0) { + return ESP_OK; + } + if (mux_sel == 0) { + esp_clk_tree_enable_power(SOC_ROOT_CIRCUIT_CLK_CPLL, enable); + return ESP_OK; + } + if (enable) { + return esp_clk_tree_mpll_acquire(); + } + esp_clk_tree_mpll_release(); + return ESP_OK; +} + +/** + * Shared ref_500m_sel: PLL_F25M and PLL_F50M must use the same upstream when both are on. + */ +static void esp_clk_tree_ref_500m_set_src(uint8_t mux_sel) +{ + if (s_derived_pll_states[ESP_CLK_TREE_DERIVED_PLL_F25M].ref_cnt > 0 + && s_derived_pll_states[ESP_CLK_TREE_DERIVED_PLL_F50M].ref_cnt > 0 + && s_ref_500m_committed_mux >= 0) { + assert(mux_sel == (uint8_t)s_ref_500m_committed_mux); + } + clk_ll_ref_500m_set_src(mux_sel); +} + +static esp_err_t esp_clk_tree_ref_500m_derived_acquire_parent(void) +{ + int8_t mux = (int8_t)clk_ll_ref_500m_get_src(); + if (mux == s_ref_500m_committed_mux) { + return ESP_OK; + } + if (s_derived_pll_states[ESP_CLK_TREE_DERIVED_PLL_F25M].ref_cnt > 0 + && s_derived_pll_states[ESP_CLK_TREE_DERIVED_PLL_F50M].ref_cnt > 0 + && s_ref_500m_committed_mux >= 0) { + assert(mux == s_ref_500m_committed_mux); + } + esp_clk_tree_ref_500m_parent_power(s_ref_500m_committed_mux, false); + esp_err_t ret = esp_clk_tree_ref_500m_parent_power(mux, true); + if (ret != ESP_OK) { + esp_clk_tree_ref_500m_parent_power(s_ref_500m_committed_mux, true); + return ret; + } + s_ref_500m_committed_mux = mux; + return ESP_OK; +} + +static esp_err_t esp_clk_tree_ref_500m_derived_release_parent(void) +{ + if (s_derived_pll_states[ESP_CLK_TREE_DERIVED_PLL_F25M].ref_cnt > 0 + || s_derived_pll_states[ESP_CLK_TREE_DERIVED_PLL_F50M].ref_cnt > 0) { + return ESP_OK; + } + esp_clk_tree_ref_500m_parent_power(s_ref_500m_committed_mux, false); + s_ref_500m_committed_mux = -1; + return ESP_OK; +} + +/** F80M parent path committed at first enable: 0 = BBPLL, 1 = XTALx2 (-1 = none). */ +static int8_t s_ref_80m_committed_sel = -1; + +/** + * REF_F80M enable-time source policy: + * 1) If BBPLL is already on → BBPLL/6 path + one more BBPLL power user. + * 2) Else → power XTALx2 and select ref_80m via clk_ll_ref_80m_set_src(1). + */ +static esp_err_t esp_clk_tree_ref_80m_derived_acquire_parent(void) +{ + if (s_ref_80m_committed_sel >= 0) { + return ESP_OK; + } + + _clk_gate_ll_ref_80m_mux_clk_en(true); + if (esp_clk_tree_port_is_power_on(SOC_ROOT_CIRCUIT_CLK_BBPLL)) { + esp_clk_tree_enable_power(SOC_ROOT_CIRCUIT_CLK_BBPLL, true); + clk_ll_ref_80m_set_src(0); + s_ref_80m_committed_sel = 0; + } else { + esp_clk_tree_enable_power(SOC_ROOT_CIRCUIT_CLK_XTAL_X2, true); + clk_ll_ref_80m_set_src(1); + s_ref_80m_committed_sel = 1; + } + return ESP_OK; +} + +static esp_err_t esp_clk_tree_ref_80m_derived_release_parent(void) +{ + if (s_derived_pll_states[ESP_CLK_TREE_DERIVED_REF_F80M].ref_cnt > 0) { + return ESP_OK; + } + if (s_ref_80m_committed_sel == 0) { + esp_clk_tree_enable_power(SOC_ROOT_CIRCUIT_CLK_BBPLL, false); + } else if (s_ref_80m_committed_sel == 1) { + esp_clk_tree_enable_power(SOC_ROOT_CIRCUIT_CLK_XTAL_X2, false); + } + _clk_gate_ll_ref_80m_mux_clk_en(false); + s_ref_80m_committed_sel = -1; + return ESP_OK; +} + // Allowed upstreams for PLL_F50M, in preference order (used by both auto-pick // and explicit-upstream paths). Mux selectors match the HP_SYS_CLKRST -// `reg_ref_500m_sel` field: 0 = CPLL, 1 = MPLL. -static const esp_clk_tree_derived_upstream_t s_pll_f50m_upstreams[] = { +// `reg_ref_500m_sel` field: 0 = CPLL, 1 = MPLL. (shared by PLL_F25M and PLL_F50M). +static const esp_clk_tree_derived_upstream_t s_ref_500m_upstreams[] = { { SOC_MOD_CLK_CPLL, 0 }, { SOC_MOD_CLK_MPLL, 1 }, }; -static esp_clk_tree_derived_clk_state_t s_pll_f50m_state = { - .ref_cnt = 0, - .cur_upstream = SOC_MOD_CLK_INVALID, - .cur_divider = 0, -}; - -static const esp_clk_tree_derived_clk_desc_t s_pll_f50m_desc = { - .clk_id = SOC_MOD_CLK_PLL_F50M, - .set_src = clk_ll_ref_500m_set_src, - .set_divider = clk_ll_pll_f50m_set_divider, - .set_gate = _clk_gate_ll_ref_50m_clk_en, // using RCC_ATOMIC lock free function version to avoid nesting critical sections - .upstreams = s_pll_f50m_upstreams, - .upstream_count = sizeof(s_pll_f50m_upstreams) / sizeof(s_pll_f50m_upstreams[0]), - .state = &s_pll_f50m_state, +static const esp_clk_tree_derived_clk_desc_t s_derived_pll_descs[ESP_CLK_TREE_DERIVED_PLL_NUM] = { + [ESP_CLK_TREE_DERIVED_PLL_F25M] = { + .clk_id = SOC_MOD_CLK_PLL_F25M, + .set_src = esp_clk_tree_ref_500m_set_src, + .set_divider = clk_ll_pll_f25m_set_divider, + .set_gate = _clk_gate_ll_ref_25m_clk_en, + .upstreams = s_ref_500m_upstreams, + .upstream_count = sizeof(s_ref_500m_upstreams) / sizeof(s_ref_500m_upstreams[0]), + .state = &s_derived_pll_states[ESP_CLK_TREE_DERIVED_PLL_F25M], + .acquire_parent = esp_clk_tree_ref_500m_derived_acquire_parent, + .release_parent = esp_clk_tree_ref_500m_derived_release_parent, + }, + [ESP_CLK_TREE_DERIVED_PLL_F50M] = { + .clk_id = SOC_MOD_CLK_PLL_F50M, + .set_src = esp_clk_tree_ref_500m_set_src, + .set_divider = clk_ll_pll_f50m_set_divider, + .set_gate = _clk_gate_ll_ref_50m_clk_en, + .upstreams = s_ref_500m_upstreams, + .upstream_count = sizeof(s_ref_500m_upstreams) / sizeof(s_ref_500m_upstreams[0]), + .state = &s_derived_pll_states[ESP_CLK_TREE_DERIVED_PLL_F50M], + .acquire_parent = esp_clk_tree_ref_500m_derived_acquire_parent, + .release_parent = esp_clk_tree_ref_500m_derived_release_parent, + }, + [ESP_CLK_TREE_DERIVED_REF_F80M] = { + .clk_id = SOC_MOD_CLK_REF_F80M, + .set_src = NULL, + .set_divider = NULL, + .set_gate = _clk_gate_ll_ref_80m_clk_en, + .upstreams = NULL, + .upstream_count = 0, + .state = &s_derived_pll_states[ESP_CLK_TREE_DERIVED_REF_F80M], + .acquire_parent = esp_clk_tree_ref_80m_derived_acquire_parent, + .release_parent = esp_clk_tree_ref_80m_derived_release_parent, + }, }; const esp_clk_tree_derived_clk_desc_t *esp_clk_tree_get_derived_clk_desc(soc_module_clk_t clk_src) { switch (clk_src) { + case SOC_MOD_CLK_PLL_F25M: + return &s_derived_pll_descs[ESP_CLK_TREE_DERIVED_PLL_F25M]; case SOC_MOD_CLK_PLL_F50M: - return &s_pll_f50m_desc; + return &s_derived_pll_descs[ESP_CLK_TREE_DERIVED_PLL_F50M]; + case SOC_MOD_CLK_REF_F80M: + return &s_derived_pll_descs[ESP_CLK_TREE_DERIVED_REF_F80M]; default: return NULL; } } +/* -------------------------------------------------------------------------- */ +/* Fixed ref clocks: gate + static BBPLL parent only */ +/* -------------------------------------------------------------------------- */ + +typedef void (*esp_clk_tree_gate_fn_t)(bool enable); +typedef void (*esp_clk_tree_parent_fn_t)(bool enable); + +typedef struct { + soc_module_clk_t clk_id; + esp_clk_tree_gate_fn_t set_gate; + esp_clk_tree_parent_fn_t parent_power; +} esp_clk_tree_gated_clk_t; + +static void esp_clk_tree_parent_bbpll(bool enable) +{ + esp_clk_tree_enable_power(SOC_ROOT_CIRCUIT_CLK_BBPLL, enable); +} + +static void esp_clk_tree_parent_rc_fast(bool enable) +{ + if (enable) { + rtc_dig_clk8m_enable(); + } else { + rtc_dig_clk8m_disable(); + } +} + +DEFINE_CRIT_SECTION_LOCK_STATIC(s_clk_tree_spinlock); + +/** Per soc_module_clk_t: record clock gate consumers */ +static int16_t s_mod_clk_gate_ref_cnt[SOC_MOD_CLK_INVALID] = { 0 }; + +/** Per soc_root_clk_circuit_t: record clock power consumers */ +static int16_t s_root_pll_power_ref_cnt[SOC_ROOT_CIRCUIT_CLK_MAX] = { 0 }; + +static bool s_clk_tree_initialized = false; + +static int16_t esp_clk_tree_root_pll_power_acquire(soc_root_clk_circuit_t clk_circuit) +{ + int16_t prev; + + assert(clk_circuit == SOC_ROOT_CIRCUIT_CLK_BBPLL || clk_circuit == SOC_ROOT_CIRCUIT_CLK_CPLL + || clk_circuit == SOC_ROOT_CIRCUIT_CLK_XTAL_X2); + + esp_os_enter_critical(&s_clk_tree_spinlock); + prev = s_root_pll_power_ref_cnt[clk_circuit]++; + if (prev == 0) { + switch (clk_circuit) { + case SOC_ROOT_CIRCUIT_CLK_BBPLL: + clk_ll_bbpll_enable(); + break; + case SOC_ROOT_CIRCUIT_CLK_CPLL: + clk_ll_cpll_enable(); + break; + case SOC_ROOT_CIRCUIT_CLK_XTAL_X2: + clk_ll_xtalx2_enable(); + break; + default: + break; + } + } + esp_os_exit_critical(&s_clk_tree_spinlock); + return prev; +} + +static int16_t esp_clk_tree_root_pll_power_release(soc_root_clk_circuit_t clk_circuit) +{ + int16_t prev; + + assert(clk_circuit == SOC_ROOT_CIRCUIT_CLK_BBPLL || clk_circuit == SOC_ROOT_CIRCUIT_CLK_CPLL + || clk_circuit == SOC_ROOT_CIRCUIT_CLK_XTAL_X2); + + esp_os_enter_critical(&s_clk_tree_spinlock); + prev = s_root_pll_power_ref_cnt[clk_circuit]; + if (prev <= 0) { + esp_os_exit_critical(&s_clk_tree_spinlock); + ESP_EARLY_LOGW(TAG, "soc_root_clk_circuit_t %d disabled multiple times!!", clk_circuit); + return prev; + } + s_root_pll_power_ref_cnt[clk_circuit] = prev - 1; + if (prev == 1) { + switch (clk_circuit) { + case SOC_ROOT_CIRCUIT_CLK_BBPLL: + clk_ll_bbpll_disable(); + break; + case SOC_ROOT_CIRCUIT_CLK_CPLL: + clk_ll_cpll_disable(); + break; + case SOC_ROOT_CIRCUIT_CLK_XTAL_X2: + clk_ll_xtalx2_disable(); + break; + default: + break; + } + } + esp_os_exit_critical(&s_clk_tree_spinlock); + return prev; +} + +static uint32_t esp_clk_tree_ref_500m_pll_get_freq_hz(uint32_t div_num) +{ + uint32_t up_hz; + + if (clk_ll_ref_500m_get_src() == 0) { + up_hz = clk_ll_cpll_get_freq_mhz(clk_hal_xtal_get_freq_mhz()) * MHZ; + } else { + up_hz = clk_ll_mpll_get_freq_mhz(clk_hal_xtal_get_freq_mhz()) * MHZ; + } + return up_hz / div_num; +} + esp_err_t esp_clk_tree_src_get_freq_hz(soc_module_clk_t clk_src, esp_clk_tree_src_freq_precision_t precision, uint32_t *freq_value) { @@ -79,9 +336,21 @@ esp_err_t esp_clk_tree_src_get_freq_hz(soc_module_clk_t clk_src, esp_clk_tree_sr case SOC_MOD_CLK_PLL_F20M: clk_src_freq = CLK_LL_PLL_480M_FREQ_MHZ / clk_ll_pll_f20m_get_divider() * MHZ; break; - case SOC_MOD_CLK_PLL_F80M: + case SOC_MOD_CLK_PLL_F25M: + clk_src_freq = esp_clk_tree_ref_500m_pll_get_freq_hz(clk_ll_pll_f25m_get_divider()); + break; + case SOC_MOD_CLK_PLL_F50M: + clk_src_freq = esp_clk_tree_ref_500m_pll_get_freq_hz(clk_ll_pll_f50m_get_divider()); + break; + case SOC_MOD_CLK_PLL_F60M: + clk_src_freq = CLK_LL_PLL_60M_FREQ_MHZ * MHZ; + break; + case SOC_MOD_CLK_REF_F80M: clk_src_freq = CLK_LL_PLL_80M_FREQ_MHZ * MHZ; break; + case SOC_MOD_CLK_PLL_F120M: + clk_src_freq = CLK_LL_PLL_120M_FREQ_MHZ * MHZ; + break; case SOC_MOD_CLK_PLL_F160M: clk_src_freq = CLK_LL_PLL_160M_FREQ_MHZ * MHZ; break; @@ -159,81 +428,159 @@ esp_err_t esp_clk_tree_src_set_freq_hz(soc_module_clk_t clk_src, uint32_t expt_f return ret; } -static _Atomic int16_t s_pll_src_cg_ref_cnt[SOC_MOD_CLK_INVALID] = { 0 }; -static bool s_clk_tree_initialized = false; -static int16_t s_cpll_ref_cnt = 0; - void esp_clk_tree_initialize(void) { - // TODO: IDF-15502 - /*soc_reset_reason_t rst_reason = esp_rom_get_reset_reason(0); - if ((rst_reason == RESET_REASON_CPU_SW) || (rst_reason == RESET_REASON_CPU_MWDT) \ - || (rst_reason == RESET_REASON_CPU_RWDT) || (rst_reason == RESET_REASON_CPU_JTAG) \ - || (rst_reason == RESET_REASON_CPU_LOCKUP)) { + soc_reset_reason_t rst_reason = esp_rom_get_reset_reason(0); + if ((rst_reason == RESET_REASON_CPU_SW) || (rst_reason == RESET_REASON_CPU_MWDT) || + (rst_reason == RESET_REASON_CPU_RWDT) || (rst_reason == RESET_REASON_CPU_JTAG) || + (rst_reason == RESET_REASON_CPU_LOCKUP)) { s_clk_tree_initialized = true; return; - }*/ - - // Power - soc_cpu_clk_src_t cpu_clk_src_btld = clk_ll_cpu_get_src(); - if (cpu_clk_src_btld == SOC_CPU_CLK_SRC_CPLL) { - s_cpll_ref_cnt++; - } else if (cpu_clk_src_btld == SOC_CPU_CLK_SRC_PLL_F240M) { - // TODO: IDF-15502 - s_pll_src_cg_ref_cnt[SOC_MOD_CLK_PLL_F240M] = 1; } - // flash clock source is set to BBPLL in bootloader - s_pll_src_cg_ref_cnt[SOC_MOD_CLK_BBPLL] = 1; + // Cold boot only + soc_cpu_clk_src_t cpu_src = clk_ll_cpu_get_src(); + if (cpu_src == SOC_CPU_CLK_SRC_PLL_F240M) { + s_mod_clk_gate_ref_cnt[SOC_MOD_CLK_PLL_F240M] = 1; + s_root_pll_power_ref_cnt[SOC_ROOT_CIRCUIT_CLK_BBPLL] = 1; + } else if (cpu_src == SOC_CPU_CLK_SRC_CPLL) { + s_root_pll_power_ref_cnt[SOC_ROOT_CIRCUIT_CLK_CPLL] = 1; + } + + if (cpu_src != SOC_CPU_CLK_SRC_PLL_F240M) { + _clk_gate_ll_ref_240m_clk_en(false); + // Not do clk_ll_bbpll_disable since MSPI depends on BBPLL: TODO: IDF-15889 + } + // Add ref count for Flash using. // TODO: IDF-15889 + s_root_pll_power_ref_cnt[SOC_ROOT_CIRCUIT_CLK_BBPLL]++; + + if (cpu_src != SOC_CPU_CLK_SRC_CPLL) { + clk_ll_cpll_disable(); + } + + _clk_gate_ll_ref_160m_clk_en(false); + _clk_gate_ll_ref_120m_clk_en(false); + _clk_gate_ll_ref_80m_clk_en(false); + _clk_gate_ll_ref_60m_clk_en(false); + _clk_gate_ll_ref_20m_clk_en(false); + _clk_gate_ll_ref_50m_clk_en(false); + _clk_gate_ll_ref_25m_clk_en(false); + + clk_ll_xtalx2_disable(); + + HP_ALIVE_SYS.hp_clk_ctrl.hp_audio_pll_clk_en = 0; + HP_ALIVE_SYS.hp_clk_ctrl.hp_sdio_pll2_clk_en = 0; + HP_ALIVE_SYS.hp_clk_ctrl.hp_sdio_pll1_clk_en = 0; + HP_ALIVE_SYS.hp_clk_ctrl.hp_sdio_pll0_clk_en = 0; - // Gating: disable all PLL-derived reference clocks; they will be re-enabled on demand via esp_clk_tree_enable_src - // TODO: IDF-15502 - //_clk_gate_ll_ref_20m_clk_en(false); - //_clk_gate_ll_ref_25m_clk_en(false); - //_clk_gate_ll_ref_50m_clk_en(false); - //_clk_gate_ll_ref_80m_clk_en(false); - //_clk_gate_ll_ref_160m_clk_en(false); - //if (s_pll_src_cg_ref_cnt[SOC_MOD_CLK_PLL_F240M] == 0) _clk_gate_ll_ref_240m_clk_en(false); s_clk_tree_initialized = true; } bool esp_clk_tree_enable_power(soc_root_clk_circuit_t clk_circuit, bool enable) { + if (clk_circuit >= SOC_ROOT_CIRCUIT_CLK_MAX) { + return false; + } + bool toggled = false; switch (clk_circuit) { case SOC_ROOT_CIRCUIT_CLK_CPLL: + case SOC_ROOT_CIRCUIT_CLK_BBPLL: + case SOC_ROOT_CIRCUIT_CLK_XTAL_X2: { if (enable) { - s_cpll_ref_cnt++; + toggled = (esp_clk_tree_root_pll_power_acquire(clk_circuit) == 0); } else { - s_cpll_ref_cnt--; + toggled = (esp_clk_tree_root_pll_power_release(clk_circuit) == 1); } - - // Note that a calibration is usually needed after enabling CPLL - if (s_cpll_ref_cnt == 1) { - clk_ll_cpll_enable(); - toggled = true; - } else if (s_cpll_ref_cnt == 0) { - clk_ll_cpll_disable(); - toggled = true; - } - - assert(s_cpll_ref_cnt >= 0); break; + } default: break; } return toggled; } -#define ENABLE_CLK_GATE(clk_src_en_func, enable) \ - PERIPH_RCC_ATOMIC() { \ - clk_src_en_func(enable); \ +bool esp_clk_tree_port_is_power_on(soc_root_clk_circuit_t clk_circuit) +{ + if (clk_circuit >= SOC_ROOT_CIRCUIT_CLK_MAX) { + return false; } + if (clk_circuit == SOC_ROOT_CIRCUIT_CLK_BBPLL || clk_circuit == SOC_ROOT_CIRCUIT_CLK_CPLL + || clk_circuit == SOC_ROOT_CIRCUIT_CLK_XTAL_X2) { + int16_t cnt; + + esp_os_enter_critical(&s_clk_tree_spinlock); + cnt = s_root_pll_power_ref_cnt[clk_circuit]; + esp_os_exit_critical(&s_clk_tree_spinlock); + return cnt > 0; + } + return false; +} + +typedef enum { + ESP_CLK_TREE_GATED_CLK_RC_FAST, + ESP_CLK_TREE_GATED_CLK_PLL_F20M, + ESP_CLK_TREE_GATED_CLK_PLL_F60M, + ESP_CLK_TREE_GATED_CLK_PLL_F120M, + ESP_CLK_TREE_GATED_CLK_PLL_F160M, + ESP_CLK_TREE_GATED_CLK_PLL_F240M, + ESP_CLK_TREE_GATED_CLK_NUM, +} esp_clk_tree_gated_clk_id_t; + +static const esp_clk_tree_gated_clk_t s_gated_ref_clks[] = { + [ESP_CLK_TREE_GATED_CLK_RC_FAST] = { SOC_MOD_CLK_RC_FAST, NULL, esp_clk_tree_parent_rc_fast }, + [ESP_CLK_TREE_GATED_CLK_PLL_F20M] = { SOC_MOD_CLK_PLL_F20M, _clk_gate_ll_ref_20m_clk_en, esp_clk_tree_parent_bbpll }, + [ESP_CLK_TREE_GATED_CLK_PLL_F60M] = { SOC_MOD_CLK_PLL_F60M, _clk_gate_ll_ref_60m_clk_en, esp_clk_tree_parent_bbpll }, + [ESP_CLK_TREE_GATED_CLK_PLL_F120M] = { SOC_MOD_CLK_PLL_F120M, _clk_gate_ll_ref_120m_clk_en, esp_clk_tree_parent_bbpll }, + [ESP_CLK_TREE_GATED_CLK_PLL_F160M] = { SOC_MOD_CLK_PLL_F160M, _clk_gate_ll_ref_160m_clk_en, esp_clk_tree_parent_bbpll }, + [ESP_CLK_TREE_GATED_CLK_PLL_F240M] = { SOC_MOD_CLK_PLL_F240M, _clk_gate_ll_ref_240m_clk_en, esp_clk_tree_parent_bbpll }, +}; + +#define ENABLE_CLK_GATE(clk_src_en_func, enable) \ + do { \ + if ((clk_src_en_func) != NULL) { \ + PERIPH_RCC_ATOMIC() { \ + (clk_src_en_func)(enable); \ + }; \ + } \ + } while (0) + +FORCE_INLINE_ATTR esp_err_t esp_clk_tree_enable_gated_clk(const esp_clk_tree_gated_clk_t *entry, bool enable) +{ + int16_t prev_ref_cnt; + + esp_os_enter_critical(&s_clk_tree_spinlock); + if (enable) { + prev_ref_cnt = s_mod_clk_gate_ref_cnt[entry->clk_id]++; + } else { + prev_ref_cnt = s_mod_clk_gate_ref_cnt[entry->clk_id]--; + if (prev_ref_cnt <= 0) { + s_mod_clk_gate_ref_cnt[entry->clk_id] = 0; + esp_os_exit_critical(&s_clk_tree_spinlock); + ESP_EARLY_LOGW(TAG, "soc_module_clk_t %d disabled multiple times!!", entry->clk_id); + return ESP_OK; + } + } + esp_os_exit_critical(&s_clk_tree_spinlock); + + if (prev_ref_cnt == 0 && enable) { + if (entry->parent_power != NULL) { + entry->parent_power(true); + } + ENABLE_CLK_GATE(entry->set_gate, true); + } else if (prev_ref_cnt == 1 && !enable) { + ENABLE_CLK_GATE(entry->set_gate, false); + if (entry->parent_power != NULL) { + entry->parent_power(false); + } + } + return ESP_OK; +} esp_err_t esp_clk_tree_enable_src(soc_module_clk_t clk_src, bool enable) { - if (clk_src < 1 || clk_src >= SOC_MOD_CLK_INVALID) { - // some conditions is legal, e.g. -1 means external clock source + if (clk_src < 1 || clk_src >= SOC_MOD_CLK_INVALID || clk_src == SOC_MOD_CLK_XTAL) { + /* Not managed by esp_clk_tree*/ return ESP_OK; } @@ -241,59 +588,36 @@ esp_err_t esp_clk_tree_enable_src(soc_module_clk_t clk_src, bool enable) return ESP_OK; } - int16_t prev_ref_cnt = 0; - - // Derived PLL clocks (PLL_F50M, ...) that participate in the shared - // refcount/lock engine route through that engine instead of the - // global s_pll_src_cg_ref_cnt array below. - if (esp_clk_tree_get_derived_clk_desc(clk_src) != NULL) { - return enable ? esp_clk_tree_derived_clk_acquire(clk_src) - : esp_clk_tree_derived_clk_release(clk_src); - } - + esp_clk_tree_gated_clk_id_t gated_clk_id; // these clock sources have their own reference counting switch (clk_src) { - case SOC_MOD_CLK_APLL: - if (enable) { - esp_clk_tree_apll_acquire(); - } else { - esp_clk_tree_apll_release(); - } - return ESP_OK; - case SOC_MOD_CLK_MPLL: - if (enable) { - return esp_clk_tree_mpll_acquire(); - } else { - esp_clk_tree_mpll_release(); - } - return ESP_OK; - default: - break; - } - - // other clock sources use the global reference counting - if (enable) { - prev_ref_cnt = atomic_fetch_add(&s_pll_src_cg_ref_cnt[clk_src], 1); - } else { - prev_ref_cnt = atomic_fetch_sub(&s_pll_src_cg_ref_cnt[clk_src], 1); - if (prev_ref_cnt <= 0) { - ESP_EARLY_LOGW(TAG, "soc_module_clk_t %d disabled multiple times!!", clk_src); - atomic_store(&s_pll_src_cg_ref_cnt[clk_src], 0); + case SOC_MOD_CLK_APLL: + if (enable) { + esp_clk_tree_apll_acquire(); + } else { + esp_clk_tree_apll_release(); + } + return ESP_OK; + case SOC_MOD_CLK_MPLL: + if (enable) { + return esp_clk_tree_mpll_acquire(); + } else { + esp_clk_tree_mpll_release(); return ESP_OK; } + case SOC_MOD_CLK_RC_FAST: gated_clk_id = ESP_CLK_TREE_GATED_CLK_RC_FAST; break; + case SOC_MOD_CLK_PLL_F20M: gated_clk_id = ESP_CLK_TREE_GATED_CLK_PLL_F20M; break; + case SOC_MOD_CLK_PLL_F60M: gated_clk_id = ESP_CLK_TREE_GATED_CLK_PLL_F60M; break; + case SOC_MOD_CLK_PLL_F120M: gated_clk_id = ESP_CLK_TREE_GATED_CLK_PLL_F120M; break; + case SOC_MOD_CLK_PLL_F160M: gated_clk_id = ESP_CLK_TREE_GATED_CLK_PLL_F160M; break; + case SOC_MOD_CLK_PLL_F240M: gated_clk_id = ESP_CLK_TREE_GATED_CLK_PLL_F240M; break; + default: + // Derived PLL clocks (PLL_F25M/F50M/F80M) use the shared derived-clk engine. + if (esp_clk_tree_get_derived_clk_desc(clk_src) != NULL) { + return enable ? esp_clk_tree_derived_clk_acquire(clk_src) + : esp_clk_tree_derived_clk_release(clk_src); + } + return ESP_OK; } - // TODO: IDF-15502 - //if ((prev_ref_cnt == 0 && enable) || (prev_ref_cnt == 1 && !enable)) { - // switch (clk_src) { - // case SOC_MOD_CLK_RC_FAST: enable ? rtc_dig_clk8m_enable() : rtc_dig_clk8m_disable(); break; - // case SOC_MOD_CLK_PLL_F20M: ENABLE_CLK_GATE(clk_gate_ll_ref_20m_clk_en, enable); break; - // case SOC_MOD_CLK_PLL_F25M: ENABLE_CLK_GATE(clk_gate_ll_ref_25m_clk_en, enable); break; - // case SOC_MOD_CLK_PLL_F80M: ENABLE_CLK_GATE(clk_gate_ll_ref_80m_clk_en, enable); break; - // case SOC_MOD_CLK_PLL_F160M: ENABLE_CLK_GATE(clk_gate_ll_ref_160m_clk_en, enable); break; - // case SOC_MOD_CLK_PLL_F240M: ENABLE_CLK_GATE(clk_gate_ll_ref_240m_clk_en, enable); break; - // default: break; - // } - //} - - return ESP_OK; + return esp_clk_tree_enable_gated_clk(&s_gated_ref_clks[gated_clk_id], enable); } diff --git a/components/esp_hw_support/port/esp32s31/include/soc/rtc.h b/components/esp_hw_support/port/esp32s31/include/soc/rtc.h index 7d0dadb89f0..44c5ee342e3 100644 --- a/components/esp_hw_support/port/esp32s31/include/soc/rtc.h +++ b/components/esp_hw_support/port/esp32s31/include/soc/rtc.h @@ -88,6 +88,10 @@ typedef struct { uint32_t slow_clk_dcap : 8; //!< RC_SLOW clock adjustment parameter (higher value leads to lower frequency) uint32_t clk_8m_dfreq : 8; //!< RC_FAST clock adjustment parameter (higher value leads to higher frequency) uint32_t rc32k_dfreq : 10; //!< Internal RC32K clock adjustment parameter (higher value leads to higher frequency) + uint32_t disable_apll : 1; //!< Whether to disable APLL in rtc_clk_init + uint32_t disable_mpll : 1; //!< Whether to disable MPLL in rtc_clk_init + uint32_t disable_cpll : 1; //!< Whether to disable CPLL in rtc_clk_init + uint32_t disable_bbpll : 1; //!< Whether to disable BBPLL in rtc_clk_init } rtc_clk_config_t; /** @@ -103,6 +107,10 @@ typedef struct { .slow_clk_dcap = RTC_CNTL_SCK_DCAP_DEFAULT, \ .clk_8m_dfreq = RTC_CNTL_CK8M_DFREQ_DEFAULT, \ .rc32k_dfreq = RTC_CNTL_RC32K_DFREQ_DEFAULT, \ + .disable_apll = 1, \ + .disable_mpll = 1, \ + .disable_cpll = 0, \ + .disable_bbpll = 1, \ } /** diff --git a/components/esp_hw_support/port/esp32s31/rtc_clk.c b/components/esp_hw_support/port/esp32s31/rtc_clk.c index 86afd68dd73..31bb1433ca5 100644 --- a/components/esp_hw_support/port/esp32s31/rtc_clk.c +++ b/components/esp_hw_support/port/esp32s31/rtc_clk.c @@ -357,7 +357,9 @@ static void rtc_clk_cpu_src_clk_enable(soc_cpu_clk_src_t new_src, uint32_t new_s rtc_clk_cpll_configure(rtc_clk_xtal_freq_get(), new_src_freq_mhz); } } else if (new_src == SOC_CPU_CLK_SRC_PLL_F240M) { -#if !BOOTLOADER_BUILD +#if BOOTLOADER_BUILD + clk_ll_bbpll_enable(); +#else if (!s_is_pll_f240m_acquired) { esp_clk_tree_enable_src(SOC_MOD_CLK_PLL_F240M, true); s_is_pll_f240m_acquired = true; @@ -380,7 +382,9 @@ static void rtc_clk_cpu_src_clk_disable(soc_cpu_clk_src_t old_src) } #endif } else if (old_src == SOC_CPU_CLK_SRC_PLL_F240M) { -#if !BOOTLOADER_BUILD +#if BOOTLOADER_BUILD + /* Do not clk_ll_bbpll_disable(): Flash may still use BBPLL (reg_flash_clk_src_sel==1) */ +#else assert(s_is_pll_f240m_acquired); s_is_pll_f240m_acquired = false; esp_clk_tree_enable_src(SOC_MOD_CLK_PLL_F240M, false); diff --git a/components/esp_hw_support/port/esp32s31/rtc_clk_init.c b/components/esp_hw_support/port/esp32s31/rtc_clk_init.c index 0e14f89fbf0..75ffc533bbb 100644 --- a/components/esp_hw_support/port/esp32s31/rtc_clk_init.c +++ b/components/esp_hw_support/port/esp32s31/rtc_clk_init.c @@ -8,6 +8,7 @@ #include #include #include +#include "sdkconfig.h" #include "esp32s31/rom/ets_sys.h" #include "esp32s31/rom/rtc.h" #include "soc/rtc.h" @@ -27,6 +28,25 @@ ESP_HW_LOG_ATTR_TAG(TAG, "rtc_clk_init"); +static inline void rtc_clk_pll_disable(rtc_clk_config_t cfg) +{ + if (cfg.disable_apll) { + clk_ll_apll_disable(); + } + if (cfg.disable_mpll) { + clk_ll_mpll_disable(); + } + if (cfg.disable_cpll) { + clk_ll_cpll_disable(); + } +#if !CONFIG_USJ_ENABLE_USB_SERIAL_JTAG && !CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG_ENABLED + // USB-Serial-JTAG depends on bbpll480M, bypass disable bbpll if USB console is used. + if (cfg.disable_bbpll) { + clk_ll_bbpll_disable(); + } +#endif +} + void rtc_clk_init(rtc_clk_config_t cfg) { rtc_cpu_freq_config_t old_config, new_config; @@ -50,6 +70,9 @@ void rtc_clk_init(rtc_clk_config_t cfg) // No need to wait UART0 TX idle since its default clock source is XTAL, should not be affected by system clock configuration + /* Disable PLLs to save power, the PLLs will be enabled by the user in application code */ + rtc_clk_pll_disable(cfg); + /* Set CPU frequency */ rtc_clk_cpu_freq_get_config(&old_config); uint32_t freq_before = old_config.freq_mhz; diff --git a/components/esp_hw_support/port/esp32s31/rtc_time.c b/components/esp_hw_support/port/esp32s31/rtc_time.c index 6c60a93f95a..004a143e62d 100644 --- a/components/esp_hw_support/port/esp32s31/rtc_time.c +++ b/components/esp_hw_support/port/esp32s31/rtc_time.c @@ -144,6 +144,9 @@ uint32_t rtc_clk_cal_internal(soc_clk_freq_calculation_src_t cal_clk_sel, uint32 } CLEAR_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START); clk_ll_freq_calculation_set_divider(1); + // Back to always on clock source, Otherwise, if the source for this calibration is subsequently turned off, + // the next calibration will not be able to switch to the new calibration source. + clk_ll_freq_calulation_set_target(CLK_CAL_RC_SLOW); /* if dig_32k_xtal was originally off and enabled due to calibration, then set back to off state */ if (cal_clk_sel == CLK_CAL_32K_XTAL && !dig_32k_xtal_enabled) { diff --git a/components/esp_hw_support/port/esp_clk_tree_common.c b/components/esp_hw_support/port/esp_clk_tree_common.c index 4c6378bbfd5..c42bbb6e66b 100644 --- a/components/esp_hw_support/port/esp_clk_tree_common.c +++ b/components/esp_hw_support/port/esp_clk_tree_common.c @@ -409,8 +409,8 @@ end: * dispatchers route into. * * Semantics: - * - acquire: ref_cnt++; on first acquire enable the gate. - * - release: ref_cnt--; on last release disable the gate. + * - acquire: ref_cnt++; on first acquire acquire_parent then enable the gate. + * - release: ref_cnt--; on last release disable the gate and release_parent. * - select_upstream: program the mux to source from `upstream`. * - freq_set: pick a divider for `state->cur_upstream` (if `select_upstream` * was called) or auto-pick an upstream that divides cleanly @@ -436,14 +436,21 @@ esp_err_t esp_clk_tree_derived_clk_acquire(soc_module_clk_t clk_src) return ESP_ERR_NOT_SUPPORTED; } esp_clk_tree_derived_clk_state_t *state = desc->state; - + esp_err_t ret = ESP_OK; esp_os_enter_critical(&s_derived_clk_spinlock); state->ref_cnt++; if (state->ref_cnt == 1) { - desc->set_gate(true); + if (desc->acquire_parent != NULL) { + ret = desc->acquire_parent(); + } + if (ret == ESP_OK) { + desc->set_gate(true); + } else { + state->ref_cnt--; + } } esp_os_exit_critical(&s_derived_clk_spinlock); - return ESP_OK; + return ret; } esp_err_t esp_clk_tree_derived_clk_release(soc_module_clk_t clk_src) @@ -455,6 +462,7 @@ esp_err_t esp_clk_tree_derived_clk_release(soc_module_clk_t clk_src) esp_clk_tree_derived_clk_state_t *state = desc->state; bool released_too_many = false; + esp_err_t ret = ESP_OK; esp_os_enter_critical(&s_derived_clk_spinlock); if (state->ref_cnt <= 0) { state->ref_cnt = 0; @@ -465,13 +473,17 @@ esp_err_t esp_clk_tree_derived_clk_release(soc_module_clk_t clk_src) desc->set_gate(false); state->cur_upstream = SOC_MOD_CLK_INVALID; state->cur_divider = 0; + if (desc->release_parent != NULL) { + ret = desc->release_parent(); + } } } esp_os_exit_critical(&s_derived_clk_spinlock); if (released_too_many) { ESP_HW_LOGW(TAG, "derived clk %d released without matching acquire", (int)clk_src); + return ESP_OK; } - return ESP_OK; + return ret; } /** @@ -521,6 +533,7 @@ esp_err_t esp_clk_tree_derived_clk_freq_set(soc_module_clk_t clk_src, if (desc == NULL || desc->state == NULL || desc->upstreams == NULL) { return ESP_ERR_NOT_SUPPORTED; } + esp_clk_tree_derived_clk_state_t *state = desc->state; ESP_RETURN_ON_FALSE(expt_freq_hz > 0, ESP_ERR_INVALID_ARG, TAG, "freq must be > 0"); @@ -551,32 +564,49 @@ esp_err_t esp_clk_tree_derived_clk_freq_set(soc_module_clk_t clk_src, // (e.g. another peer ran enable_src already but hasn't called freq_set // yet). Mirrors MPLL's `cur == 0 || ref_cnt < 2` check. bool first_commit = (state->cur_divider == 0); + bool upstream_changed = false; if (state->ref_cnt < 2 || same_config || first_commit) { // First-time configuration: also program the mux. When the caller // already invoked `select_upstream`, `state->cur_upstream` already // matches `upstream` so the mux is left untouched. - if (state->cur_upstream != upstream && desc->set_src != NULL) { - desc->set_src(mux_sel); + if (state->cur_upstream != upstream) { + upstream_changed = true; + if (desc->set_src != NULL) { + desc->set_src(mux_sel); + } + } + if (desc->set_divider != NULL) { + desc->set_divider(divider); } - desc->set_divider(divider); state->cur_upstream = upstream; state->cur_divider = divider; } else { ret = ESP_ERR_INVALID_STATE; } + if (ret == ESP_OK && upstream_changed && desc->acquire_parent != NULL) { + ret = desc->acquire_parent(); + } esp_os_exit_critical(&s_derived_clk_spinlock); reported_upstream = state->cur_upstream; reported_divider = state->cur_divider; if (real_freq_hz != NULL) { - uint32_t up_hz = 0; - if (reported_upstream != SOC_MOD_CLK_INVALID && reported_divider != 0 && - esp_clk_tree_src_get_freq_hz(reported_upstream, - ESP_CLK_TREE_SRC_FREQ_PRECISION_APPROX, - &up_hz) == ESP_OK) { - *real_freq_hz = up_hz / reported_divider; + if (desc->set_divider == NULL) { + if (esp_clk_tree_src_get_freq_hz(clk_src, + ESP_CLK_TREE_SRC_FREQ_PRECISION_APPROX, + real_freq_hz) != ESP_OK) { + *real_freq_hz = 0; + } } else { - *real_freq_hz = 0; + uint32_t up_hz = 0; + if (reported_upstream != SOC_MOD_CLK_INVALID && reported_divider != 0 && + esp_clk_tree_src_get_freq_hz(reported_upstream, + ESP_CLK_TREE_SRC_FREQ_PRECISION_APPROX, + &up_hz) == ESP_OK) { + *real_freq_hz = up_hz / reported_divider; + } else { + *real_freq_hz = 0; + } } } return ret; @@ -626,7 +656,33 @@ esp_err_t esp_clk_tree_src_select_upstream(soc_module_clk_t clk_src, // Divider for the previous upstream is no longer meaningful; the next // `set_freq_hz` call will program a fresh divider for `upstream`. state->cur_divider = 0; + if (desc->acquire_parent != NULL) { + ret = desc->acquire_parent(); + } } esp_os_exit_critical(&s_derived_clk_spinlock); return ret; } + +bool esp_clk_tree_is_power_on(soc_root_clk_circuit_t clk_circuit) +{ +#if SOC_CLK_MPLL_SUPPORTED + if (clk_circuit == SOC_ROOT_CIRCUIT_CLK_MPLL) { + bool on; + esp_os_enter_critical(&s_periph_mpll_spinlock); + on = s_mpll_ref_cnt > 0; + esp_os_exit_critical(&s_periph_mpll_spinlock); + return on; + } +#endif +#if SOC_CLK_APLL_SUPPORTED + if (clk_circuit == SOC_ROOT_CIRCUIT_CLK_APLL) { + bool on; + esp_os_enter_critical(&s_periph_apll_spinlock); + on = s_apll_ref_cnt > 0; + esp_os_exit_critical(&s_periph_apll_spinlock); + return on; + } +#endif + return esp_clk_tree_port_is_power_on(clk_circuit); +} diff --git a/components/esp_lcd/i80/esp_lcd_panel_io_i80.c b/components/esp_lcd/i80/esp_lcd_panel_io_i80.c index 8e39afb418f..423d6aa2621 100644 --- a/components/esp_lcd/i80/esp_lcd_panel_io_i80.c +++ b/components/esp_lcd/i80/esp_lcd_panel_io_i80.c @@ -124,6 +124,9 @@ esp_err_t esp_lcd_new_i80_bus(const esp_lcd_i80_bus_config_t *bus_config, esp_lc { esp_err_t ret = ESP_OK; esp_lcd_i80_bus_t *bus = NULL; +#if CONFIG_IDF_TARGET_ESP32S31 + bool pll_f120m_enabled = false; +#endif ESP_RETURN_ON_FALSE(bus_config && ret_bus, ESP_ERR_INVALID_ARG, TAG, "invalid argument"); // although LCD_CAM can support up to 24 data lines, we restrict users to only use 8 or 16 bit width ESP_RETURN_ON_FALSE(bus_config->bus_width == 8 || bus_config->bus_width == 16, ESP_ERR_INVALID_ARG, @@ -185,6 +188,11 @@ esp_err_t esp_lcd_new_i80_bus(const esp_lcd_i80_bus_config_t *bus_config, esp_lc #endif // I80_USE_RETENTION_LINK // initialize HAL layer, so we can call LL APIs later lcd_hal_init(&bus->hal, bus_id); +#if CONFIG_IDF_TARGET_ESP32S31 + // PLL 120M was selected in esp_perip_clk_init on esp32s31. + ESP_GOTO_ON_ERROR(esp_clk_tree_enable_src((soc_module_clk_t)SOC_MOD_CLK_PLL_F120M, true), err, TAG, "clock source enable failed"); + pll_f120m_enabled = true; +#endif PERIPH_RCC_ATOMIC() { lcd_ll_enable_clock(bus->hal.dev, true); } @@ -268,6 +276,11 @@ err: esp_clk_tree_enable_src(bus->clk_src, false); bus->clk_src = SOC_MOD_CLK_INVALID; } +#if CONFIG_IDF_TARGET_ESP32S31 + if (pll_f120m_enabled) { + esp_clk_tree_enable_src((soc_module_clk_t)SOC_MOD_CLK_PLL_F120M, false); + } +#endif #if CONFIG_PM_ENABLE if (bus->pm_lock) { esp_pm_lock_delete(bus->pm_lock); @@ -291,6 +304,9 @@ esp_err_t esp_lcd_del_i80_bus(esp_lcd_i80_bus_handle_t bus) esp_clk_tree_enable_src(bus->clk_src, false); bus->clk_src = SOC_MOD_CLK_INVALID; } +#if CONFIG_IDF_TARGET_ESP32S31 + ESP_GOTO_ON_ERROR(esp_clk_tree_enable_src((soc_module_clk_t)SOC_MOD_CLK_PLL_F120M, false), err, TAG, "clock source disable failed"); +#endif #if I80_USE_RETENTION_LINK const periph_retention_module_t module_id = lcd_i80_reg_retention_info[bus_id].retention_module; sleep_retention_module_detach(module_id); diff --git a/components/esp_lcd/rgb/esp_lcd_panel_rgb.c b/components/esp_lcd/rgb/esp_lcd_panel_rgb.c index ae2add8c14c..9d5f5491d72 100644 --- a/components/esp_lcd/rgb/esp_lcd_panel_rgb.c +++ b/components/esp_lcd/rgb/esp_lcd_panel_rgb.c @@ -170,6 +170,9 @@ struct esp_rgb_panel_t { uint32_t fb_behind_cache: 1; // Whether the frame buffer is behind the cache uint32_t bb_behind_cache: 1; // Whether the bounce buffer is behind the cache uint32_t user_fb: 1; // Whether the frame buffer is provided by user +#if CONFIG_IDF_TARGET_ESP32S31 + uint32_t pll_f120m_enabled: 1; // Whether PLL_F120M was enabled for this panel instance +#endif } flags; }; @@ -257,6 +260,12 @@ static esp_err_t lcd_rgb_panel_destroy(esp_rgb_panel_t *rgb_panel) PERIPH_RCC_ATOMIC() { lcd_ll_enable_clock(rgb_panel->hal.dev, false); } +#if CONFIG_IDF_TARGET_ESP32S31 + if (rgb_panel->flags.pll_f120m_enabled) { + esp_clk_tree_enable_src((soc_module_clk_t)SOC_MOD_CLK_PLL_F120M, false); + rgb_panel->flags.pll_f120m_enabled = 0; + } +#endif if (rgb_panel->clk_src) { esp_clk_tree_enable_src(rgb_panel->clk_src, false); } @@ -405,6 +414,11 @@ esp_err_t esp_lcd_new_rgb_panel(const esp_lcd_rgb_panel_config_t *rgb_panel_conf lcd_hal_init(&rgb_panel->hal, panel_id); lcd_hal_context_t *hal = &rgb_panel->hal; // enable clock +#if CONFIG_IDF_TARGET_ESP32S31 + // PLL 120M was selected in esp_perip_clk_init on esp32s31. + ESP_GOTO_ON_ERROR(esp_clk_tree_enable_src((soc_module_clk_t)SOC_MOD_CLK_PLL_F120M, true), err, TAG, "clock source enable failed"); + rgb_panel->flags.pll_f120m_enabled = 1; +#endif PERIPH_RCC_ATOMIC() { lcd_ll_enable_clock(hal->dev, true); } diff --git a/components/esp_security/CMakeLists.txt b/components/esp_security/CMakeLists.txt index e210ad2c176..9d55a5336ac 100644 --- a/components/esp_security/CMakeLists.txt +++ b/components/esp_security/CMakeLists.txt @@ -9,7 +9,7 @@ endif() set(srcs "") set(requires esp_hal_security) -set(priv_requires esp_hw_support hal efuse) +set(priv_requires esp_hw_support hal efuse esp_hal_clock) set(priv_includes "src/${IDF_TARGET}") if(NOT non_os_build) diff --git a/components/esp_security/Kconfig b/components/esp_security/Kconfig index feadfe56a2f..c9784ffdf41 100644 --- a/components/esp_security/Kconfig +++ b/components/esp_security/Kconfig @@ -1,5 +1,22 @@ menu "ESP Security Specific" + config ESP_CRYPTO_CLK_ON_DEMAND + bool "Enable on-demand crypto clock management" + depends on IDF_TARGET_ESP32S31 + default y if PM_ENABLE + default n + help + When enabled, crypto/security peripheral clocks and their parent + (PLL_F240M) are enabled only while crypto operations are in + progress and disabled afterwards, reducing power consumption. + + Enabling and disabling these clocks has a noticeable performance + cost for crypto operations. When this option is disabled (default), + crypto clocks remain always on after initialization for better + crypto performance. + + Defaults to enabled when Power Management (CONFIG_PM_ENABLE) is on. + menu "Crypto DPA Protection" depends on SOC_CRYPTO_DPA_PROTECTION_SUPPORTED config ESP_CRYPTO_DPA_PROTECTION_AT_STARTUP diff --git a/components/esp_security/src/esp32c5/esp_crypto_clk.h b/components/esp_security/src/esp32c5/esp_crypto_clk.h index caca106b28f..d6d22b90130 100644 --- a/components/esp_security/src/esp32c5/esp_crypto_clk.h +++ b/components/esp_security/src/esp32c5/esp_crypto_clk.h @@ -1,20 +1,19 @@ /* - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2024-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ -#include "soc/soc.h" -#include "soc/pcr_reg.h" - #pragma once #include +#include "hal/sec_ll.h" +#include "soc/clk_tree_defs.h" void esp_crypto_common_clk_enable(bool enable); static inline void esp_crypto_clk_init(void) { // Set crypto clock (`clk_sec`) to use 480M SPLL clock - REG_SET_FIELD(PCR_SEC_CONF_REG, PCR_SEC_CLK_SEL, 0x2); + sec_ll_crypto_clk_src_sel(SOC_MOD_CLK_SPLL); } diff --git a/components/esp_security/src/esp32c61/esp_crypto_clk.h b/components/esp_security/src/esp32c61/esp_crypto_clk.h index caca106b28f..d6d22b90130 100644 --- a/components/esp_security/src/esp32c61/esp_crypto_clk.h +++ b/components/esp_security/src/esp32c61/esp_crypto_clk.h @@ -1,20 +1,19 @@ /* - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2024-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ -#include "soc/soc.h" -#include "soc/pcr_reg.h" - #pragma once #include +#include "hal/sec_ll.h" +#include "soc/clk_tree_defs.h" void esp_crypto_common_clk_enable(bool enable); static inline void esp_crypto_clk_init(void) { // Set crypto clock (`clk_sec`) to use 480M SPLL clock - REG_SET_FIELD(PCR_SEC_CONF_REG, PCR_SEC_CLK_SEL, 0x2); + sec_ll_crypto_clk_src_sel(SOC_MOD_CLK_SPLL); } diff --git a/components/esp_security/src/esp32h2/esp_crypto_clk.h b/components/esp_security/src/esp32h2/esp_crypto_clk.h index 74f36a220b4..290da917979 100644 --- a/components/esp_security/src/esp32h2/esp_crypto_clk.h +++ b/components/esp_security/src/esp32h2/esp_crypto_clk.h @@ -1,20 +1,19 @@ /* - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2024-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ -#include "soc/soc.h" -#include "soc/pcr_reg.h" - #pragma once #include +#include "hal/sec_ll.h" +#include "soc/clk_tree_defs.h" void esp_crypto_common_clk_enable(bool enable); static inline void esp_crypto_clk_init(void) { // Set crypto clock (`clk_sec`) to use 96M PLL clock - REG_SET_FIELD(PCR_SEC_CONF_REG, PCR_SEC_CLK_SEL, 0x3); + sec_ll_crypto_clk_src_sel(SOC_MOD_CLK_PLL_F96M); } diff --git a/components/esp_security/src/esp32h21/esp_crypto_clk.h b/components/esp_security/src/esp32h21/esp_crypto_clk.h index 14865e0f7c7..1be3fc08d62 100644 --- a/components/esp_security/src/esp32h21/esp_crypto_clk.h +++ b/components/esp_security/src/esp32h21/esp_crypto_clk.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2024-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -7,6 +7,7 @@ #include "soc/soc.h" #include "soc/pcr_reg.h" #include "esp_private/esp_clk_tree_common.h" +#include "hal/sec_ll.h" #pragma once @@ -18,5 +19,5 @@ static inline void esp_crypto_clk_init(void) { // Set crypto clock (`clk_sec`) to use 96M PLL clock esp_clk_tree_enable_src(SOC_MOD_CLK_PLL_F96M, true); - REG_SET_FIELD(PCR_SEC_CONF_REG, PCR_SEC_CLK_SEL, 0x3); + sec_ll_crypto_clk_src_sel(SOC_MOD_CLK_PLL_F96M); } diff --git a/components/esp_security/src/esp32h4/esp_crypto_clk.h b/components/esp_security/src/esp32h4/esp_crypto_clk.h index cf0a043509f..a39fdfabf09 100644 --- a/components/esp_security/src/esp32h4/esp_crypto_clk.h +++ b/components/esp_security/src/esp32h4/esp_crypto_clk.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -7,6 +7,7 @@ #include "soc/soc.h" #include "soc/pcr_reg.h" #include "esp_private/esp_clk_tree_common.h" +#include "hal/sec_ll.h" #pragma once @@ -18,5 +19,5 @@ static inline void esp_crypto_clk_init(void) { // Set crypto clock (`clk_sec`) to use 96M PLL clock esp_clk_tree_enable_src(SOC_MOD_CLK_PLL_F96M, true); - REG_SET_FIELD(PCR_SEC_CONF_REG, PCR_SEC_CLK_SEL, 0x3); + sec_ll_crypto_clk_src_sel(SOC_MOD_CLK_PLL_F96M); } diff --git a/components/esp_security/src/esp32p4/esp_crypto_clk.h b/components/esp_security/src/esp32p4/esp_crypto_clk.h index 694dfa496cd..9c07db3c080 100644 --- a/components/esp_security/src/esp32p4/esp_crypto_clk.h +++ b/components/esp_security/src/esp32p4/esp_crypto_clk.h @@ -1,14 +1,15 @@ /* - * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2024-2026 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ -#include "soc/soc.h" -#include "soc/hp_sys_clkrst_reg.h" -#include "esp_private/esp_clk_tree_common.h" + #pragma once #include +#include "hal/sec_ll.h" +#include "soc/clk_tree_defs.h" +#include "esp_private/esp_clk_tree_common.h" void esp_crypto_common_clk_enable(bool enable); @@ -16,5 +17,5 @@ static inline void esp_crypto_clk_init(void) { // Set crypto clock (`clk_sec`) to use 240M PLL clock esp_clk_tree_enable_src(SOC_MOD_CLK_PLL_F240M, true); - REG_SET_FIELD(HP_SYS_CLKRST_PERI_CLK_CTRL25_REG, HP_SYS_CLKRST_REG_CRYPTO_CLK_SRC_SEL, 0x2); + sec_ll_crypto_clk_src_sel(SOC_MOD_CLK_PLL_F240M); } diff --git a/components/esp_security/src/esp32s31/esp_crypto_clk.c b/components/esp_security/src/esp32s31/esp_crypto_clk.c index 172f291e2ae..a12cb869886 100644 --- a/components/esp_security/src/esp32s31/esp_crypto_clk.c +++ b/components/esp_security/src/esp32s31/esp_crypto_clk.c @@ -4,35 +4,83 @@ * SPDX-License-Identifier: Apache-2.0 */ +#include "sdkconfig.h" +#include "esp_attr.h" #include "esp_crypto_clk.h" #include "soc/clk_tree_defs.h" #include "soc/hp_sys_clkrst_struct.h" +#include "hal/clk_gate_ll.h" +#include "esp_private/esp_clk_tree_common.h" #if !NON_OS_BUILD #include "esp_private/critical_section.h" #endif #if !NON_OS_BUILD DEFINE_CRIT_SECTION_LOCK_STATIC(s_crypto_common_clk_mux); +#define CRYPTO_CLK_LOCK() esp_os_enter_critical_safe(&s_crypto_common_clk_mux) +#define CRYPTO_CLK_UNLOCK() esp_os_exit_critical_safe(&s_crypto_common_clk_mux) +#else +#define CRYPTO_CLK_LOCK() +#define CRYPTO_CLK_UNLOCK() #endif + +static void esp_crypto_pll_f240m_enable(bool enable) +{ +#if !NON_OS_BUILD + esp_clk_tree_enable_src(SOC_MOD_CLK_PLL_F240M, enable); +#else + /* Bootloader: BBPLL is already on; no esp_clk_tree in NON_OS. */ + _clk_gate_ll_ref_240m_clk_en(enable); +#endif +} + +FORCE_INLINE_ATTR void esp_crypto_periph_clk_enable(bool enable) +{ + HP_SYS_CLKRST.crypto_ctrl0.reg_crypto_sys_clk_en = enable; + HP_SYS_CLKRST.crypto_ctrl0.reg_crypto_sec_clk_en = enable; +} + +#if CONFIG_ESP_CRYPTO_CLK_ON_DEMAND + static int s_crypto_common_clk_ref_cnt; void esp_crypto_common_clk_enable(bool enable) { -#if !NON_OS_BUILD - esp_os_enter_critical_safe(&s_crypto_common_clk_mux); -#endif + CRYPTO_CLK_LOCK(); if (enable) { if (s_crypto_common_clk_ref_cnt++ == 0) { - HP_SYS_CLKRST.crypto_ctrl0.reg_crypto_sys_clk_en = 1; - HP_SYS_CLKRST.crypto_ctrl0.reg_crypto_sec_clk_en = 1; - } - } else { - if (s_crypto_common_clk_ref_cnt > 0 && --s_crypto_common_clk_ref_cnt == 0) { - HP_SYS_CLKRST.crypto_ctrl0.reg_crypto_sec_clk_en = 0; - HP_SYS_CLKRST.crypto_ctrl0.reg_crypto_sys_clk_en = 0; + /* Parent: PLL_F240M (see esp_crypto_clk_init() REG_CRYPTO_CLK_SRC_SEL). */ + esp_crypto_pll_f240m_enable(true); + esp_crypto_periph_clk_enable(true); } + } else if (s_crypto_common_clk_ref_cnt > 0 && --s_crypto_common_clk_ref_cnt == 0) { + esp_crypto_periph_clk_enable(false); + esp_crypto_pll_f240m_enable(false); } -#if !NON_OS_BUILD - esp_os_exit_critical_safe(&s_crypto_common_clk_mux); -#endif + CRYPTO_CLK_UNLOCK(); } + +#else /* !CONFIG_ESP_CRYPTO_CLK_ON_DEMAND */ + +static bool s_crypto_clk_always_on_done; + +static void esp_crypto_clk_always_on(void) +{ + CRYPTO_CLK_LOCK(); + if (!s_crypto_clk_always_on_done) { + esp_crypto_pll_f240m_enable(true); + esp_crypto_periph_clk_enable(true); + s_crypto_clk_always_on_done = true; + } + CRYPTO_CLK_UNLOCK(); +} + +void esp_crypto_common_clk_enable(bool enable) +{ + /* Keep clocks always on: enable once, ignore disable. */ + if (enable) { + esp_crypto_clk_always_on(); + } +} + +#endif /* CONFIG_ESP_CRYPTO_CLK_ON_DEMAND */ diff --git a/components/esp_security/src/esp32s31/esp_crypto_clk.h b/components/esp_security/src/esp32s31/esp_crypto_clk.h index 094e8c7f6da..25c3b3f80c2 100644 --- a/components/esp_security/src/esp32s31/esp_crypto_clk.h +++ b/components/esp_security/src/esp32s31/esp_crypto_clk.h @@ -7,14 +7,18 @@ #pragma once #include -#include "soc/soc.h" -#include "soc/hp_sys_clkrst_reg.h" -#include "soc/hp_sys_clkrst_struct.h" +#include "sdkconfig.h" +#include "hal/sec_ll.h" +#include "soc/clk_tree_defs.h" + +void esp_crypto_common_clk_enable(bool enable); static inline void esp_crypto_clk_init(void) { // Set crypto clock (`clk_sec`) to use 240M PLL clock - REG_SET_FIELD(HP_SYS_CLKRST_CRYPTO_CTRL0_REG, HP_SYS_CLKRST_REG_CRYPTO_CLK_SRC_SEL, 0x2); + sec_ll_crypto_clk_src_sel(SOC_MOD_CLK_PLL_F240M); +#if !CONFIG_ESP_CRYPTO_CLK_ON_DEMAND + /* Keep crypto clocks always on for better crypto performance. */ + esp_crypto_common_clk_enable(true); +#endif } - -void esp_crypto_common_clk_enable(bool enable); diff --git a/components/esp_system/CMakeLists.txt b/components/esp_system/CMakeLists.txt index ef9c9713f1f..e0824a29aef 100644 --- a/components/esp_system/CMakeLists.txt +++ b/components/esp_system/CMakeLists.txt @@ -100,7 +100,7 @@ else() INCLUDE_DIRS include PRIV_REQUIRES spi_flash esp_timer esp_mm esp_hal_clock esp_hal_mspi esp_hal_wdt esp_hal_debug_assist - esp_hal_uart esp_hal_dma + esp_hal_uart esp_hal_dma esp_hal_security # [refactor-todo] requirements due to init code, # should be removable once using component init functions # link-time registration is used. diff --git a/components/esp_system/port/soc/esp32s31/system_internal.c b/components/esp_system/port/soc/esp32s31/system_internal.c index deca93027e9..c7d9a6cbb4a 100644 --- a/components/esp_system/port/soc/esp32s31/system_internal.c +++ b/components/esp_system/port/soc/esp32s31/system_internal.c @@ -26,6 +26,7 @@ #endif #include "esp_private/cache_err_int.h" #include "hal/uart_ll.h" +#include "hal/sec_ll.h" #include "esp_memory_utils.h" extern int _bss_end; @@ -50,6 +51,9 @@ void esp_system_reset_modules_on_exit(void) CLEAR_PERI_REG_MASK(HP_SYSTEM_ECC_MEM_LP_CTRL_REG, HP_SYSTEM_ECC_MEM_LP_EN); SET_PERI_REG_MASK(HP_SYSTEM_ECC_MEM_LP_CTRL_REG, HP_SYSTEM_ECC_MEM_LP_FORCE_CTRL); + // Reset the clock source selection to an always-on source (XTAL), otherwise if the clock source + // is disabled, will get stuck in ROM encryption related ops. + sec_ll_crypto_clk_src_sel(SOC_MOD_CLK_XTAL); } static void IRAM_ATTR __attribute__((noinline, noreturn)) esp_restart_noos_inner(void) diff --git a/components/espcoredump/src/core_dump_sha.c b/components/espcoredump/src/core_dump_sha.c index 5ac04de8c4b..04194a81128 100644 --- a/components/espcoredump/src/core_dump_sha.c +++ b/components/espcoredump/src/core_dump_sha.c @@ -6,7 +6,9 @@ #include "sdkconfig.h" #include +#include "hal/sec_ll.h" #include "esp_core_dump_types.h" +#include "esp_crypto_periph_clk.h" const static char TAG[] __attribute__((unused)) = "esp_core_dump_sha"; @@ -44,6 +46,9 @@ static void core_dump_sha256_finish(core_dump_sha_ctx_t *sha_ctx) static void core_dump_sha256_start(core_dump_sha_ctx_t *sha_ctx) { + /* Back to always on clock source since the crypto clock source selected in + esp_crypto_clk_init may be disabled */ + sec_ll_crypto_clk_src_sel(SOC_MOD_CLK_XTAL); /* Enable SHA hardware */ ets_sha_enable(); ets_sha_init(&sha_ctx->ctx, SHA2_256); diff --git a/components/hal/esp32s31/include/hal/etm_ll.h b/components/hal/esp32s31/include/hal/etm_ll.h index a793e5bafbe..7d4376e95a6 100644 --- a/components/hal/esp32s31/include/hal/etm_ll.h +++ b/components/hal/esp32s31/include/hal/etm_ll.h @@ -74,7 +74,7 @@ static inline void etm_ll_set_clock_source(int group_id, etm_clock_source_t clk_ case ETM_CLK_SRC_RC_FAST: HP_SYS_CLKRST.etm_ctrl0.reg_soc_etm_clk_sel = 1; break; - case ETM_CLK_SRC_PLL_F80M: + case ETM_CLK_SRC_REF_F80M: HP_SYS_CLKRST.etm_ctrl0.reg_soc_etm_clk_sel = 2; break; default: diff --git a/components/soc/esp32s31/include/soc/clk_tree_defs.h b/components/soc/esp32s31/include/soc/clk_tree_defs.h index 6168f2d30f5..4504a342eef 100644 --- a/components/soc/esp32s31/include/soc/clk_tree_defs.h +++ b/components/soc/esp32s31/include/soc/clk_tree_defs.h @@ -77,6 +77,8 @@ typedef enum { SOC_ROOT_CIRCUIT_CLK_CPLL, /*!< CPLL_CLK is the output of the CPLL generator circuit */ SOC_ROOT_CIRCUIT_CLK_MPLL, /*!< MPLL_CLK is the output of the MPLL generator circuit */ SOC_ROOT_CIRCUIT_CLK_APLL, /*!< APLL_CLK is the output of the APLL generator circuit */ + SOC_ROOT_CIRCUIT_CLK_XTAL_X2, /*!< XTALx2 80MHz; ref_80m mux alternate source (see clk_ll_xtalx2_enable) */ + SOC_ROOT_CIRCUIT_CLK_MAX, } soc_root_clk_circuit_t; /** @@ -141,9 +143,11 @@ typedef enum { // For digital domain: peripherals SOC_MOD_CLK_SYS, /*!< SYS_CLK is the system clock, derived from SOC_CLK clock source */ SOC_MOD_CLK_PLL_F20M, /*!< PLL_F20M_CLK is derived from BBPLL (clock gating + default divider 24), its default frequency is 20MHz */ - SOC_MOD_CLK_PLL_F25M, /*!< PLL_F25M_CLK is derived from MPLL (clock gating + configurable divider), it will have a frequency of 25MHz */ - SOC_MOD_CLK_PLL_F50M, /*!< PLL_F50M_CLK is derived from C/MPLL (clock gating + configurable divider 10), it will have a frequency of 50MHz */ - SOC_MOD_CLK_PLL_F80M, /*!< PLL_F80M_CLK is derived from BBPLL (clock gating + default divider 6), its default frequency is 80MHz */ + SOC_MOD_CLK_PLL_F25M, /*!< PLL_F25M_CLK is from ref_25m (clock gating + configurable divider). Shares HP_SYS `ref_500m_sel` with PLL_F50M (0=CPLL, 1=MPLL); if both are used, they must select the same upstream. */ + SOC_MOD_CLK_PLL_F50M, /*!< PLL_F50M_CLK is from ref_50m (clock gating + configurable divider). Shares `ref_500m_sel` with PLL_F25M; frequency via esp_clk_tree_src_set_freq_hz (CPLL or MPLL upstream). */ + SOC_MOD_CLK_PLL_F60M, /*!< PLL_F60M_CLK is derived from BBPLL (clock gating + default divider 8), its default frequency is 60MHz */ + SOC_MOD_CLK_REF_F80M, /*!< REF_F80M_CLK from ref_80m (gate). Mux: BBPLL/6 (default) or XTALx2 80MHz (`reg_ref_80m_sel`). Frequency 80MHz either path. */ + SOC_MOD_CLK_PLL_F120M, /*!< PLL_F120M_CLK is derived from BBPLL (clock gating + default divider 4), its default frequency is 120MHz */ SOC_MOD_CLK_PLL_F160M, /*!< PLL_F160M_CLK is derived from BBPLL (clock gating + default divider 3), its default frequency is 160MHz */ SOC_MOD_CLK_PLL_F240M, /*!< PLL_F240M_CLK is derived from BBPLL (clock gating + default divider 2), its default frequency is 240MHz */ SOC_MOD_CLK_CPLL, /*!< CPLL is from 40MHz XTAL oscillator frequency multipliers */ @@ -222,25 +226,25 @@ typedef enum { * } * @endcode */ -#define SOC_GPTIMER_CLKS {SOC_MOD_CLK_PLL_F80M, SOC_MOD_CLK_RC_FAST, SOC_MOD_CLK_XTAL} +#define SOC_GPTIMER_CLKS {SOC_MOD_CLK_REF_F80M, SOC_MOD_CLK_RC_FAST, SOC_MOD_CLK_XTAL} /** * @brief Type of GPTimer clock source */ typedef enum { - GPTIMER_CLK_SRC_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M as the source clock */ + GPTIMER_CLK_SRC_REF_F80M = SOC_MOD_CLK_REF_F80M, /*!< Select REF_F80M as the source clock */ GPTIMER_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */ GPTIMER_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ - GPTIMER_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M as the default choice */ + GPTIMER_CLK_SRC_DEFAULT = SOC_MOD_CLK_REF_F80M, /*!< Select REF_F80M as the default choice */ } soc_periph_gptimer_clk_src_t; //////////////////////////////////////////////////ETM/////////////////////////////////////////////////////////////////// typedef enum { - ETM_CLK_SRC_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M as the source clock */ + ETM_CLK_SRC_REF_F80M = SOC_MOD_CLK_REF_F80M, /*!< Select REF_F80M as the source clock */ ETM_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */ ETM_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ - ETM_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M as the default choice */ + ETM_CLK_SRC_DEFAULT = SOC_MOD_CLK_REF_F80M, /*!< Select REF_F80M as the default choice */ } soc_periph_etm_clk_src_t; //////////////////////////////////////////////////RMT/////////////////////////////////////////////////////////////////// @@ -248,16 +252,16 @@ typedef enum { /** * @brief Array initializer for all supported clock sources of RMT */ -#define SOC_RMT_CLKS {SOC_MOD_CLK_PLL_F80M, SOC_MOD_CLK_RC_FAST, SOC_MOD_CLK_XTAL} +#define SOC_RMT_CLKS {SOC_MOD_CLK_REF_F80M, SOC_MOD_CLK_RC_FAST, SOC_MOD_CLK_XTAL} /** * @brief Type of RMT clock source */ typedef enum { - RMT_CLK_SRC_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M as the source clock */ + RMT_CLK_SRC_REF_F80M = SOC_MOD_CLK_REF_F80M, /*!< Select REF_F80M as the source clock */ RMT_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */ RMT_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ - RMT_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M as the default choice */ + RMT_CLK_SRC_DEFAULT = SOC_MOD_CLK_REF_F80M, /*!< Select REF_F80M as the default choice */ } soc_periph_rmt_clk_src_t; ///////////////////////////////////////////////////UART///////////////////////////////////////////////////////////////// @@ -265,16 +269,16 @@ typedef enum { /** * @brief Array initializer for all supported clock sources of UART */ -#define SOC_UART_CLKS {SOC_MOD_CLK_PLL_F80M, SOC_MOD_CLK_XTAL, SOC_MOD_CLK_RC_FAST} +#define SOC_UART_CLKS {SOC_MOD_CLK_REF_F80M, SOC_MOD_CLK_XTAL, SOC_MOD_CLK_RC_FAST} /** * @brief Type of UART clock source, reserved for the legacy UART driver */ typedef enum { - UART_SCLK_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< UART source clock is PLL_F80M */ + UART_SCLK_REF_F80M = SOC_MOD_CLK_REF_F80M, /*!< UART source clock is REF_F80M */ UART_SCLK_RTC = SOC_MOD_CLK_RC_FAST, /*!< UART source clock is RC_FAST */ UART_SCLK_XTAL = SOC_MOD_CLK_XTAL, /*!< UART source clock is XTAL */ - UART_SCLK_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< UART source clock default choice is PLL_F80M */ + UART_SCLK_DEFAULT = SOC_MOD_CLK_REF_F80M, /*!< UART source clock default choice is REF_F80M */ } soc_periph_uart_clk_src_legacy_t; /** @@ -296,7 +300,7 @@ typedef enum { /** * @brief Array initializer for all supported clock sources of LEDC */ -#define SOC_LEDC_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_PLL_F80M, SOC_MOD_CLK_RC_FAST} +#define SOC_LEDC_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_REF_F80M, SOC_MOD_CLK_RC_FAST} #define SOC_LEDC_CLK_STRS {"LEDC_USE_XTAL_CLK", "LEDC_USE_PLL_DIV_CLK", "LEDC_USE_RC_FAST_CLK"} /** @@ -304,7 +308,7 @@ typedef enum { */ typedef enum { LEDC_AUTO_CLK = 0, /*!< LEDC source clock will be automatically selected based on the giving resolution and duty parameter when init the timer*/ - LEDC_USE_PLL_DIV_CLK = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M clock as the source clock */ + LEDC_USE_PLL_DIV_CLK = SOC_MOD_CLK_REF_F80M, /*!< Select REF_F80M clock as the source clock */ LEDC_USE_RC_FAST_CLK = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */ LEDC_USE_XTAL_CLK = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ } soc_periph_ledc_clk_src_legacy_t; @@ -412,14 +416,14 @@ typedef enum { /** * @brief Array initializer for all supported clock sources of MWDT */ -#define SOC_MWDT_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_PLL_F80M, SOC_MOD_CLK_RC_FAST} +#define SOC_MWDT_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_REF_F80M, SOC_MOD_CLK_RC_FAST} /** * @brief MWDT clock source */ typedef enum { MWDT_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ - MWDT_CLK_SRC_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL fixed 80 MHz as the source clock */ + MWDT_CLK_SRC_REF_F80M = SOC_MOD_CLK_REF_F80M, /*!< Select PLL fixed 80 MHz as the source clock */ MWDT_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RTC fast as the source clock */ MWDT_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL 40 MHz as the default clock choice */ } soc_periph_mwdt_clk_src_t; @@ -431,8 +435,8 @@ typedef enum { */ typedef enum { SDM_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL clock as the source clock */ - SDM_CLK_SRC_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M clock as the source clock */ - SDM_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M clock as the default clock choice */ + SDM_CLK_SRC_REF_F80M = SOC_MOD_CLK_REF_F80M, /*!< Select REF_F80M clock as the source clock */ + SDM_CLK_SRC_DEFAULT = SOC_MOD_CLK_REF_F80M, /*!< Select REF_F80M clock as the default clock choice */ } soc_periph_sdm_clk_src_t; //////////////////////////////////////////////////GPIO Glitch Filter//////////////////////////////////////////////////// @@ -443,8 +447,8 @@ typedef enum { typedef enum { GLITCH_FILTER_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL clock as the source clock */ - GLITCH_FILTER_CLK_SRC_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M clock as the source clock */ - GLITCH_FILTER_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M clock as the default clock choice */ + GLITCH_FILTER_CLK_SRC_REF_F80M = SOC_MOD_CLK_REF_F80M, /*!< Select REF_F80M clock as the source clock */ + GLITCH_FILTER_CLK_SRC_DEFAULT = SOC_MOD_CLK_REF_F80M, /*!< Select REF_F80M clock as the default clock choice */ } soc_periph_glitch_filter_clk_src_t; ////////////////////////////////////////////////ANA_CMPR//////////////////////////////////////////////////// @@ -452,7 +456,7 @@ typedef enum { /** * @brief Array initializer for all supported clock sources of Analog Comparator */ -#define SOC_ANA_CMPR_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_RC_FAST, SOC_MOD_CLK_PLL_F80M} +#define SOC_ANA_CMPR_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_RC_FAST, SOC_MOD_CLK_REF_F80M} /** * @brief Type of Analog Comparator clock source @@ -460,8 +464,8 @@ typedef enum { typedef enum { ANA_CMPR_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL clock as the source clock */ ANA_CMPR_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */ - ANA_CMPR_CLK_SRC_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M as the source clock */ - ANA_CMPR_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M as the default clock choice */ + ANA_CMPR_CLK_SRC_REF_F80M = SOC_MOD_CLK_REF_F80M, /*!< Select REF_F80M as the source clock */ + ANA_CMPR_CLK_SRC_DEFAULT = SOC_MOD_CLK_REF_F80M, /*!< Select REF_F80M as the default clock choice */ } soc_periph_ana_cmpr_clk_src_t; //////////////////////////////////////////////////TWAI////////////////////////////////////////////////////////////////// @@ -469,15 +473,15 @@ typedef enum { /** * @brief Array initializer for all supported clock sources of TWAI */ -#define SOC_TWAI_CLKS {(soc_periph_twai_clk_src_t)SOC_MOD_CLK_XTAL, (soc_periph_twai_clk_src_t)SOC_MOD_CLK_PLL_F80M} +#define SOC_TWAI_CLKS {(soc_periph_twai_clk_src_t)SOC_MOD_CLK_XTAL, (soc_periph_twai_clk_src_t)SOC_MOD_CLK_REF_F80M} /** * @brief TWAI clock source */ typedef enum { TWAI_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */ - TWAI_CLK_SRC_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M as the source clock */ - TWAI_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M as the default clock choice */ + TWAI_CLK_SRC_REF_F80M = SOC_MOD_CLK_REF_F80M, /*!< Select REF_F80M as the source clock */ + TWAI_CLK_SRC_DEFAULT = SOC_MOD_CLK_REF_F80M, /*!< Select REF_F80M as the default clock choice */ } soc_periph_twai_clk_src_t; //////////////////////////////////////////////////MCPWM///////////////////////////////////////////////////////////////// @@ -786,11 +790,11 @@ typedef enum { /** * @brief Array initializer for all supported clock sources of EMAC PTP */ -#define SOC_EMAC_PTP_CLK {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_PLL_F80M} +#define SOC_EMAC_PTP_CLK {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_REF_F80M} typedef enum { EMAC_PTP_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, - EMAC_PTP_CLK_SRC_PLL_F80M = SOC_MOD_CLK_PLL_F80M, + EMAC_PTP_CLK_SRC_REF_F80M = SOC_MOD_CLK_REF_F80M, EMAC_PTP_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, } soc_periph_emac_ptp_clk_src_t;