Revert "fix(esp_hw_support): fix the issue of wifi rx packet loss when switchng soc root clock source"

This reverts commit 45ea08b955.
This commit is contained in:
sibeibei
2026-05-12 15:37:50 +08:00
parent 4c811d1e48
commit aa2bd15d46
2 changed files with 4 additions and 26 deletions
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -53,6 +53,7 @@ esp_err_t sleep_clock_system_retention_init(void *arg)
#if SOC_PM_SUPPORT_PMU_MODEM_STATE && CONFIG_ESP_WIFI_ENHANCED_LIGHT_SLEEP && CONFIG_XTAL_FREQ_AUTO
uint32_t xtal_freq_mhz = (uint32_t)rtc_clk_xtal_freq_get();
if (xtal_freq_mhz == SOC_XTAL_FREQ_48M) {
/* For the 48 MHz main XTAL, we need regdma to configured BBPLL by exec
* the PHY_I2C_MST_CMD_TYPE_BBPLL_CFG command from PHY i2c master
* command memory */
@@ -69,21 +70,6 @@ esp_err_t sleep_clock_system_retention_init(void *arg)
}
#endif
#if CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP
/* On ESP32-C5 ECO1, clearing BIT(31) of PCR_FPGA_DEBUG_REG (it's
* located in TOP domain) is used to fix the issue where the modem
* module fails to transmit and receive packets due to the loss of The
* modem root clock caused by automatic clock gating during soc root
* clock source switching. For detailed information, refer to IDF-11064 */
if (ESP_CHIP_REV_ABOVE(efuse_hal_chip_revision(), 1)) {
const static sleep_retention_entries_config_t rootclk_workaround[] = {
[0] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_PCR_LINK(9), PCR_FPGA_DEBUG_REG, PCR_FPGA_DEBUG_REG, 1, 0, 0), .owner = ENTRY(0) | ENTRY(1) }
};
err = sleep_retention_entries_create(rootclk_workaround, ARRAY_SIZE(rootclk_workaround), 1, SLEEP_RETENTION_MODULE_CLOCK_SYSTEM);
ESP_RETURN_ON_ERROR(err, TAG, "failed to allocate memory for modem root clock workaround, 1 level priority");
}
#endif
ESP_LOGI(TAG, "System Power, Clock and Reset sleep retention initialization");
return ESP_OK;
}