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fix(soc): Remove non-existent crypto registers (ESP32-C61)

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This commit is contained in:
harshal.patil
2026-06-03 16:03:20 +05:30
parent 837628688e
commit a9b74b5219
8 changed files with 59 additions and 312 deletions
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132
components/soc/esp32c61/register/soc/pcr_reg.h
View File

@@ -1,5 +1,5 @@
/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -1166,32 +1166,6 @@ extern "C" {
#define PCR_SPI2_CLKM_EN_V 0x00000001U
#define PCR_SPI2_CLKM_EN_S 22
/** PCR_AES_CONF_REG register
* AES configuration register
*/
#define PCR_AES_CONF_REG (DR_REG_PCR_BASE + 0x9c)
/** PCR_AES_CLK_EN : R/W; bitpos: [0]; default: 1;
* Set 1 to enable aes clock
*/
#define PCR_AES_CLK_EN (BIT(0))
#define PCR_AES_CLK_EN_M (PCR_AES_CLK_EN_V << PCR_AES_CLK_EN_S)
#define PCR_AES_CLK_EN_V 0x00000001U
#define PCR_AES_CLK_EN_S 0
/** PCR_AES_RST_EN : R/W; bitpos: [1]; default: 0;
* Set 1 to reset aes module
*/
#define PCR_AES_RST_EN (BIT(1))
#define PCR_AES_RST_EN_M (PCR_AES_RST_EN_V << PCR_AES_RST_EN_S)
#define PCR_AES_RST_EN_V 0x00000001U
#define PCR_AES_RST_EN_S 1
/** PCR_AES_READY : RO; bitpos: [2]; default: 1;
* Query this field after reset aes module
*/
#define PCR_AES_READY (BIT(2))
#define PCR_AES_READY_M (PCR_AES_READY_V << PCR_AES_READY_S)
#define PCR_AES_READY_V 0x00000001U
#define PCR_AES_READY_S 2
/** PCR_SHA_CONF_REG register
* SHA configuration register
*/
@@ -1218,58 +1192,6 @@ extern "C" {
#define PCR_SHA_READY_V 0x00000001U
#define PCR_SHA_READY_S 2
/** PCR_RSA_CONF_REG register
* RSA configuration register
*/
#define PCR_RSA_CONF_REG (DR_REG_PCR_BASE + 0xa4)
/** PCR_RSA_CLK_EN : R/W; bitpos: [0]; default: 1;
* Set 1 to enable rsa clock
*/
#define PCR_RSA_CLK_EN (BIT(0))
#define PCR_RSA_CLK_EN_M (PCR_RSA_CLK_EN_V << PCR_RSA_CLK_EN_S)
#define PCR_RSA_CLK_EN_V 0x00000001U
#define PCR_RSA_CLK_EN_S 0
/** PCR_RSA_RST_EN : R/W; bitpos: [1]; default: 0;
* Set 1 to reset rsa module
*/
#define PCR_RSA_RST_EN (BIT(1))
#define PCR_RSA_RST_EN_M (PCR_RSA_RST_EN_V << PCR_RSA_RST_EN_S)
#define PCR_RSA_RST_EN_V 0x00000001U
#define PCR_RSA_RST_EN_S 1
/** PCR_RSA_READY : RO; bitpos: [2]; default: 1;
* Query this field after reset rsa module
*/
#define PCR_RSA_READY (BIT(2))
#define PCR_RSA_READY_M (PCR_RSA_READY_V << PCR_RSA_READY_S)
#define PCR_RSA_READY_V 0x00000001U
#define PCR_RSA_READY_S 2
/** PCR_RSA_PD_CTRL_REG register
* RSA power control register
*/
#define PCR_RSA_PD_CTRL_REG (DR_REG_PCR_BASE + 0xa8)
/** PCR_RSA_MEM_PD : R/W; bitpos: [0]; default: 0;
* Set this bit to power down rsa internal memory.
*/
#define PCR_RSA_MEM_PD (BIT(0))
#define PCR_RSA_MEM_PD_M (PCR_RSA_MEM_PD_V << PCR_RSA_MEM_PD_S)
#define PCR_RSA_MEM_PD_V 0x00000001U
#define PCR_RSA_MEM_PD_S 0
/** PCR_RSA_MEM_FORCE_PU : R/W; bitpos: [1]; default: 1;
* Set this bit to force power up rsa internal memory
*/
#define PCR_RSA_MEM_FORCE_PU (BIT(1))
#define PCR_RSA_MEM_FORCE_PU_M (PCR_RSA_MEM_FORCE_PU_V << PCR_RSA_MEM_FORCE_PU_S)
#define PCR_RSA_MEM_FORCE_PU_V 0x00000001U
#define PCR_RSA_MEM_FORCE_PU_S 1
/** PCR_RSA_MEM_FORCE_PD : R/W; bitpos: [2]; default: 0;
* Set this bit to force power down rsa internal memory.
*/
#define PCR_RSA_MEM_FORCE_PD (BIT(2))
#define PCR_RSA_MEM_FORCE_PD_M (PCR_RSA_MEM_FORCE_PD_V << PCR_RSA_MEM_FORCE_PD_S)
#define PCR_RSA_MEM_FORCE_PD_V 0x00000001U
#define PCR_RSA_MEM_FORCE_PD_S 2
/** PCR_ECC_CONF_REG register
* ECC configuration register
*/
@@ -1322,58 +1244,6 @@ extern "C" {
#define PCR_ECC_MEM_FORCE_PD_V 0x00000001U
#define PCR_ECC_MEM_FORCE_PD_S 2
/** PCR_DS_CONF_REG register
* DS configuration register
*/
#define PCR_DS_CONF_REG (DR_REG_PCR_BASE + 0xb4)
/** PCR_DS_CLK_EN : R/W; bitpos: [0]; default: 1;
* Set 1 to enable ds clock
*/
#define PCR_DS_CLK_EN (BIT(0))
#define PCR_DS_CLK_EN_M (PCR_DS_CLK_EN_V << PCR_DS_CLK_EN_S)
#define PCR_DS_CLK_EN_V 0x00000001U
#define PCR_DS_CLK_EN_S 0
/** PCR_DS_RST_EN : R/W; bitpos: [1]; default: 0;
* Set 1 to reset ds module
*/
#define PCR_DS_RST_EN (BIT(1))
#define PCR_DS_RST_EN_M (PCR_DS_RST_EN_V << PCR_DS_RST_EN_S)
#define PCR_DS_RST_EN_V 0x00000001U
#define PCR_DS_RST_EN_S 1
/** PCR_DS_READY : RO; bitpos: [2]; default: 1;
* Query this field after reset ds module
*/
#define PCR_DS_READY (BIT(2))
#define PCR_DS_READY_M (PCR_DS_READY_V << PCR_DS_READY_S)
#define PCR_DS_READY_V 0x00000001U
#define PCR_DS_READY_S 2
/** PCR_HMAC_CONF_REG register
* HMAC configuration register
*/
#define PCR_HMAC_CONF_REG (DR_REG_PCR_BASE + 0xb8)
/** PCR_HMAC_CLK_EN : R/W; bitpos: [0]; default: 1;
* Set 1 to enable hmac clock
*/
#define PCR_HMAC_CLK_EN (BIT(0))
#define PCR_HMAC_CLK_EN_M (PCR_HMAC_CLK_EN_V << PCR_HMAC_CLK_EN_S)
#define PCR_HMAC_CLK_EN_V 0x00000001U
#define PCR_HMAC_CLK_EN_S 0
/** PCR_HMAC_RST_EN : R/W; bitpos: [1]; default: 0;
* Set 1 to reset hmac module
*/
#define PCR_HMAC_RST_EN (BIT(1))
#define PCR_HMAC_RST_EN_M (PCR_HMAC_RST_EN_V << PCR_HMAC_RST_EN_S)
#define PCR_HMAC_RST_EN_V 0x00000001U
#define PCR_HMAC_RST_EN_S 1
/** PCR_HMAC_READY : RO; bitpos: [2]; default: 1;
* Query this field after reset hmac module
*/
#define PCR_HMAC_READY (BIT(2))
#define PCR_HMAC_READY_M (PCR_HMAC_READY_V << PCR_HMAC_READY_S)
#define PCR_HMAC_READY_V 0x00000001U
#define PCR_HMAC_READY_S 2
/** PCR_ECDSA_CONF_REG register
* ECDSA configuration register
*/

122
components/soc/esp32c61/register/soc/pcr_struct.h
View File

@@ -1,5 +1,5 @@
/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -997,28 +997,6 @@ typedef union {
uint32_t val;
} pcr_spi2_clkm_conf_reg_t;
/** Type of aes_conf register
* AES configuration register
*/
typedef union {
struct {
/** aes_clk_en : R/W; bitpos: [0]; default: 1;
* Set 1 to enable aes clock
*/
uint32_t aes_clk_en:1;
/** aes_rst_en : R/W; bitpos: [1]; default: 0;
* Set 1 to reset aes module
*/
uint32_t aes_rst_en:1;
/** aes_ready : RO; bitpos: [2]; default: 1;
* Query this field after reset aes module
*/
uint32_t aes_ready:1;
uint32_t reserved_3:29;
};
uint32_t val;
} pcr_aes_conf_reg_t;
/** Type of sha_conf register
* SHA configuration register
*/
@@ -1041,50 +1019,6 @@ typedef union {
uint32_t val;
} pcr_sha_conf_reg_t;
/** Type of rsa_conf register
* RSA configuration register
*/
typedef union {
struct {
/** rsa_clk_en : R/W; bitpos: [0]; default: 1;
* Set 1 to enable rsa clock
*/
uint32_t rsa_clk_en:1;
/** rsa_rst_en : R/W; bitpos: [1]; default: 0;
* Set 1 to reset rsa module
*/
uint32_t rsa_rst_en:1;
/** rsa_ready : RO; bitpos: [2]; default: 1;
* Query this field after reset rsa module
*/
uint32_t rsa_ready:1;
uint32_t reserved_3:29;
};
uint32_t val;
} pcr_rsa_conf_reg_t;
/** Type of rsa_pd_ctrl register
* RSA power control register
*/
typedef union {
struct {
/** rsa_mem_pd : R/W; bitpos: [0]; default: 0;
* Set this bit to power down rsa internal memory.
*/
uint32_t rsa_mem_pd:1;
/** rsa_mem_force_pu : R/W; bitpos: [1]; default: 1;
* Set this bit to force power up rsa internal memory
*/
uint32_t rsa_mem_force_pu:1;
/** rsa_mem_force_pd : R/W; bitpos: [2]; default: 0;
* Set this bit to force power down rsa internal memory.
*/
uint32_t rsa_mem_force_pd:1;
uint32_t reserved_3:29;
};
uint32_t val;
} pcr_rsa_pd_ctrl_reg_t;
/** Type of ecc_conf register
* ECC configuration register
*/
@@ -1129,50 +1063,6 @@ typedef union {
uint32_t val;
} pcr_ecc_pd_ctrl_reg_t;
/** Type of ds_conf register
* DS configuration register
*/
typedef union {
struct {
/** ds_clk_en : R/W; bitpos: [0]; default: 1;
* Set 1 to enable ds clock
*/
uint32_t ds_clk_en:1;
/** ds_rst_en : R/W; bitpos: [1]; default: 0;
* Set 1 to reset ds module
*/
uint32_t ds_rst_en:1;
/** ds_ready : RO; bitpos: [2]; default: 1;
* Query this field after reset ds module
*/
uint32_t ds_ready:1;
uint32_t reserved_3:29;
};
uint32_t val;
} pcr_ds_conf_reg_t;
/** Type of hmac_conf register
* HMAC configuration register
*/
typedef union {
struct {
/** hmac_clk_en : R/W; bitpos: [0]; default: 1;
* Set 1 to enable hmac clock
*/
uint32_t hmac_clk_en:1;
/** hmac_rst_en : R/W; bitpos: [1]; default: 0;
* Set 1 to reset hmac module
*/
uint32_t hmac_rst_en:1;
/** hmac_ready : RO; bitpos: [2]; default: 1;
* Query this field after reset hmac module
*/
uint32_t hmac_ready:1;
uint32_t reserved_3:29;
};
uint32_t val;
} pcr_hmac_conf_reg_t;
/** Type of ecdsa_conf register
* ECDSA configuration register
*/
@@ -1952,14 +1842,14 @@ typedef struct {
volatile pcr_gdma_conf_reg_t gdma_conf;
volatile pcr_spi2_conf_reg_t spi2_conf;
volatile pcr_spi2_clkm_conf_reg_t spi2_clkm_conf;
volatile pcr_aes_conf_reg_t aes_conf;
uint32_t reserved_9c;
volatile pcr_sha_conf_reg_t sha_conf;
volatile pcr_rsa_conf_reg_t rsa_conf;
volatile pcr_rsa_pd_ctrl_reg_t rsa_pd_ctrl;
uint32_t reserved_a4;
uint32_t reserved_a8;
volatile pcr_ecc_conf_reg_t ecc_conf;
volatile pcr_ecc_pd_ctrl_reg_t ecc_pd_ctrl;
volatile pcr_ds_conf_reg_t ds_conf;
volatile pcr_hmac_conf_reg_t hmac_conf;
uint32_t reserved_b4;
uint32_t reserved_b8;
volatile pcr_ecdsa_conf_reg_t ecdsa_conf;
volatile pcr_iomux_conf_reg_t iomux_conf;
volatile pcr_iomux_clk_conf_reg_t iomux_clk_conf;