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fix(soc): Remove non-existent crypto registers (ESP32-C61)

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This commit is contained in:
harshal.patil
2026-06-03 16:03:20 +05:30
parent 837628688e
commit a9b74b5219
8 changed files with 59 additions and 312 deletions
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4
components/efuse/esp32c61/include/esp_efuse_chip.h
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@@ -64,10 +64,6 @@ typedef enum {
ESP_EFUSE_KEY_PURPOSE_USER = 0, /**< User purposes (software-only use) */
ESP_EFUSE_KEY_PURPOSE_ECDSA_KEY = 1, /**< ECDSA private key (Expected in little endian order)*/
ESP_EFUSE_KEY_PURPOSE_XTS_AES_128_KEY = 4, /**< XTS_AES_128_KEY (flash/PSRAM encryption) */
ESP_EFUSE_KEY_PURPOSE_HMAC_DOWN_ALL = 5, /**< HMAC Downstream mode */
ESP_EFUSE_KEY_PURPOSE_HMAC_DOWN_JTAG = 6, /**< JTAG soft enable key (uses HMAC Downstream mode) */
ESP_EFUSE_KEY_PURPOSE_HMAC_DOWN_DIGITAL_SIGNATURE = 7, /**< Digital Signature peripheral key (uses HMAC Downstream mode) */
ESP_EFUSE_KEY_PURPOSE_HMAC_UP = 8, /**< HMAC Upstream mode */
ESP_EFUSE_KEY_PURPOSE_SECURE_BOOT_DIGEST0 = 9, /**< SECURE_BOOT_DIGEST0 (Secure Boot key digest) */
ESP_EFUSE_KEY_PURPOSE_SECURE_BOOT_DIGEST1 = 10, /**< SECURE_BOOT_DIGEST1 (Secure Boot key digest) */
ESP_EFUSE_KEY_PURPOSE_SECURE_BOOT_DIGEST2 = 11, /**< SECURE_BOOT_DIGEST2 (Secure Boot key digest) */

33
components/efuse/src/efuse_controller/keys/with_key_purposes/esp_efuse_api_key.c
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@@ -300,35 +300,38 @@ esp_err_t esp_efuse_write_key(esp_efuse_block_t block, esp_efuse_purpose_t purpo
}
#endif // SOC_EFUSE_BLOCK9_KEY_PURPOSE_QUIRK
if (purpose == ESP_EFUSE_KEY_PURPOSE_XTS_AES_128_KEY ||
if (purpose == ESP_EFUSE_KEY_PURPOSE_XTS_AES_128_KEY
#ifdef SOC_EFUSE_XTS_AES_KEY_256
purpose == ESP_EFUSE_KEY_PURPOSE_XTS_AES_256_KEY_1 ||
purpose == ESP_EFUSE_KEY_PURPOSE_XTS_AES_256_KEY_2 ||
|| purpose == ESP_EFUSE_KEY_PURPOSE_XTS_AES_256_KEY_1
|| purpose == ESP_EFUSE_KEY_PURPOSE_XTS_AES_256_KEY_2
#endif //#ifdef SOC_EFUSE_XTS_AES_KEY_256
#if SOC_EFUSE_ECDSA_KEY
purpose == ESP_EFUSE_KEY_PURPOSE_ECDSA_KEY ||
|| purpose == ESP_EFUSE_KEY_PURPOSE_ECDSA_KEY
#endif
#if (!defined(CONFIG_IDF_TARGET_ESP32P4) && SOC_EFUSE_ECDSA_KEY_P192) || EFUSE_LL_HAS_ECDSA_KEY_P192
purpose == ESP_EFUSE_KEY_PURPOSE_ECDSA_KEY_P192 ||
|| purpose == ESP_EFUSE_KEY_PURPOSE_ECDSA_KEY_P192
#endif
#if (!defined(CONFIG_IDF_TARGET_ESP32P4) && SOC_EFUSE_ECDSA_KEY_P384) || EFUSE_LL_HAS_ECDSA_KEY_P384
purpose == ESP_EFUSE_KEY_PURPOSE_ECDSA_KEY_P384_L ||
purpose == ESP_EFUSE_KEY_PURPOSE_ECDSA_KEY_P384_H ||
|| purpose == ESP_EFUSE_KEY_PURPOSE_ECDSA_KEY_P384_L
|| purpose == ESP_EFUSE_KEY_PURPOSE_ECDSA_KEY_P384_H
#endif
#if SOC_PSRAM_ENCRYPTION_XTS_AES_128 || EFUSE_LL_HAS_PSRAM_ENCRYPTION_XTS_AES_128
purpose == ESP_EFUSE_KEY_PURPOSE_XTS_AES_128_PSRAM_KEY ||
|| purpose == ESP_EFUSE_KEY_PURPOSE_XTS_AES_128_PSRAM_KEY
#endif
#if SOC_PSRAM_ENCRYPTION_XTS_AES_256 || EFUSE_LL_HAS_PSRAM_ENCRYPTION_XTS_AES_256
purpose == ESP_EFUSE_KEY_PURPOSE_XTS_AES_256_PSRAM_KEY_1 ||
purpose == ESP_EFUSE_KEY_PURPOSE_XTS_AES_256_PSRAM_KEY_2 ||
|| purpose == ESP_EFUSE_KEY_PURPOSE_XTS_AES_256_PSRAM_KEY_1
|| purpose == ESP_EFUSE_KEY_PURPOSE_XTS_AES_256_PSRAM_KEY_2
#endif
#if SOC_KEY_MANAGER_SUPPORTED
purpose == ESP_EFUSE_KEY_PURPOSE_KM_INIT_KEY ||
|| purpose == ESP_EFUSE_KEY_PURPOSE_KM_INIT_KEY
#endif
purpose == ESP_EFUSE_KEY_PURPOSE_HMAC_DOWN_ALL ||
purpose == ESP_EFUSE_KEY_PURPOSE_HMAC_DOWN_JTAG ||
purpose == ESP_EFUSE_KEY_PURPOSE_HMAC_DOWN_DIGITAL_SIGNATURE ||
purpose == ESP_EFUSE_KEY_PURPOSE_HMAC_UP) {
#if SOC_HMAC_SUPPORTED
|| purpose == ESP_EFUSE_KEY_PURPOSE_HMAC_DOWN_ALL
|| purpose == ESP_EFUSE_KEY_PURPOSE_HMAC_DOWN_JTAG
|| purpose == ESP_EFUSE_KEY_PURPOSE_HMAC_DOWN_DIGITAL_SIGNATURE
|| purpose == ESP_EFUSE_KEY_PURPOSE_HMAC_UP
#endif
) {
ESP_EFUSE_CHK(esp_efuse_set_key_dis_read(block));
}
#if SOC_EFUSE_ECDSA_USE_HARDWARE_K

47
components/efuse/test_apps/main/with_key_purposes/test_efuse_keys.c
View File

@@ -86,35 +86,38 @@ static esp_err_t s_check_key(esp_efuse_block_t num_key, void* wr_key)
#endif // not CONFIG_EFUSE_FPGA_TEST
TEST_ASSERT_TRUE(esp_efuse_get_key_dis_write(num_key));
if (purpose == ESP_EFUSE_KEY_PURPOSE_XTS_AES_128_KEY ||
if (purpose == ESP_EFUSE_KEY_PURPOSE_XTS_AES_128_KEY
#ifdef SOC_EFUSE_XTS_AES_KEY_256
purpose == ESP_EFUSE_KEY_PURPOSE_XTS_AES_256_KEY_1 ||
purpose == ESP_EFUSE_KEY_PURPOSE_XTS_AES_256_KEY_2 ||
|| purpose == ESP_EFUSE_KEY_PURPOSE_XTS_AES_256_KEY_1
|| purpose == ESP_EFUSE_KEY_PURPOSE_XTS_AES_256_KEY_2
#endif
#if SOC_EFUSE_ECDSA_KEY
purpose == ESP_EFUSE_KEY_PURPOSE_ECDSA_KEY ||
|| purpose == ESP_EFUSE_KEY_PURPOSE_ECDSA_KEY
#endif
#if (!defined(CONFIG_IDF_TARGET_ESP32P4) && SOC_EFUSE_ECDSA_KEY_P192) || EFUSE_LL_HAS_ECDSA_KEY_P192
purpose == ESP_EFUSE_KEY_PURPOSE_ECDSA_KEY_P192 ||
|| purpose == ESP_EFUSE_KEY_PURPOSE_ECDSA_KEY_P192
#endif
#if (!defined(CONFIG_IDF_TARGET_ESP32P4) && SOC_EFUSE_ECDSA_KEY_P384) || EFUSE_LL_HAS_ECDSA_KEY_P384
purpose == ESP_EFUSE_KEY_PURPOSE_ECDSA_KEY_P384_L ||
purpose == ESP_EFUSE_KEY_PURPOSE_ECDSA_KEY_P384_H ||
|| purpose == ESP_EFUSE_KEY_PURPOSE_ECDSA_KEY_P384_L
|| purpose == ESP_EFUSE_KEY_PURPOSE_ECDSA_KEY_P384_H
#endif
#if SOC_PSRAM_ENCRYPTION_XTS_AES_128 || EFUSE_LL_HAS_PSRAM_ENCRYPTION_XTS_AES_128
purpose == ESP_EFUSE_KEY_PURPOSE_XTS_AES_128_PSRAM_KEY ||
|| purpose == ESP_EFUSE_KEY_PURPOSE_XTS_AES_128_PSRAM_KEY
#endif
#if SOC_PSRAM_ENCRYPTION_XTS_AES_256 || EFUSE_LL_HAS_PSRAM_ENCRYPTION_XTS_AES_256
purpose == ESP_EFUSE_KEY_PURPOSE_XTS_AES_256_PSRAM_KEY_1 ||
purpose == ESP_EFUSE_KEY_PURPOSE_XTS_AES_256_PSRAM_KEY_2 ||
|| purpose == ESP_EFUSE_KEY_PURPOSE_XTS_AES_256_PSRAM_KEY_1
|| purpose == ESP_EFUSE_KEY_PURPOSE_XTS_AES_256_PSRAM_KEY_2
#endif
#if SOC_HMAC_SUPPORTED
|| purpose == ESP_EFUSE_KEY_PURPOSE_HMAC_DOWN_ALL
|| purpose == ESP_EFUSE_KEY_PURPOSE_HMAC_DOWN_JTAG
|| purpose == ESP_EFUSE_KEY_PURPOSE_HMAC_DOWN_DIGITAL_SIGNATURE
|| purpose == ESP_EFUSE_KEY_PURPOSE_HMAC_UP
#endif
purpose == ESP_EFUSE_KEY_PURPOSE_HMAC_DOWN_ALL ||
purpose == ESP_EFUSE_KEY_PURPOSE_HMAC_DOWN_JTAG ||
purpose == ESP_EFUSE_KEY_PURPOSE_HMAC_DOWN_DIGITAL_SIGNATURE ||
#if SOC_KEY_MANAGER_SUPPORTED
purpose == ESP_EFUSE_KEY_PURPOSE_KM_INIT_KEY ||
|| purpose == ESP_EFUSE_KEY_PURPOSE_KM_INIT_KEY
#endif
purpose == ESP_EFUSE_KEY_PURPOSE_HMAC_UP) {
) {
TEST_ASSERT_TRUE(esp_efuse_get_key_dis_read(num_key));
#if CONFIG_EFUSE_FPGA_TEST && !CONFIG_EFUSE_VIRTUAL
TEST_ASSERT_EACH_EQUAL_HEX8(0, rd_key, sizeof(rd_key));
@@ -236,7 +239,11 @@ TEST_CASE("Test 1 esp_efuse_write_key for FPGA", "[efuse]")
ESP_EFUSE_KEY_PURPOSE_XTS_AES_128_KEY,
#endif
ESP_EFUSE_KEY_PURPOSE_XTS_AES_128_KEY,
#if SOC_HMAC_SUPPORTED
ESP_EFUSE_KEY_PURPOSE_HMAC_DOWN_ALL,
#else
ESP_EFUSE_KEY_PURPOSE_XTS_AES_128_KEY,
#endif
};
int max_keys = EFUSE_BLK_KEY_MAX - EFUSE_BLK_KEY0;
@@ -264,9 +271,15 @@ TEST_CASE("Test 2 esp_efuse_write_key for FPGA", "[efuse]")
TEST_ASSERT_EQUAL_MESSAGE(EFUSE_BLK_KEY_MAX - EFUSE_BLK_KEY0, esp_efuse_count_unused_key_blocks(), "Efuses should be in initial state");
esp_efuse_purpose_t purpose [] = {
#if SOC_HMAC_SUPPORTED
ESP_EFUSE_KEY_PURPOSE_HMAC_DOWN_JTAG,
ESP_EFUSE_KEY_PURPOSE_HMAC_DOWN_DIGITAL_SIGNATURE,
ESP_EFUSE_KEY_PURPOSE_HMAC_UP,
#else
ESP_EFUSE_KEY_PURPOSE_XTS_AES_128_KEY,
ESP_EFUSE_KEY_PURPOSE_XTS_AES_128_KEY,
ESP_EFUSE_KEY_PURPOSE_XTS_AES_128_KEY,
#endif
ESP_EFUSE_KEY_PURPOSE_SECURE_BOOT_DIGEST0,
ESP_EFUSE_KEY_PURPOSE_SECURE_BOOT_DIGEST1,
ESP_EFUSE_KEY_PURPOSE_SECURE_BOOT_DIGEST2,
@@ -312,7 +325,11 @@ TEST_CASE("Test esp_efuse_write_keys", "[efuse]")
#else
esp_efuse_purpose_t purpose1[BLOCKS_NEEDED1] = {
ESP_EFUSE_KEY_PURPOSE_XTS_AES_128_KEY,
#if SOC_HMAC_SUPPORTED
ESP_EFUSE_KEY_PURPOSE_HMAC_DOWN_ALL
#else
ESP_EFUSE_KEY_PURPOSE_USER
#endif
};
#endif
uint8_t keys1[BLOCKS_NEEDED1][32] = {{0xEE}};