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feat(espefuse): Adds efuses for esp32h2 eco5

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- Support efuses that are not present in the main efuse table
This commit is contained in:
Konstantin Kondrashov
2025-01-08 11:16:49 +02:00
parent d43f647f80
commit a98c20d4e0
13 changed files with 255 additions and 70 deletions
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components/efuse/esp32h2/esp_efuse_table.csv
+9 -3
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@@ -9,7 +9,7 @@
# this will generate new source files, next rebuild all the sources.
# !!!!!!!!!!! #
# This file was generated by regtools.py based on the efuses.yaml file with the version: ef562916e77cf77203c1a4c0cff35ac5
# This file was generated by regtools.py based on the efuses.yaml file with the version: 44563d2af4ebdba4db6c0a34a50c94f9
WR_DIS, EFUSE_BLK0, 0, 32, [] Disable programming of individual eFuses
WR_DIS.RD_DIS, EFUSE_BLK0, 0, 1, [] wr_dis of RD_DIS
@@ -22,6 +22,7 @@ WR_DIS.DIS_TWAI, EFUSE_BLK0, 2, 1, [WR_DIS.D
WR_DIS.JTAG_SEL_ENABLE, EFUSE_BLK0, 2, 1, [] wr_dis of JTAG_SEL_ENABLE
WR_DIS.DIS_PAD_JTAG, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_PAD_JTAG
WR_DIS.DIS_DOWNLOAD_MANUAL_ENCRYPT, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_DOWNLOAD_MANUAL_ENCRYPT
WR_DIS.POWERGLITCH_EN1, EFUSE_BLK0, 2, 1, [] wr_dis of POWERGLITCH_EN1
WR_DIS.WDT_DELAY_SEL, EFUSE_BLK0, 3, 1, [] wr_dis of WDT_DELAY_SEL
WR_DIS.SPI_BOOT_CRYPT_CNT, EFUSE_BLK0, 4, 1, [] wr_dis of SPI_BOOT_CRYPT_CNT
WR_DIS.SECURE_BOOT_KEY_REVOKE0, EFUSE_BLK0, 5, 1, [] wr_dis of SECURE_BOOT_KEY_REVOKE0
@@ -33,11 +34,13 @@ WR_DIS.KEY_PURPOSE_2, EFUSE_BLK0, 10, 1, [WR_DIS.K
WR_DIS.KEY_PURPOSE_3, EFUSE_BLK0, 11, 1, [WR_DIS.KEY3_PURPOSE] wr_dis of KEY_PURPOSE_3
WR_DIS.KEY_PURPOSE_4, EFUSE_BLK0, 12, 1, [WR_DIS.KEY4_PURPOSE] wr_dis of KEY_PURPOSE_4
WR_DIS.KEY_PURPOSE_5, EFUSE_BLK0, 13, 1, [WR_DIS.KEY5_PURPOSE] wr_dis of KEY_PURPOSE_5
WR_DIS.XTS_DPA_PSEUDO_LEVEL, EFUSE_BLK0, 14, 1, [] wr_dis of XTS_DPA_PSEUDO_LEVEL
WR_DIS.SEC_DPA_LEVEL, EFUSE_BLK0, 14, 1, [] wr_dis of SEC_DPA_LEVEL
WR_DIS.CRYPT_DPA_ENABLE, EFUSE_BLK0, 14, 1, [] wr_dis of CRYPT_DPA_ENABLE
WR_DIS.SECURE_BOOT_EN, EFUSE_BLK0, 15, 1, [] wr_dis of SECURE_BOOT_EN
WR_DIS.SECURE_BOOT_AGGRESSIVE_REVOKE, EFUSE_BLK0, 16, 1, [] wr_dis of SECURE_BOOT_AGGRESSIVE_REVOKE
WR_DIS.ECDSA_FORCE_USE_HARDWARE_K, EFUSE_BLK0, 17, 1, [] wr_dis of ECDSA_FORCE_USE_HARDWARE_K
WR_DIS.ECDSA_CURVE_MODE, EFUSE_BLK0, 17, 1, [] wr_dis of ECDSA_CURVE_MODE
WR_DIS.ECC_FORCE_CONST_TIME, EFUSE_BLK0, 17, 1, [] wr_dis of ECC_FORCE_CONST_TIME
WR_DIS.FLASH_TPUW, EFUSE_BLK0, 18, 1, [] wr_dis of FLASH_TPUW
WR_DIS.DIS_DOWNLOAD_MODE, EFUSE_BLK0, 18, 1, [] wr_dis of DIS_DOWNLOAD_MODE
WR_DIS.DIS_DIRECT_BOOT, EFUSE_BLK0, 18, 1, [] wr_dis of DIS_DIRECT_BOOT
@@ -118,6 +121,9 @@ DIS_PAD_JTAG, EFUSE_BLK0, 51, 1, [] Repres
DIS_DOWNLOAD_MANUAL_ENCRYPT, EFUSE_BLK0, 52, 1, [] Represents whether flash encrypt function is disabled or enabled(except in SPI boot mode). 1: disabled. 0: enabled
USB_EXCHG_PINS, EFUSE_BLK0, 57, 1, [] Represents whether the D+ and D- pins is exchanged. 1: exchanged. 0: not exchanged
VDD_SPI_AS_GPIO, EFUSE_BLK0, 58, 1, [] Represents whether vdd spi pin is functioned as gpio. 1: functioned. 0: not functioned
ECDSA_CURVE_MODE, EFUSE_BLK0, 59, 2, [] Configures the curve of ECDSA calculation: 0: only enable P256. 1: only enable P192. 2: both enable P256 and P192. 3: only enable P256
ECC_FORCE_CONST_TIME, EFUSE_BLK0, 61, 1, [] Set this bit to permanently turn on ECC const-time mode
XTS_DPA_PSEUDO_LEVEL, EFUSE_BLK0, 62, 2, [] Set this bit to control the xts pseudo-round anti-dpa attack function: 0: controlled by register. 1-3: the higher the value is; the more pseudo-rounds are inserted to the xts-aes calculation
WDT_DELAY_SEL, EFUSE_BLK0, 80, 2, [] Represents whether RTC watchdog timeout threshold is selected at startup. 1: selected. 0: not selected
SPI_BOOT_CRYPT_CNT, EFUSE_BLK0, 82, 3, [] Enables flash encryption when 1 or 3 bits are set and disables otherwise {0: "Disable"; 1: "Enable"; 3: "Disable"; 7: "Enable"}
SECURE_BOOT_KEY_REVOKE0, EFUSE_BLK0, 85, 1, [] Revoke 1st secure boot key
@@ -130,10 +136,10 @@ KEY_PURPOSE_3, EFUSE_BLK0, 100, 4, [KEY3_PUR
KEY_PURPOSE_4, EFUSE_BLK0, 104, 4, [KEY4_PURPOSE] Represents the purpose of Key4
KEY_PURPOSE_5, EFUSE_BLK0, 108, 4, [KEY5_PURPOSE] Represents the purpose of Key5
SEC_DPA_LEVEL, EFUSE_BLK0, 112, 2, [] Represents the spa secure level by configuring the clock random divide mode
ECDSA_FORCE_USE_HARDWARE_K, EFUSE_BLK0, 114, 1, [] Represents whether hardware random number k is forced used in ESDCA. 1: force used. 0: not force used
CRYPT_DPA_ENABLE, EFUSE_BLK0, 115, 1, [] Represents whether anti-dpa attack is enabled. 1:enabled. 0: disabled
SECURE_BOOT_EN, EFUSE_BLK0, 116, 1, [] Represents whether secure boot is enabled or disabled. 1: enabled. 0: disabled
SECURE_BOOT_AGGRESSIVE_REVOKE, EFUSE_BLK0, 117, 1, [] Represents whether revoking aggressive secure boot is enabled or disabled. 1: enabled. 0: disabled
POWERGLITCH_EN1, EFUSE_BLK0, 118, 5, [] Set these bits to enable power glitch function when chip power on
FLASH_TPUW, EFUSE_BLK0, 124, 4, [] Represents the flash waiting time after power-up; in unit of ms. When the value less than 15; the waiting time is the programmed value. Otherwise; the waiting time is 2 times the programmed value
DIS_DOWNLOAD_MODE, EFUSE_BLK0, 128, 1, [] Represents whether Download mode is disabled or enabled. 1: disabled. 0: enabled
DIS_DIRECT_BOOT, EFUSE_BLK0, 129, 1, [] Represents whether direct boot mode is disabled or enabled. 1: disabled. 0: enabled
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