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feat(ana_cmpr): supported analog comparator on esp32p4

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This commit is contained in:
laokaiyao
2023-09-25 19:57:34 +08:00
parent b953afe030
commit a989ce4ab1
18 changed files with 377 additions and 66 deletions
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components/soc/esp32h2/ana_cmpr_periph.c
+1
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@@ -10,5 +10,6 @@ const ana_cmpr_conn_t ana_cmpr_io_map[SOC_ANA_CMPR_NUM] = {
[0] = {
.src_gpio = ANA_CMPR0_SRC_GPIO,
.ext_ref_gpio = ANA_CMPR0_EXT_REF_GPIO,
.intr_src = ETS_GPIO_INTR_SOURCE,
},
};
components/soc/esp32p4/ana_cmpr_periph.c
+38
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@@ -0,0 +1,38 @@
/*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/ana_cmpr_periph.h"
#include "soc/ana_cmpr_struct.h"
const ana_cmpr_conn_t ana_cmpr_io_map[SOC_ANA_CMPR_NUM] = {
[0] = {
.src_gpio = ANA_CMPR0_SRC_GPIO,
.ext_ref_gpio = ANA_CMPR0_EXT_REF_GPIO,
.intr_src = ETS_GPIO_PAD_COMP_INTR_SOURCE,
},
[1] = {
.src_gpio = ANA_CMPR1_SRC_GPIO,
.ext_ref_gpio = ANA_CMPR1_EXT_REF_GPIO,
.intr_src = ETS_GPIO_PAD_COMP_INTR_SOURCE,
},
};
analog_cmpr_dev_t ANALOG_CMPR[SOC_ANA_CMPR_NUM] = {
[0] = {
.pad_comp_config = &LP_SYS.pad_comp[0],
.pad_comp_filter = &GPIO.zero_det_filter_cnt[0],
.int_st = &GPIO.int_st,
.int_ena = &GPIO.int_ena,
.int_clr = &GPIO.int_clr,
},
[1] = {
.pad_comp_config = &LP_SYS.pad_comp[1],
.pad_comp_filter = &GPIO.zero_det_filter_cnt[1],
.int_st = &GPIO.int_st,
.int_ena = &GPIO.int_ena,
.int_clr = &GPIO.int_clr,
},
};
components/soc/esp32p4/include/soc/Kconfig.soc_caps.in
+12
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@@ -3,6 +3,10 @@
# using gen_soc_caps_kconfig.py, do not edit manually
#####################################################
config SOC_ANA_CMPR_SUPPORTED
bool
default y
config SOC_UART_SUPPORTED
bool
default y
@@ -383,6 +387,14 @@ config SOC_DEDIC_PERIPH_ALWAYS_ENABLE
bool
default y
config SOC_ANA_CMPR_NUM
int
default 2
config SOC_ANA_CMPR_SUPPORT_MULTI_INTR
bool
default y
config SOC_I2C_NUM
int
default 2
components/soc/esp32p4/include/soc/ana_cmpr_channel.h
+12
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@@ -0,0 +1,12 @@
/*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#define ANA_CMPR0_EXT_REF_GPIO 51 /*!< The GPIO that can be used as external reference voltage */
#define ANA_CMPR0_SRC_GPIO 52 /*!< The GPIO that used for inputting the source signal to compare */
#define ANA_CMPR1_EXT_REF_GPIO 53 /*!< The GPIO that can be used as external reference voltage */
#define ANA_CMPR1_SRC_GPIO 54 /*!< The GPIO that used for inputting the source signal to compare */
components/soc/esp32p4/include/soc/ana_cmpr_struct.h
+37
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@@ -0,0 +1,37 @@
/**
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
/* NOTE: this file is created manually for compatibility */
#pragma once
#include <stdint.h>
#include "soc/gpio_struct.h"
#include "soc/lp_system_struct.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief The Analog Comparator Device struct
* @note The field in it are register pointers, which point to the physical address
* of the corresponding configuration register
* @note see 'ana_cmpr_periph.c' for the device instance
*/
typedef struct {
volatile lp_system_reg_pad_comp_reg_t *pad_comp_config;
volatile gpio_zero_det_filter_cnt_reg_t *pad_comp_filter;
volatile gpio_int_st_reg_t *int_st;
volatile gpio_int_ena_reg_t *int_ena;
volatile gpio_int_clr_reg_t *int_clr;
} analog_cmpr_dev_t;
extern analog_cmpr_dev_t ANALOG_CMPR[2];
#ifdef __cplusplus
}
#endif
components/soc/esp32p4/include/soc/clk_tree_defs.h
+16
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@@ -405,6 +405,22 @@ typedef enum {
//////////////////////////////////////////////////GPIO Glitch Filter////////////////////////////////////////////////////
///////////////////////////////////////////////////Analog Comparator////////////////////////////////////////////////////
/**
* @brief Array initializer for all supported clock sources of Analog Comparator
*/
#define SOC_ANA_CMPR_CLKS {SOC_MOD_CLK_PLL_F80M, SOC_MOD_CLK_XTAL}
/**
* @brief Sigma Delta Modulator clock source
*/
typedef enum {
ANA_CMPR_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL clock as the source clock */
ANA_CMPR_CLK_SRC_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M clock as the source clock */
ANA_CMPR_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M as the default clock choice */
} soc_periph_ana_cmpr_clk_src_t;
//////////////////////////////////////////////////TWAI//////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////ADC///////////////////////////////////////////////////////////////////
components/soc/esp32p4/include/soc/gpio_struct.h
+4 -18
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@@ -558,26 +558,13 @@ typedef union {
*/
typedef union {
struct {
/** zero_det0_filter_cnt : R/W; bitpos: [31:0]; default: 4294967295;
/** zero_det_filter_cnt : R/W; bitpos: [31:0]; default: 4294967295;
* GPIO analog comparator zero detect filter count
*/
uint32_t zero_det0_filter_cnt:32;
uint32_t zero_det_filter_cnt:32;
};
uint32_t val;
} gpio_zero_det0_filter_cnt_reg_t;
/** Type of zero_det1_filter_cnt register
* GPIO analog comparator zero detect filter count
*/
typedef union {
struct {
/** zero_det1_filter_cnt : R/W; bitpos: [31:0]; default: 4294967295;
* GPIO analog comparator zero detect filter count
*/
uint32_t zero_det1_filter_cnt:32;
};
uint32_t val;
} gpio_zero_det1_filter_cnt_reg_t;
} gpio_zero_det_filter_cnt_reg_t;
/** Type of send_seq register
* High speed sdio pad bist send sequence
@@ -871,8 +858,7 @@ typedef struct gpio_dev_t {
volatile gpio_int_st_reg_t int_st;
volatile gpio_int_ena_reg_t int_ena;
volatile gpio_int_clr_reg_t int_clr;
volatile gpio_zero_det0_filter_cnt_reg_t zero_det0_filter_cnt;
volatile gpio_zero_det1_filter_cnt_reg_t zero_det1_filter_cnt;
volatile gpio_zero_det_filter_cnt_reg_t zero_det_filter_cnt[2];
volatile gpio_send_seq_reg_t send_seq;
volatile gpio_recive_seq_reg_t recive_seq;
volatile gpio_bistin_sel_reg_t bistin_sel;
components/soc/esp32p4/include/soc/lp_system_struct.h
+9 -31
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@@ -677,44 +677,22 @@ typedef union {
*/
typedef union {
struct {
/** dref_comp0 : R/W; bitpos: [2:0]; default: 0;
/** dref_comp : R/W; bitpos: [2:0]; default: 0;
* pad comp dref
*/
uint32_t dref_comp0:3;
/** mode_comp0 : R/W; bitpos: [3]; default: 0;
uint32_t dref_comp:3;
/** mode_comp : R/W; bitpos: [3]; default: 0;
* pad comp mode
*/
uint32_t mode_comp0:1;
/** xpd_comp0 : R/W; bitpos: [4]; default: 0;
uint32_t mode_comp:1;
/** xpd_comp : R/W; bitpos: [4]; default: 0;
* pad comp xpd
*/
uint32_t xpd_comp0:1;
uint32_t xpd_comp:1;
uint32_t reserved_5:27;
};
uint32_t val;
} lp_system_reg_pad_comp0_reg_t;
/** Type of pad_comp1 register
* need_des
*/
typedef union {
struct {
/** dref_comp1 : R/W; bitpos: [2:0]; default: 0;
* pad comp dref
*/
uint32_t dref_comp1:3;
/** mode_comp1 : R/W; bitpos: [3]; default: 0;
* pad comp mode
*/
uint32_t mode_comp1:1;
/** xpd_comp1 : R/W; bitpos: [4]; default: 0;
* pad comp xpd
*/
uint32_t xpd_comp1:1;
uint32_t reserved_5:27;
};
uint32_t val;
} lp_system_reg_pad_comp1_reg_t;
} lp_system_reg_pad_comp_reg_t;
/** Type of backup_dma_cfg0 register
* need_des
@@ -1291,8 +1269,7 @@ typedef struct {
volatile lp_system_reg_lp_pmu_rdn_eco_low_reg_t lp_pmu_rdn_eco_low;
volatile lp_system_reg_lp_pmu_rdn_eco_high_reg_t lp_pmu_rdn_eco_high;
uint32_t reserved_140[2];
volatile lp_system_reg_pad_comp0_reg_t pad_comp0;
volatile lp_system_reg_pad_comp1_reg_t pad_comp1;
volatile lp_system_reg_pad_comp_reg_t pad_comp[2];
uint32_t reserved_150;
volatile lp_system_reg_backup_dma_cfg0_reg_t backup_dma_cfg0;
volatile lp_system_reg_backup_dma_cfg1_reg_t backup_dma_cfg1;
@@ -1323,6 +1300,7 @@ typedef struct {
volatile lp_system_reg_rng_cfg_reg_t rng_cfg;
} lp_system_reg_dev_t;
extern lp_system_reg_dev_t LP_SYS;
#ifndef __cplusplus
_Static_assert(sizeof(lp_system_reg_dev_t) == 0x1c4, "Invalid size of lp_system_reg_dev_t structure");
components/soc/esp32p4/include/soc/soc_caps.h
+5 -1
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@@ -26,7 +26,7 @@
/*-------------------------- COMMON CAPS ---------------------------------------*/
// #define SOC_ADC_SUPPORTED 1 //TODO: IDF-6496
// #define SOC_ANA_CMPR_SUPPORTED 1 //TODO: IDF-7479
#define SOC_ANA_CMPR_SUPPORTED 1
// #define SOC_DEDICATED_GPIO_SUPPORTED 1 //TODO: IDF-7552
#define SOC_UART_SUPPORTED 1
#define SOC_GDMA_SUPPORTED 1
@@ -220,6 +220,10 @@
#define SOC_DEDIC_GPIO_IN_CHANNELS_NUM (8) /*!< 8 inward channels on each CPU core */
#define SOC_DEDIC_PERIPH_ALWAYS_ENABLE (1) /*!< The dedicated GPIO (a.k.a. fast GPIO) is featured by some customized CPU instructions, which is always enabled */
/*------------------------- Analog Comparator CAPS ---------------------------*/
#define SOC_ANA_CMPR_NUM (2U)
#define SOC_ANA_CMPR_SUPPORT_MULTI_INTR (1)
/*-------------------------- I2C CAPS ----------------------------------------*/
// ESP32-P4 has 2 I2Cs
#define SOC_I2C_NUM (2U)
components/soc/esp32p4/ld/esp32p4.peripherals.ld
+1
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@@ -65,6 +65,7 @@ PROVIDE ( TEE = 0x60098000 ); /* TODO: IDF-7542 */
PROVIDE ( HP_APM = 0x60099000 ); /* TODO: IDF-7542 */
PROVIDE ( PMU = 0x50115000 );
PROVIDE ( LP_SYS = 0x50110000 );
PROVIDE ( LP_AON_CLKRST = 0x50111000 );
PROVIDE ( EFUSE = 0x5012D000 );
PROVIDE ( LP_TIMER = 0x50112000 );
components/soc/include/soc/ana_cmpr_periph.h
+2
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@@ -8,6 +8,7 @@
#include <stdint.h>
#include "soc/soc_caps.h"
#include "soc/periph_defs.h"
#if SOC_ANA_CMPR_SUPPORTED
#include "soc/ana_cmpr_channel.h"
#endif
@@ -20,6 +21,7 @@ extern "C" {
typedef struct {
int src_gpio;
int ext_ref_gpio;
int intr_src;
} ana_cmpr_conn_t;
extern const ana_cmpr_conn_t ana_cmpr_io_map[SOC_ANA_CMPR_NUM];