feat(p4): p4 rev3 soc support

components/hal/cache_hal.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2021-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */

components/hal/esp32p4/include/hal/uart_ll.h

@@ -10,6 +10,7 @@
 
 #pragma once
 
+#include <stdint.h>
 #include "esp_attr.h"
 #include "hal/misc.h"
 #include "hal/assert.h"

components/hal/esp32p4/include/hal/usb_serial_jtag_ll.h

@@ -120,7 +120,7 @@ static inline int usb_serial_jtag_ll_read_rxfifo(uint8_t *buf, uint32_t rd_len)
     int i;
     for (i = 0; i < (int)rd_len; i++) {
         if (!USB_SERIAL_JTAG.ep1_conf.serial_out_ep_data_avail) break;
-        buf[i] = USB_SERIAL_JTAG.ep1.rdwr_byte;
+        buf[i] = HAL_FORCE_READ_U32_REG_FIELD(USB_SERIAL_JTAG.ep1, rdwr_byte);
     }
     return i;
 }
@@ -139,7 +139,7 @@ static inline int usb_serial_jtag_ll_write_txfifo(const uint8_t *buf, uint32_t w
     int i;
     for (i = 0; i < (int)wr_len; i++) {
         if (!USB_SERIAL_JTAG.ep1_conf.serial_in_ep_data_free) break;
-        USB_SERIAL_JTAG.ep1.rdwr_byte = buf[i];
+        HAL_FORCE_MODIFY_U32_REG_FIELD(USB_SERIAL_JTAG.ep1, rdwr_byte, buf[i]);
     }
     return i;
 }

components/soc/CMakeLists.txt

@@ -18,11 +18,16 @@ if(EXISTS "${CMAKE_CURRENT_SOURCE_DIR}/${target_folder}/include")
     list(APPEND includes "${target_folder}/include")
 endif()
 
-if(EXISTS "${CMAKE_CURRENT_SOURCE_DIR}/${target_folder}/register")
+# register headers that generated by script from CSV
-    # register headers that generated by script from CSV
+if(CONFIG_IDF_TARGET_ESP32P4)
+    list(APPEND includes "${target_folder}/register/hw_ver1")
+else()
+    if(EXISTS "${CMAKE_CURRENT_SOURCE_DIR}/${target_folder}/register")
         list(APPEND includes "${target_folder}/register")
+    endif()
 endif()
 
+
 if(target STREQUAL "esp32")
     list(APPEND srcs "${target_folder}/dport_access.c")
 endif()

components/soc/esp32p4/include/soc/soc.h

@@ -224,6 +224,7 @@
 #define SOC_CPU_SUBSYSTEM_HIGH 0x30000000
 
 // Start (highest address) of ROM boot stack, only relevant during early boot
+#define SOC_ROM_STACK_START_REV2    0x4ffbcfc0
 #define SOC_ROM_STACK_START         0x4ff3cfc0
 #define SOC_ROM_STACK_SIZE          0x2000