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refactor(hal/usb): Remove usb_fsls_phy_ll.h

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For targets that only contain a USJ peripheral (and not a DWC OTG), their
'usb_fsls_phy_ll.h' headers only contain a single function
('usb_fsls_phy_ll_int_jtag_enable()') whose feature is already covered by
functions in 'usb_serial_jtag_ll.h'. Thus, this header is redundant.

This commit does the following:

- Remove 'usb_fsls_phy_ll.h' for targets that only contain a USJ peripheral
- Rename 'usb_fsls_phy_[hal|ll].[h|c]' to `usb_wrap_[hal|ll].[h|c]` for targets
that contain a DWC OTG peripheral. This better reflects the underlying peripheral
that the LL header accesses.
This commit is contained in:
Darian Leung
2024-03-18 19:23:43 +08:00
parent 5d091a9bb3
commit a77e5cc718
15 changed files with 30 additions and 160 deletions
Download Patch File Download Diff File Expand all files Collapse all files
components/hal/CMakeLists.txt
+1 -1
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@@ -258,7 +258,7 @@ if(NOT BOOTLOADER_BUILD)
if(CONFIG_SOC_USB_OTG_SUPPORTED)
list(APPEND srcs "usb_dwc_hal.c")
if(NOT ${target} STREQUAL "esp32p4")
list(APPEND srcs "usb_fsls_phy_hal.c")
list(APPEND srcs "usb_wrap_hal.c")
endif()
endif()
components/hal/esp32c3/include/hal/usb_fsls_phy_ll.h
-47
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@@ -1,47 +0,0 @@
/*
* SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include "soc/usb_serial_jtag_struct.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief Configures the internal PHY for USB_Serial_JTAG
*
* @param hw Start address of the USB Serial_JTAG registers
*/
static inline void usb_fsls_phy_ll_int_jtag_enable(usb_serial_jtag_dev_t *hw)
{
// USB_Serial_JTAG use internal PHY
hw->conf0.phy_sel = 0;
// Disable software control USB D+ D- pullup pulldown (Device FS: dp_pullup = 1)
hw->conf0.pad_pull_override = 0;
// Enable USB D+ pullup
hw->conf0.dp_pullup = 1;
// Enable USB pad function
hw->conf0.usb_pad_enable = 1;
}
/**
* @brief Disable the internal PHY for USB_Serial_JTAG
*
* @param hw Start address of the USB Serial_JTAG registers
*/
static inline void usb_fsls_phy_ll_int_jtag_disable(usb_serial_jtag_dev_t *hw)
{
// Disable USB D+ pullup
hw->conf0.dp_pullup = 0;
// Disable USB pad function
hw->conf0.usb_pad_enable = 0;
}
#ifdef __cplusplus
}
#endif
components/hal/esp32c6/include/hal/usb_fsls_phy_ll.h
-47
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@@ -1,47 +0,0 @@
/*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include "soc/usb_serial_jtag_struct.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief Configures the internal PHY for USB_Serial_JTAG
*
* @param hw Start address of the USB Serial_JTAG registers
*/
static inline void usb_fsls_phy_ll_int_jtag_enable(usb_serial_jtag_dev_t *hw)
{
// USB_Serial_JTAG use internal PHY
hw->conf0.phy_sel = 0;
// Disable software control USB D+ D- pullup pulldown (Device FS: dp_pullup = 1)
hw->conf0.pad_pull_override = 0;
// Enable USB D+ pullup
hw->conf0.dp_pullup = 1;
// Enable USB pad function
hw->conf0.usb_pad_enable = 1;
}
/**
* @brief Disable the internal PHY for USB_Serial_JTAG
*
* @param hw Start address of the USB Serial_JTAG registers
*/
static inline void usb_fsls_phy_ll_int_jtag_disable(usb_serial_jtag_dev_t *hw)
{
// Disable USB D+ pullup
hw->conf0.dp_pullup = 0;
// Disable USB pad function
hw->conf0.usb_pad_enable = 0;
}
#ifdef __cplusplus
}
#endif
components/hal/esp32h2/include/hal/usb_fsls_phy_ll.h
-47
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@@ -1,47 +0,0 @@
/*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include "soc/usb_serial_jtag_struct.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief Configures the internal PHY for USB_Serial_JTAG
*
* @param hw Start address of the USB Serial_JTAG registers
*/
static inline void usb_fsls_phy_ll_int_jtag_enable(usb_serial_jtag_dev_t *hw)
{
// USB_Serial_JTAG use internal PHY
hw->conf0.phy_sel = 0;
// Disable software control USB D+ D- pullup pulldown (Device FS: dp_pullup = 1)
hw->conf0.pad_pull_override = 0;
// Enable USB D+ pullup
hw->conf0.dp_pullup = 1;
// Enable USB pad function
hw->conf0.usb_pad_enable = 1;
}
/**
* @brief Disable the internal PHY for USB_Serial_JTAG
*
* @param hw Start address of the USB Serial_JTAG registers
*/
static inline void usb_fsls_phy_ll_int_jtag_disable(usb_serial_jtag_dev_t *hw)
{
// Disable USB D+ pullup
hw->conf0.dp_pullup = 0;
// Disable USB pad function
hw->conf0.usb_pad_enable = 0;
}
#ifdef __cplusplus
}
#endif
components/hal/esp32s2/include/hal/usb_fsls_phy_ll.h → components/hal/esp32s2/include/hal/usb_wrap_ll.h
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components/hal/esp32s3/include/hal/usb_fsls_phy_ll.h → components/hal/esp32s3/include/hal/usb_wrap_ll.h
View File
components/hal/include/hal/usb_fsls_phy_hal.h → components/hal/include/hal/usb_wrap_hal.h
View File
components/hal/usb_fsls_phy_hal.c → components/hal/usb_wrap_hal.c
+18 -4
View File
@@ -4,8 +4,13 @@
* SPDX-License-Identifier: Apache-2.0
*/
#include "hal/usb_fsls_phy_ll.h"
#include "hal/usb_fsls_phy_hal.h"
#include "soc/soc_caps.h"
#include "soc/rtc_cntl_struct.h"
#if SOC_USB_SERIAL_JTAG_SUPPORTED
#include "hal/usb_serial_jtag_ll.h"
#endif
#include "hal/usb_wrap_ll.h"
#include "hal/usb_wrap_hal.h"
void usb_fsls_phy_hal_init(usb_fsls_phy_hal_context_t *hal)
{
@@ -29,9 +34,18 @@ void usb_fsls_phy_hal_otg_conf(usb_fsls_phy_hal_context_t *hal, usb_phy_target_t
void usb_fsls_phy_hal_jtag_conf(usb_fsls_phy_hal_context_t *hal, usb_phy_target_t phy_target)
{
if (phy_target == USB_PHY_TARGET_EXT) {
usb_fsls_phy_ll_ext_jtag_enable(hal->jtag_dev);
usb_serial_jtag_ll_phy_enable_external(true); // USJ uses external PHY
// Enable SW control of muxing USB OTG vs USJ to the internal USB FSLS PHY
RTCCNTL.usb_conf.sw_hw_usb_phy_sel = 1;
// Internal USB FSLS PHY is mapped to the USJ
RTCCNTL.usb_conf.sw_usb_phy_sel = 1;
} else if (phy_target == USB_PHY_TARGET_INT) {
usb_fsls_phy_ll_int_jtag_enable(hal->jtag_dev);
usb_serial_jtag_ll_phy_enable_external(true); // USJ uses internal PHY
usb_serial_jtag_ll_phy_enable_pad(true); // Enable USB PHY pads
// Enable SW control of muxing USB OTG vs USJ to the internal USB FSLS PHY
RTCCNTL.usb_conf.sw_hw_usb_phy_sel = 1;
// Internal USB FSLS PHY is mapped to the USJ
RTCCNTL.usb_conf.sw_usb_phy_sel = 0;
}
}
#endif