feat(p4): p4 rev3 real chip support

This commit is contained in:
armando
2025-10-13 15:24:14 +08:00
parent ea4451d6b3
commit a70a29b7a6
266 changed files with 83 additions and 379739 deletions
-2
View File
@@ -251,7 +251,6 @@ menu "Hardware Settings"
config ESP_BRINGUP_BYPASS_CPU_CLK_SETTING
bool
default y if !SOC_CLK_TREE_SUPPORTED
default y if ESP32P4_REV_MIN_200 # TODO: IDF-13574
default n
help
This option is only used for new chip bringup, when
@@ -261,7 +260,6 @@ menu "Hardware Settings"
config ESP_BRINGUP_BYPASS_RANDOM_SETTING
bool
default y if !SOC_RNG_SUPPORTED
default y if ESP32P4_REV_MIN_200 # TODO: IDF-13574
default n
help
This option is only used for new chip bringup, when
@@ -1,13 +1,14 @@
comment "NOTE! Support of ESP32-P4 rev. <2.0 and >=2.0 is mutually exclusive"
comment "NOTE! Support of ESP32-P4 rev. <3.0 and >=3.0 is mutually exclusive"
comment "Read the help text of the option below for explanation"
config ESP32P4_SELECTS_REV_LESS_V2
bool "Select ESP32-P4 revisions <2.0 (No >=2.x Support)"
config ESP32P4_SELECTS_REV_LESS_V3
bool "Select ESP32-P4 revisions <3.0 (No >=3.x Support)"
default y
help
Select this option to support ESP32-P4 revisions 0.x and 1.x.
Revision 2.0 and revisions less than 2.0 have huge hardware difference.
Revisions higher than 2.0 (included) is not compatible with 0.x and 1.x.
Revisions higher than 3.0 (included) and revisions less than 3.0
have huge hardware difference.
Revisions higher than 3.0 (included) is not compatible with 0.x and 1.x.
choice ESP32P4_REV_MIN
prompt "Minimum Supported ESP32-P4 Revision"
@@ -21,18 +22,18 @@ choice ESP32P4_REV_MIN
this will also help to reduce binary size.
config ESP32P4_REV_MIN_0
depends on ESP32P4_SELECTS_REV_LESS_V2
depends on ESP32P4_SELECTS_REV_LESS_V3
bool "Rev v0.0"
config ESP32P4_REV_MIN_1
depends on ESP32P4_SELECTS_REV_LESS_V2
depends on ESP32P4_SELECTS_REV_LESS_V3
bool "Rev v0.1"
config ESP32P4_REV_MIN_100
depends on ESP32P4_SELECTS_REV_LESS_V2
depends on ESP32P4_SELECTS_REV_LESS_V3
bool "Rev v1.0"
config ESP32P4_REV_MIN_200
bool "Rev v2.0"
depends on !ESP32P4_SELECTS_REV_LESS_V2
select ESPTOOLPY_NO_STUB if (IDF_ENV_FPGA || IDF_ENV_BRINGUP)
config ESP32P4_REV_MIN_300
bool "Rev v3.0"
depends on !ESP32P4_SELECTS_REV_LESS_V3
select ESPTOOLPY_NO_STUB # TODO: IDF-13911
endchoice
config ESP32P4_REV_MIN_FULL
@@ -40,7 +41,7 @@ config ESP32P4_REV_MIN_FULL
default 0 if ESP32P4_REV_MIN_0
default 1 if ESP32P4_REV_MIN_1
default 100 if ESP32P4_REV_MIN_100
default 0 if ESP32P4_REV_MIN_200 # TODO: IDF-13410. To be updated to 200 when chip efuse is burnt
default 300 if ESP32P4_REV_MIN_300
config ESP_REV_MIN_FULL
int
@@ -50,7 +51,10 @@ config ESP_REV_MIN_FULL
# MAX Revision
#
comment "Maximum Supported ESP32-P4 Revision (Rev v2.99)"
comment "Maximum Supported ESP32-P4 Revision (Rev v1.99)"
depends on ESP32P4_SELECTS_REV_LESS_V3
comment "Maximum Supported ESP32-P4 Revision (Rev v3.99)"
depends on !ESP32P4_SELECTS_REV_LESS_V3
# Maximum revision that IDF supports.
# It can not be changed by user.
# Only Espressif can change it when a new version will be supported in IDF.
@@ -58,7 +62,8 @@ config ESP_REV_MIN_FULL
config ESP32P4_REV_MAX_FULL
int
default 199 #TODO: IDF-13574
default 399 if !ESP32P4_SELECTS_REV_LESS_V3
default 199 if ESP32P4_SELECTS_REV_LESS_V3
# keep in sync the "Maximum Supported Revision" description with this value
config ESP_REV_MAX_FULL
@@ -78,6 +83,6 @@ config ESP_EFUSE_BLOCK_REV_MIN_FULL
config ESP_EFUSE_BLOCK_REV_MAX_FULL
int
default 99
default 199
comment "Maximum Supported ESP32-P4 eFuse Block Revision (eFuse Block Rev v0.99)"
# The revision in the comment must correspond to the default value of ESP_EFUSE_BLOCK_REV_MAX_FULL
@@ -8,6 +8,7 @@
#include <stdbool.h>
#include <stddef.h>
#include <stdint.h>
#include "sdkconfig.h"
#include "soc/soc.h"
#include "soc/clk_tree_defs.h"
#include "hal/hal_utils.h"
@@ -189,6 +190,7 @@ typedef struct {
/**
* Default initializer for rtc_clk_config_t
*/
#if CONFIG_ESP32P4_SELECTS_REV_LESS_V3
#define RTC_CLK_CONFIG_DEFAULT() { \
.xtal_freq = CONFIG_XTAL_FREQ, \
.cpu_freq_mhz = 90, \
@@ -200,6 +202,19 @@ typedef struct {
.clk_8m_dfreq = RTC_CNTL_CK8M_DFREQ_DEFAULT, \
.rc32k_dfreq = RTC_CNTL_RC32K_DFREQ_DEFAULT, \
}
#else
#define RTC_CLK_CONFIG_DEFAULT() { \
.xtal_freq = CONFIG_XTAL_FREQ, \
.cpu_freq_mhz = 100, \
.fast_clk_src = SOC_RTC_FAST_CLK_SRC_RC_FAST, \
.slow_clk_src = SOC_RTC_SLOW_CLK_SRC_RC_SLOW, \
.clk_rtc_clk_div = 0, \
.clk_8m_clk_div = 0, \
.slow_clk_dcap = RTC_CNTL_SCK_DCAP_DEFAULT, \
.clk_8m_dfreq = RTC_CNTL_CK8M_DFREQ_DEFAULT, \
.rc32k_dfreq = RTC_CNTL_RC32K_DFREQ_DEFAULT, \
}
#endif
/**
* Initialize clocks and set CPU frequency
@@ -220,7 +220,7 @@ static void rtc_clk_cpu_freq_to_cpll_mhz(int cpu_freq_mhz, hal_utils_clk_div_t *
uint32_t mem_divider = 1;
uint32_t sys_divider = 1; // We are not going to change this
uint32_t apb_divider = 1;
#if CONFIG_ESP32P4_SELECTS_REV_LESS_V2
#if CONFIG_ESP32P4_SELECTS_REV_LESS_V3
switch (cpu_freq_mhz) {
case 360:
mem_divider = 2;
@@ -308,7 +308,7 @@ bool rtc_clk_cpu_freq_mhz_to_config(uint32_t freq_mhz, rtc_cpu_freq_config_t *ou
// Keep default CPLL at 360MHz
uint32_t xtal_freq = (uint32_t)rtc_clk_xtal_freq_get();
#if CONFIG_ESP32P4_SELECTS_REV_LESS_V2
#if CONFIG_ESP32P4_SELECTS_REV_LESS_V3
if (freq_mhz <= xtal_freq && freq_mhz != 0) {
divider.integer = xtal_freq / freq_mhz;
real_freq_mhz = (xtal_freq + divider.integer / 2) / divider.integer; /* round */