mirror of
https://github.com/espressif/esp-idf.git
synced 2026-10-03 03:31:41 +03:00
feat(p4): p4 rev3 real chip support
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@@ -251,7 +251,6 @@ menu "Hardware Settings"
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config ESP_BRINGUP_BYPASS_CPU_CLK_SETTING
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bool
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default y if !SOC_CLK_TREE_SUPPORTED
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default y if ESP32P4_REV_MIN_200 # TODO: IDF-13574
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default n
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help
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This option is only used for new chip bringup, when
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@@ -261,7 +260,6 @@ menu "Hardware Settings"
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config ESP_BRINGUP_BYPASS_RANDOM_SETTING
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bool
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default y if !SOC_RNG_SUPPORTED
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default y if ESP32P4_REV_MIN_200 # TODO: IDF-13574
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default n
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help
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This option is only used for new chip bringup, when
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@@ -1,13 +1,14 @@
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comment "NOTE! Support of ESP32-P4 rev. <2.0 and >=2.0 is mutually exclusive"
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comment "NOTE! Support of ESP32-P4 rev. <3.0 and >=3.0 is mutually exclusive"
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comment "Read the help text of the option below for explanation"
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config ESP32P4_SELECTS_REV_LESS_V2
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bool "Select ESP32-P4 revisions <2.0 (No >=2.x Support)"
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config ESP32P4_SELECTS_REV_LESS_V3
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bool "Select ESP32-P4 revisions <3.0 (No >=3.x Support)"
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default y
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help
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Select this option to support ESP32-P4 revisions 0.x and 1.x.
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Revision 2.0 and revisions less than 2.0 have huge hardware difference.
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Revisions higher than 2.0 (included) is not compatible with 0.x and 1.x.
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Revisions higher than 3.0 (included) and revisions less than 3.0
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have huge hardware difference.
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Revisions higher than 3.0 (included) is not compatible with 0.x and 1.x.
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choice ESP32P4_REV_MIN
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prompt "Minimum Supported ESP32-P4 Revision"
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@@ -21,18 +22,18 @@ choice ESP32P4_REV_MIN
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this will also help to reduce binary size.
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config ESP32P4_REV_MIN_0
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depends on ESP32P4_SELECTS_REV_LESS_V2
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depends on ESP32P4_SELECTS_REV_LESS_V3
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bool "Rev v0.0"
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config ESP32P4_REV_MIN_1
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depends on ESP32P4_SELECTS_REV_LESS_V2
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depends on ESP32P4_SELECTS_REV_LESS_V3
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bool "Rev v0.1"
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config ESP32P4_REV_MIN_100
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depends on ESP32P4_SELECTS_REV_LESS_V2
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depends on ESP32P4_SELECTS_REV_LESS_V3
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bool "Rev v1.0"
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config ESP32P4_REV_MIN_200
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bool "Rev v2.0"
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depends on !ESP32P4_SELECTS_REV_LESS_V2
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select ESPTOOLPY_NO_STUB if (IDF_ENV_FPGA || IDF_ENV_BRINGUP)
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config ESP32P4_REV_MIN_300
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bool "Rev v3.0"
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depends on !ESP32P4_SELECTS_REV_LESS_V3
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select ESPTOOLPY_NO_STUB # TODO: IDF-13911
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endchoice
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config ESP32P4_REV_MIN_FULL
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@@ -40,7 +41,7 @@ config ESP32P4_REV_MIN_FULL
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default 0 if ESP32P4_REV_MIN_0
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default 1 if ESP32P4_REV_MIN_1
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default 100 if ESP32P4_REV_MIN_100
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default 0 if ESP32P4_REV_MIN_200 # TODO: IDF-13410. To be updated to 200 when chip efuse is burnt
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default 300 if ESP32P4_REV_MIN_300
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config ESP_REV_MIN_FULL
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int
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@@ -50,7 +51,10 @@ config ESP_REV_MIN_FULL
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# MAX Revision
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#
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comment "Maximum Supported ESP32-P4 Revision (Rev v2.99)"
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comment "Maximum Supported ESP32-P4 Revision (Rev v1.99)"
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depends on ESP32P4_SELECTS_REV_LESS_V3
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comment "Maximum Supported ESP32-P4 Revision (Rev v3.99)"
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depends on !ESP32P4_SELECTS_REV_LESS_V3
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# Maximum revision that IDF supports.
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# It can not be changed by user.
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# Only Espressif can change it when a new version will be supported in IDF.
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@@ -58,7 +62,8 @@ config ESP_REV_MIN_FULL
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config ESP32P4_REV_MAX_FULL
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int
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default 199 #TODO: IDF-13574
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default 399 if !ESP32P4_SELECTS_REV_LESS_V3
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default 199 if ESP32P4_SELECTS_REV_LESS_V3
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# keep in sync the "Maximum Supported Revision" description with this value
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config ESP_REV_MAX_FULL
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@@ -78,6 +83,6 @@ config ESP_EFUSE_BLOCK_REV_MIN_FULL
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config ESP_EFUSE_BLOCK_REV_MAX_FULL
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int
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default 99
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default 199
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comment "Maximum Supported ESP32-P4 eFuse Block Revision (eFuse Block Rev v0.99)"
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# The revision in the comment must correspond to the default value of ESP_EFUSE_BLOCK_REV_MAX_FULL
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@@ -8,6 +8,7 @@
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#include <stdbool.h>
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#include <stddef.h>
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#include <stdint.h>
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#include "sdkconfig.h"
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#include "soc/soc.h"
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#include "soc/clk_tree_defs.h"
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#include "hal/hal_utils.h"
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@@ -189,6 +190,7 @@ typedef struct {
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/**
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* Default initializer for rtc_clk_config_t
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*/
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#if CONFIG_ESP32P4_SELECTS_REV_LESS_V3
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#define RTC_CLK_CONFIG_DEFAULT() { \
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.xtal_freq = CONFIG_XTAL_FREQ, \
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.cpu_freq_mhz = 90, \
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@@ -200,6 +202,19 @@ typedef struct {
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.clk_8m_dfreq = RTC_CNTL_CK8M_DFREQ_DEFAULT, \
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.rc32k_dfreq = RTC_CNTL_RC32K_DFREQ_DEFAULT, \
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}
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#else
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#define RTC_CLK_CONFIG_DEFAULT() { \
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.xtal_freq = CONFIG_XTAL_FREQ, \
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.cpu_freq_mhz = 100, \
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.fast_clk_src = SOC_RTC_FAST_CLK_SRC_RC_FAST, \
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.slow_clk_src = SOC_RTC_SLOW_CLK_SRC_RC_SLOW, \
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.clk_rtc_clk_div = 0, \
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.clk_8m_clk_div = 0, \
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.slow_clk_dcap = RTC_CNTL_SCK_DCAP_DEFAULT, \
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.clk_8m_dfreq = RTC_CNTL_CK8M_DFREQ_DEFAULT, \
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.rc32k_dfreq = RTC_CNTL_RC32K_DFREQ_DEFAULT, \
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}
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#endif
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/**
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* Initialize clocks and set CPU frequency
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@@ -220,7 +220,7 @@ static void rtc_clk_cpu_freq_to_cpll_mhz(int cpu_freq_mhz, hal_utils_clk_div_t *
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uint32_t mem_divider = 1;
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uint32_t sys_divider = 1; // We are not going to change this
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uint32_t apb_divider = 1;
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#if CONFIG_ESP32P4_SELECTS_REV_LESS_V2
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#if CONFIG_ESP32P4_SELECTS_REV_LESS_V3
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switch (cpu_freq_mhz) {
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case 360:
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mem_divider = 2;
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@@ -308,7 +308,7 @@ bool rtc_clk_cpu_freq_mhz_to_config(uint32_t freq_mhz, rtc_cpu_freq_config_t *ou
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// Keep default CPLL at 360MHz
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uint32_t xtal_freq = (uint32_t)rtc_clk_xtal_freq_get();
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#if CONFIG_ESP32P4_SELECTS_REV_LESS_V2
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#if CONFIG_ESP32P4_SELECTS_REV_LESS_V3
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if (freq_mhz <= xtal_freq && freq_mhz != 0) {
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divider.integer = xtal_freq / freq_mhz;
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real_freq_mhz = (xtal_freq + divider.integer / 2) / divider.integer; /* round */
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