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Merge branch 'ci/enable_sysview_tests_v5.2' into 'release/v5.2'

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ci: enable sysview example tests for all chips (v5.2)

See merge request espressif/esp-idf!39475
This commit is contained in:
Jiang Jiang Jian
2025-07-28 14:28:54 +08:00
parent 55644f7c6a 693e9ced04
commit a6ce7bb281
13 changed files with 292 additions and 405 deletions
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.gitlab/ci/target-test.yml
+12
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@@ -155,6 +155,18 @@ pytest_examples_esp32s2_jtag:
- .rules:test:example_test-esp32s2
tags: [ esp32s2, jtag ]
pytest_examples_esp32c6_usb_serial_jtag:
extends:
- .pytest_examples_dir_jtag_template
- .rules:test:example_test-esp32c6
tags: [ esp32c6, usb_serial_jtag ]
pytest_examples_esp32h2_usb_serial_jtag:
extends:
- .pytest_examples_dir_jtag_template
- .rules:test:example_test-esp32h2
tags: [ esp32h2, usb_serial_jtag ]
pytest_examples_esp32s3_generic:
extends:
- .pytest_examples_dir_template