mirror of
https://github.com/espressif/esp-idf.git
synced 2026-10-02 03:00:34 +03:00
Merge branch 'feat/sdmmc_s31' into 'master'
sdmmc: s31 support Closes IDF-14705 and IDF-14706 See merge request espressif/esp-idf!47232
This commit is contained in:
Armando (Dou Yiwen)
@@ -243,6 +243,10 @@ config SOC_PSRAM_DMA_CAPABLE
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bool
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default y
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config SOC_SDMMC_HOST_SUPPORTED
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bool
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default y
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config SOC_CLK_TREE_SUPPORTED
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bool
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default y
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@@ -275,6 +279,10 @@ config SOC_TOUCH_SENSOR_SUPPORTED
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bool
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default y
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config SOC_GP_LDO_SUPPORTED
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bool
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default y
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config SOC_RNG_SUPPORTED
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bool
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default y
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@@ -783,6 +791,34 @@ config SOC_MMU_PER_EXT_MEM_TARGET
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bool
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default y
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config SOC_SDMMC_USE_IOMUX
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bool
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default y
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config SOC_SDMMC_NUM_SLOTS
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int
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default 2
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config SOC_SDMMC_DATA_WIDTH_MAX
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int
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default 4
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config SOC_SDMMC_DELAY_PHASE_NUM
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int
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default 8
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config SOC_SDMMC_IO_UHS_POWER_EXTERNAL
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bool
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default y
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config SOC_SDMMC_PSRAM_DMA_CAPABLE
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bool
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default y
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config SOC_SDMMC_UHS_I_SUPPORTED
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bool
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default y
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config SOC_SPI_PERIPH_NUM
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int
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default 3
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@@ -340,6 +340,21 @@ typedef enum {
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LP_I2C_SCLK_DEFAULT = SOC_MOD_CLK_RTC_FAST, /*!< LP_I2C source clock default choice is RTC_FAST */
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} soc_periph_lp_i2c_clk_src_t;
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//////////////////////////////////////////////////SDMMC///////////////////////////////////////////////////////////////
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/**
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* @brief Array initializer for all supported clock sources of SDMMC
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*/
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#define SOC_SDMMC_CLKS {SOC_MOD_CLK_MPLL}
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/**
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* @brief Type of SDMMC clock source
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*/
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typedef enum {
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SDMMC_CLK_SRC_DEFAULT = SOC_MOD_CLK_MPLL, /*!< Select MPLL as the default choice */
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SDMMC_CLK_SRC_MPLL = SOC_MOD_CLK_MPLL, /*!< Select MPLL as the source clock */
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} soc_periph_sdmmc_clk_src_t;
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/////////////////////////////////////////////////SPI////////////////////////////////////////////////////////////////////
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/**
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@@ -89,7 +89,7 @@
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#define SOC_LP_SPI_SUPPORTED 1
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#define SOC_SPIRAM_SUPPORTED 1
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#define SOC_PSRAM_DMA_CAPABLE 1
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// #define SOC_SDMMC_HOST_SUPPORTED 1 // TODO: [ESP32S31] IDF-14705
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#define SOC_SDMMC_HOST_SUPPORTED 1
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#define SOC_CLK_TREE_SUPPORTED 1
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#define SOC_ASSIST_DEBUG_SUPPORTED 1
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#define SOC_CPU_LOCKUP_DEBUG_SUPPORTED 1
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@@ -99,6 +99,7 @@
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#define SOC_SPI_FLASH_SUPPORTED 1 // TODO: [ESP32S31] IDF-14777
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#define SOC_SPI_FLASH_HAS_DEDICATED_LDO 1
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#define SOC_TOUCH_SENSOR_SUPPORTED 1
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#define SOC_GP_LDO_SUPPORTED 1 // General purpose LDO
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#define SOC_RNG_SUPPORTED 1
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#define SOC_PPA_SUPPORTED 1
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#define SOC_LIGHT_SLEEP_SUPPORTED 1
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@@ -301,6 +302,16 @@
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#define SOC_MMU_DI_VADDR_SHARED (1) /*!< D/I vaddr are shared */
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#define SOC_MMU_PER_EXT_MEM_TARGET (1) /*!< MMU is per physical external memory target (flash, psram) */
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/*-------------------------- SDMMC CAPS -----------------------------------------*/
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#define SOC_SDMMC_USE_IOMUX 1
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#define SOC_SDMMC_NUM_SLOTS 2
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#define SOC_SDMMC_DATA_WIDTH_MAX 4
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/* Supported host clock delay phase number */
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#define SOC_SDMMC_DELAY_PHASE_NUM 8
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#define SOC_SDMMC_IO_UHS_POWER_EXTERNAL 1 ///< SDMMC IO power controlled by external power supply
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#define SOC_SDMMC_PSRAM_DMA_CAPABLE 1 ///< SDMMC peripheral can do DMA transfer to/from PSRAMsts
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#define SOC_SDMMC_UHS_I_SUPPORTED 1
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/*-------------------------- SPI CAPS ----------------------------------------*/
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#define SOC_SPI_PERIPH_NUM 3
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#define SOC_SPI_MAXIMUM_BUFFER_SIZE 64
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@@ -579,7 +579,7 @@ typedef union {
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} cnnt_sys_gmac_ctrl2_reg_t;
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typedef struct {
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typedef struct cnnt_dev_t {
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volatile cnnt_sys_ver_date_reg_t sys_ver_date;
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volatile cnnt_clk_en_reg_t clk_en;
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uint32_t reserved_008[2];
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@@ -1,5 +1,5 @@
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/**
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* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0 OR MIT
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*/
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@@ -162,7 +162,7 @@ extern "C" {
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* Clock source selection register
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*/
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#define SDHOST_CLKSRC_REG (DR_REG_SDHOST_BASE + 0xc)
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/** SDHOST_CLKSRC_REG : R/W; bitpos: [3:0]; default: 0;
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/** SDHOST_CLKSRC : R/W; bitpos: [3:0]; default: 0;
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* Clock divider source for two SD cards is supported. Each card has two bits assigned
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* to it. For example, bit[1:0] are assigned for card 0, bit[3:2] are assigned for
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* card 1. Card 0 maps and internally routes clock divider[0:3] outputs to
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@@ -172,10 +172,10 @@ extern "C" {
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* 10 : Clock divider 2;
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* 11 : Clock divider 3.
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*/
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#define SDHOST_CLKSRC_REG 0x0000000FU
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#define SDHOST_CLKSRC_REG_M (SDHOST_CLKSRC_REG_V << SDHOST_CLKSRC_REG_S)
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#define SDHOST_CLKSRC_REG_V 0x0000000FU
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#define SDHOST_CLKSRC_REG_S 0
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#define SDHOST_CLKSRC 0x0000000FU
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#define SDHOST_CLKSRC_M (SDHOST_CLKSRC_V << SDHOST_CLKSRC_S)
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#define SDHOST_CLKSRC_V 0x0000000FU
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#define SDHOST_CLKSRC_S 0
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/** SDHOST_CLKENA_REG register
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* Clock enable register
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@@ -320,13 +320,13 @@ extern "C" {
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* Command argument data register
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*/
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#define SDHOST_CMDARG_REG (DR_REG_SDHOST_BASE + 0x28)
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/** SDHOST_CMDARG_REG : R/W; bitpos: [31:0]; default: 0;
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/** SDHOST_CMDARG : R/W; bitpos: [31:0]; default: 0;
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* Value indicates command argument to be passed to the card.
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*/
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#define SDHOST_CMDARG_REG 0xFFFFFFFFU
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#define SDHOST_CMDARG_REG_M (SDHOST_CMDARG_REG_V << SDHOST_CMDARG_REG_S)
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#define SDHOST_CMDARG_REG_V 0xFFFFFFFFU
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#define SDHOST_CMDARG_REG_S 0
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#define SDHOST_CMDARG 0xFFFFFFFFU
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#define SDHOST_CMDARG_M (SDHOST_CMDARG_V << SDHOST_CMDARG_S)
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#define SDHOST_CMDARG_V 0xFFFFFFFFU
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#define SDHOST_CMDARG_S 0
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/** SDHOST_CMD_REG register
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* Command and boot configuration register
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@@ -807,25 +807,25 @@ extern "C" {
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* Transferred byte count register
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*/
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#define SDHOST_TCBCNT_REG (DR_REG_SDHOST_BASE + 0x5c)
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/** SDHOST_TCBCNT_REG : RO; bitpos: [31:0]; default: 0;
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/** SDHOST_TCBCNT : RO; bitpos: [31:0]; default: 0;
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* Number of bytes transferred by CIU unit to card.
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*/
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#define SDHOST_TCBCNT_REG 0xFFFFFFFFU
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#define SDHOST_TCBCNT_REG_M (SDHOST_TCBCNT_REG_V << SDHOST_TCBCNT_REG_S)
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#define SDHOST_TCBCNT_REG_V 0xFFFFFFFFU
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#define SDHOST_TCBCNT_REG_S 0
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#define SDHOST_TCBCNT 0xFFFFFFFFU
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#define SDHOST_TCBCNT_M (SDHOST_TCBCNT_V << SDHOST_TCBCNT_S)
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#define SDHOST_TCBCNT_V 0xFFFFFFFFU
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#define SDHOST_TCBCNT_S 0
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/** SDHOST_TBBCNT_REG register
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* Transferred byte count register
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*/
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#define SDHOST_TBBCNT_REG (DR_REG_SDHOST_BASE + 0x60)
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/** SDHOST_TBBCNT_REG : RO; bitpos: [31:0]; default: 0;
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/** SDHOST_TBBCNT : RO; bitpos: [31:0]; default: 0;
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* Number of bytes transferred between Host/DMA memory and BIU FIFO.
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*/
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#define SDHOST_TBBCNT_REG 0xFFFFFFFFU
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#define SDHOST_TBBCNT_REG_M (SDHOST_TBBCNT_REG_V << SDHOST_TBBCNT_REG_S)
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#define SDHOST_TBBCNT_REG_V 0xFFFFFFFFU
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#define SDHOST_TBBCNT_REG_S 0
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#define SDHOST_TBBCNT 0xFFFFFFFFU
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#define SDHOST_TBBCNT_M (SDHOST_TBBCNT_V << SDHOST_TBBCNT_S)
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#define SDHOST_TBBCNT_V 0xFFFFFFFFU
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#define SDHOST_TBBCNT_S 0
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/** SDHOST_DEBNCE_REG register
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* Debounce filter time configuration register
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@@ -845,14 +845,14 @@ extern "C" {
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* User ID (scratchpad) register
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*/
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#define SDHOST_USRID_REG (DR_REG_SDHOST_BASE + 0x68)
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/** SDHOST_USRID_REG : R/W; bitpos: [31:0]; default: 0;
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/** SDHOST_USRID : R/W; bitpos: [31:0]; default: 0;
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* User identification register, value set by user. Can also be used as a scratchpad
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* register by user.
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*/
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#define SDHOST_USRID_REG 0xFFFFFFFFU
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#define SDHOST_USRID_REG_M (SDHOST_USRID_REG_V << SDHOST_USRID_REG_S)
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#define SDHOST_USRID_REG_V 0xFFFFFFFFU
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#define SDHOST_USRID_REG_S 0
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#define SDHOST_USRID 0xFFFFFFFFU
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#define SDHOST_USRID_M (SDHOST_USRID_V << SDHOST_USRID_S)
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#define SDHOST_USRID_V 0xFFFFFFFFU
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#define SDHOST_USRID_S 0
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/** SDHOST_VERID_REG register
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* Version ID (scratchpad) register
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@@ -1035,15 +1035,15 @@ extern "C" {
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* Descriptor base address register
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*/
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#define SDHOST_DBADDR_REG (DR_REG_SDHOST_BASE + 0x88)
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/** SDHOST_DBADDR_REG : R/W; bitpos: [31:0]; default: 0;
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/** SDHOST_DBADDR : R/W; bitpos: [31:0]; default: 0;
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* Start of Descriptor List. Contains the base address of the First Descriptor. The
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* LSB bits [1:0] are ignored and taken as all-zero by the IDMAC internally. Hence
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* these LSB bits may be treated as read-only.
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*/
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#define SDHOST_DBADDR_REG 0xFFFFFFFFU
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#define SDHOST_DBADDR_REG_M (SDHOST_DBADDR_REG_V << SDHOST_DBADDR_REG_S)
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#define SDHOST_DBADDR_REG_V 0xFFFFFFFFU
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#define SDHOST_DBADDR_REG_S 0
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#define SDHOST_DBADDR 0xFFFFFFFFU
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#define SDHOST_DBADDR_M (SDHOST_DBADDR_V << SDHOST_DBADDR_S)
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#define SDHOST_DBADDR_V 0xFFFFFFFFU
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#define SDHOST_DBADDR_S 0
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/** SDHOST_IDSTS_REG register
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* IDMAC status register
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@@ -1219,29 +1219,29 @@ extern "C" {
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* Host descriptor address pointer
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*/
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#define SDHOST_DSCADDR_REG (DR_REG_SDHOST_BASE + 0x94)
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/** SDHOST_DSCADDR_REG : RO; bitpos: [31:0]; default: 0;
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/** SDHOST_DSCADDR : RO; bitpos: [31:0]; default: 0;
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* Host Descriptor Address Pointer, updated by IDMAC during operation and cleared on
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* reset. This register points to the start address of the current descriptor read by
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* the IDMAC.
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*/
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#define SDHOST_DSCADDR_REG 0xFFFFFFFFU
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#define SDHOST_DSCADDR_REG_M (SDHOST_DSCADDR_REG_V << SDHOST_DSCADDR_REG_S)
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#define SDHOST_DSCADDR_REG_V 0xFFFFFFFFU
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#define SDHOST_DSCADDR_REG_S 0
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#define SDHOST_DSCADDR 0xFFFFFFFFU
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#define SDHOST_DSCADDR_M (SDHOST_DSCADDR_V << SDHOST_DSCADDR_S)
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#define SDHOST_DSCADDR_V 0xFFFFFFFFU
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#define SDHOST_DSCADDR_S 0
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/** SDHOST_BUFADDR_REG register
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* Host buffer address pointer register
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*/
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#define SDHOST_BUFADDR_REG (DR_REG_SDHOST_BASE + 0x98)
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/** SDHOST_BUFADDR_REG : RO; bitpos: [31:0]; default: 0;
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/** SDHOST_BUFADDR : RO; bitpos: [31:0]; default: 0;
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* Host Buffer Address Pointer, updated by IDMAC during operation and cleared on
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* reset. This register points to the current Data Buffer Address being accessed by
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* the IDMAC.
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*/
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#define SDHOST_BUFADDR_REG 0xFFFFFFFFU
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#define SDHOST_BUFADDR_REG_M (SDHOST_BUFADDR_REG_V << SDHOST_BUFADDR_REG_S)
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#define SDHOST_BUFADDR_REG_V 0xFFFFFFFFU
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#define SDHOST_BUFADDR_REG_S 0
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#define SDHOST_BUFADDR 0xFFFFFFFFU
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#define SDHOST_BUFADDR_M (SDHOST_BUFADDR_V << SDHOST_BUFADDR_S)
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#define SDHOST_BUFADDR_V 0xFFFFFFFFU
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#define SDHOST_BUFADDR_S 0
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/** SDHOST_CARDTHRCTL_REG register
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* Card Threshold Control register
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@@ -1327,14 +1327,14 @@ extern "C" {
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* CPU write and read transmit data by FIFO
|
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*/
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#define SDHOST_BUFFIFO_REG (DR_REG_SDHOST_BASE + 0x200)
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/** SDHOST_BUFFIFO_REG : R/W; bitpos: [31:0]; default: 0;
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/** SDHOST_BUFFIFO : R/W; bitpos: [31:0]; default: 0;
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* CPU write and read transmit data by FIFO. This register points to the current Data
|
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* FIFO .
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*/
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#define SDHOST_BUFFIFO_REG 0xFFFFFFFFU
|
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#define SDHOST_BUFFIFO_REG_M (SDHOST_BUFFIFO_REG_V << SDHOST_BUFFIFO_REG_S)
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#define SDHOST_BUFFIFO_REG_V 0xFFFFFFFFU
|
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#define SDHOST_BUFFIFO_REG_S 0
|
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#define SDHOST_BUFFIFO 0xFFFFFFFFU
|
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#define SDHOST_BUFFIFO_M (SDHOST_BUFFIFO_V << SDHOST_BUFFIFO_S)
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#define SDHOST_BUFFIFO_V 0xFFFFFFFFU
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#define SDHOST_BUFFIFO_S 0
|
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/** SDHOST_CLK_EDGE_SEL_REG register
|
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* SDIO control register.
|
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@@ -1492,6 +1492,34 @@ extern "C" {
|
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#define SDHOST_DLL_CAL_END_V 0x00000001U
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#define SDHOST_DLL_CAL_END_S 1
|
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#define SDMMC_INTMASK_IO_SLOT1 BIT(17)
|
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#define SDMMC_INTMASK_IO_SLOT0 BIT(16)
|
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#define SDMMC_INTMASK_EBE BIT(15)
|
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#define SDMMC_INTMASK_ACD BIT(14)
|
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#define SDMMC_INTMASK_SBE BIT(13)
|
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#define SDMMC_INTMASK_HLE BIT(12)
|
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#define SDMMC_INTMASK_FRUN BIT(11)
|
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#define SDMMC_INTMASK_HTO BIT(10)
|
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#define SDMMC_INTMASK_VOLT_SW SDMMC_INTMASK_HTO
|
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#define SDMMC_INTMASK_DTO BIT(9)
|
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#define SDMMC_INTMASK_RTO BIT(8)
|
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#define SDMMC_INTMASK_DCRC BIT(7)
|
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#define SDMMC_INTMASK_RCRC BIT(6)
|
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#define SDMMC_INTMASK_RXDR BIT(5)
|
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#define SDMMC_INTMASK_TXDR BIT(4)
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#define SDMMC_INTMASK_DATA_OVER BIT(3)
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#define SDMMC_INTMASK_CMD_DONE BIT(2)
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#define SDMMC_INTMASK_RESP_ERR BIT(1)
|
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#define SDMMC_INTMASK_CD BIT(0)
|
||||
|
||||
#define SDMMC_IDMAC_INTMASK_AI BIT(9)
|
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#define SDMMC_IDMAC_INTMASK_NI BIT(8)
|
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#define SDMMC_IDMAC_INTMASK_CES BIT(5)
|
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#define SDMMC_IDMAC_INTMASK_DU BIT(4)
|
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#define SDMMC_IDMAC_INTMASK_FBE BIT(2)
|
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#define SDMMC_IDMAC_INTMASK_RI BIT(1)
|
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#define SDMMC_IDMAC_INTMASK_TI BIT(0)
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|
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#ifdef __cplusplus
|
||||
}
|
||||
#endif
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||||
|
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@@ -1,5 +1,5 @@
|
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/**
|
||||
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
|
||||
* SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0 OR MIT
|
||||
*/
|
||||
@@ -10,6 +10,36 @@
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef struct sdmmc_desc_s {
|
||||
struct {
|
||||
uint32_t reserved1: 1;
|
||||
uint32_t disable_int_on_completion: 1;
|
||||
uint32_t last_descriptor: 1;
|
||||
uint32_t first_descriptor: 1;
|
||||
uint32_t second_address_chained: 1;
|
||||
uint32_t end_of_ring: 1;
|
||||
uint32_t reserved2: 24;
|
||||
uint32_t card_error_summary: 1;
|
||||
uint32_t owned_by_idmac: 1;
|
||||
};
|
||||
struct {
|
||||
uint32_t buffer1_size: 13;
|
||||
uint32_t buffer2_size: 13;
|
||||
uint32_t reserved3: 6;
|
||||
};
|
||||
void* buffer1_ptr;
|
||||
union {
|
||||
void* buffer2_ptr;
|
||||
void* next_desc_ptr;
|
||||
};
|
||||
} sdmmc_desc_t;
|
||||
|
||||
#define SDMMC_DMA_MAX_BUF_LEN 4096
|
||||
|
||||
#ifndef __cplusplus
|
||||
_Static_assert(sizeof(sdmmc_desc_t) == 16, "invalid size of sdmmc_desc_t structure");
|
||||
#endif
|
||||
|
||||
/** Group: Control register */
|
||||
/** Type of ctrl register
|
||||
* Control register
|
||||
@@ -39,7 +69,7 @@ typedef union {
|
||||
* Global interrupt enable/disable bit. 0: Disable; 1: Enable.
|
||||
*/
|
||||
uint32_t int_enable:1;
|
||||
uint32_t reserved_5:1;
|
||||
uint32_t dma_enable:1;
|
||||
/** read_wait : R/W; bitpos: [6]; default: 0;
|
||||
* For sending read-wait to SDIO cards.
|
||||
*/
|
||||
@@ -90,7 +120,12 @@ typedef union {
|
||||
* then software should set this bit.
|
||||
*/
|
||||
uint32_t ceata_device_interrupt_status:1;
|
||||
uint32_t reserved_12:20;
|
||||
uint32_t reserved2:4;
|
||||
uint32_t card_voltage_a:4;
|
||||
uint32_t card_voltage_b:4;
|
||||
uint32_t enable_od_pullup:1;
|
||||
uint32_t use_internal_dma:1;
|
||||
uint32_t reserved3:6;
|
||||
};
|
||||
uint32_t val;
|
||||
} sdhost_ctrl_reg_t;
|
||||
@@ -147,7 +182,8 @@ typedef union {
|
||||
* 10 : Clock divider 2;
|
||||
* 11 : Clock divider 3.
|
||||
*/
|
||||
uint32_t clksrc_reg:4;
|
||||
uint32_t card0:2;
|
||||
uint32_t card1:2;
|
||||
uint32_t reserved_4:28;
|
||||
};
|
||||
uint32_t val;
|
||||
@@ -334,10 +370,10 @@ typedef union {
|
||||
* 0: No response expected from card; 1: Response expected from card.
|
||||
*/
|
||||
uint32_t response_expect:1;
|
||||
/** response_length : R/W; bitpos: [7]; default: 0;
|
||||
/** response_long : R/W; bitpos: [7]; default: 0;
|
||||
* 0: Short response expected from card; 1: Long response expected from card.
|
||||
*/
|
||||
uint32_t response_length:1;
|
||||
uint32_t response_long:1;
|
||||
/** check_response_crc : R/W; bitpos: [8]; default: 0;
|
||||
* 0: Do not check; 1: Check response CRC.
|
||||
* Some of command responses do not return valid CRC bits. Software should disable CRC
|
||||
@@ -348,11 +384,11 @@ typedef union {
|
||||
* 0: No data transfer expected; 1: Data transfer expected.
|
||||
*/
|
||||
uint32_t data_expected:1;
|
||||
/** read_write : R/W; bitpos: [10]; default: 0;
|
||||
/** rw : R/W; bitpos: [10]; default: 0;
|
||||
* 0: Read from card; 1: Write to card.
|
||||
* Don't care if no data is expected from card.
|
||||
*/
|
||||
uint32_t read_write:1;
|
||||
uint32_t rw:1;
|
||||
/** transfer_mode : R/W; bitpos: [11]; default: 0;
|
||||
* 0: Block data transfer command; 1: Stream data transfer command.
|
||||
* Don't care if no data expected.
|
||||
@@ -363,14 +399,14 @@ typedef union {
|
||||
* end of data transfer.
|
||||
*/
|
||||
uint32_t send_auto_stop:1;
|
||||
/** wait_prvdata_complete : R/W; bitpos: [13]; default: 0;
|
||||
/** wait_complete : R/W; bitpos: [13]; default: 0;
|
||||
* 0: Send command at once, even if previous data transfer has not completed; 1: Wait
|
||||
* for previous data transfer to complete before sending Command.
|
||||
* The SDHOST_WAIT_PRVDATA_COMPLETE] = 0 option is typically used to query status of
|
||||
* The SDHOST_WAIT_COMPLETE] = 0 option is typically used to query status of
|
||||
* card during data transfer or to stop current data transfer. SDHOST_CARD_NUMBERr
|
||||
* should be same as in previous command.
|
||||
*/
|
||||
uint32_t wait_prvdata_complete:1;
|
||||
uint32_t wait_complete:1;
|
||||
/** stop_abort_cmd : R/W; bitpos: [14]; default: 0;
|
||||
* 0: Neither stop nor abort command can stop current data transfer. If abort is sent
|
||||
* to function-number currently selected or not in data-transfer mode, then bit should
|
||||
@@ -381,20 +417,20 @@ typedef union {
|
||||
* state-machines of CIU can return correctly to idle state.
|
||||
*/
|
||||
uint32_t stop_abort_cmd:1;
|
||||
/** send_initialization : R/W; bitpos: [15]; default: 0;
|
||||
/** send_init : R/W; bitpos: [15]; default: 0;
|
||||
* 0: Do not send initialization sequence (80 clocks of 1) before sending this
|
||||
* command; 1: Send initialization sequence before sending this command.
|
||||
* After powered on, 80 clocks must be sent to card for initialization before sending
|
||||
* any commands to card. Bit should be set while sending first command to card so that
|
||||
* controller will initialize clocks before sending command to card.
|
||||
*/
|
||||
uint32_t send_initialization:1;
|
||||
/** card_number : R/W; bitpos: [20:16]; default: 0;
|
||||
uint32_t send_init:1;
|
||||
/** card_num : R/W; bitpos: [20:16]; default: 0;
|
||||
* Card number in use. Represents physical slot number of card being accessed. In
|
||||
* SD-only mode, up to two cards are supported.
|
||||
*/
|
||||
uint32_t card_number:5;
|
||||
/** update_clock_registers_only : R/W; bitpos: [21]; default: 0;
|
||||
uint32_t card_num:5;
|
||||
/** update_clk_reg : R/W; bitpos: [21]; default: 0;
|
||||
* 0: Normal command sequence; 1: Do not send commands, just update clock register
|
||||
* value into card clock domain.
|
||||
* Following register values are transferred into card clock domain: CLKDIV, CLRSRC,
|
||||
@@ -407,7 +443,7 @@ typedef union {
|
||||
* register values for new command sequence to card(s). When bit is set, there are no
|
||||
* Command Done interrupts because no command is sent to SD_MMC_CEATA cards.
|
||||
*/
|
||||
uint32_t update_clock_registers_only:1;
|
||||
uint32_t update_clk_reg:1;
|
||||
/** read_ceata_device : R/W; bitpos: [22]; default: 0;
|
||||
* Read access flag.
|
||||
* 0: Host is not performing read access (RW_REG or RW_BLK)towards CE-ATA device;
|
||||
@@ -431,83 +467,33 @@ typedef union {
|
||||
* not masked.
|
||||
*/
|
||||
uint32_t ccs_expected:1;
|
||||
uint32_t reserved_24:5;
|
||||
uint32_t reserved_24:4;
|
||||
/** volt_switch : R/W; bitpos: [28]; default: 0;
|
||||
* Voltage switch bit.
|
||||
* 0: No voltage switching.
|
||||
* 1: Voltage switching enabled; must be set for CMD11 only.
|
||||
*/
|
||||
uint32_t volt_switch:1;
|
||||
/** use_hole_reg : R/W; bitpos: [29]; default: 1;
|
||||
* Use Hold Register.
|
||||
* 0: CMD and DATA sent to card bypassing HOLD Register;
|
||||
* 1: CMD and DATA sent to card through the HOLD Register.
|
||||
*/
|
||||
uint32_t use_hole_reg:1;
|
||||
uint32_t use_hold_reg:1;
|
||||
uint32_t reserved_30:1;
|
||||
/** start_cmd : R/W; bitpos: [31]; default: 0;
|
||||
/** start_command : R/W; bitpos: [31]; default: 0;
|
||||
* Start command. Once command is served by the CIU, this bit is automatically
|
||||
* cleared. When this bit is set, host should not attempt to write to any command
|
||||
* registers. If a write is attempted, hardware lock error is set in raw interrupt
|
||||
* register. Once command is sent and a response is received from SD_MMC_CEATA cards,
|
||||
* Command Done bit is set in the raw interrupt Register.
|
||||
*/
|
||||
uint32_t start_cmd:1;
|
||||
uint32_t start_command:1;
|
||||
};
|
||||
uint32_t val;
|
||||
} sdhost_cmd_reg_t;
|
||||
|
||||
|
||||
/** Group: Response data register */
|
||||
/** Type of resp0 register
|
||||
* Response data register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** response0_reg : RO; bitpos: [31:0]; default: 0;
|
||||
* Bit[31:0] of response.
|
||||
*/
|
||||
uint32_t response0_reg:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} sdhost_resp0_reg_t;
|
||||
|
||||
|
||||
/** Group: Long response data register */
|
||||
/** Type of resp1 register
|
||||
* Long response data register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** response1_reg : RO; bitpos: [31:0]; default: 0;
|
||||
* Bit[63:32] of long response.
|
||||
*/
|
||||
uint32_t response1_reg:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} sdhost_resp1_reg_t;
|
||||
|
||||
/** Type of resp2 register
|
||||
* Long response data register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** response2_reg : RO; bitpos: [31:0]; default: 0;
|
||||
* Bit[95:64] of long response.
|
||||
*/
|
||||
uint32_t response2_reg:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} sdhost_resp2_reg_t;
|
||||
|
||||
/** Type of resp3 register
|
||||
* Long response data register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** response3_reg : RO; bitpos: [31:0]; default: 0;
|
||||
* Bit[127:96] of long response.
|
||||
*/
|
||||
uint32_t response3_reg:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} sdhost_resp3_reg_t;
|
||||
|
||||
|
||||
/** Group: Masked interrupt status register */
|
||||
/** Type of mintsts register
|
||||
* Masked interrupt status register
|
||||
@@ -880,13 +866,18 @@ typedef union {
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t reserved_0:16;
|
||||
/** ddr_reg : R/W; bitpos: [17:16]; default: 0;
|
||||
/** volt: R/W; bitpos: [1:0]; default: 0;
|
||||
* 0: 3.3V mode.
|
||||
* 1: 1.8V mode.
|
||||
*/
|
||||
uint32_t volt:2;
|
||||
uint32_t reserved_0:14;
|
||||
/** ddr : R/W; bitpos: [17:16]; default: 0;
|
||||
* DDR mode selection,1 bit for each card.
|
||||
* 0-Non-DDR mode.
|
||||
* 1-DDR mode.
|
||||
*/
|
||||
uint32_t ddr_reg:2;
|
||||
uint32_t ddr:2;
|
||||
uint32_t reserved_18:14;
|
||||
};
|
||||
uint32_t val;
|
||||
@@ -1392,7 +1383,7 @@ typedef union {
|
||||
} sdhost_dll_conf_reg_t;
|
||||
|
||||
|
||||
typedef struct {
|
||||
typedef struct sdmmc_dev_t {
|
||||
volatile sdhost_ctrl_reg_t ctrl;
|
||||
uint32_t reserved_004;
|
||||
volatile sdhost_clkdiv_reg_t clkdiv;
|
||||
@@ -1403,12 +1394,9 @@ typedef struct {
|
||||
volatile sdhost_blksiz_reg_t blksiz;
|
||||
volatile sdhost_bytcnt_reg_t bytcnt;
|
||||
volatile sdhost_intmask_reg_t intmask;
|
||||
volatile sdhost_cmdarg_reg_t cmdarg;
|
||||
volatile uint32_t cmdarg;
|
||||
volatile sdhost_cmd_reg_t cmd;
|
||||
volatile sdhost_resp0_reg_t resp0;
|
||||
volatile sdhost_resp1_reg_t resp1;
|
||||
volatile sdhost_resp2_reg_t resp2;
|
||||
volatile sdhost_resp3_reg_t resp3;
|
||||
volatile uint32_t resp[4];
|
||||
volatile sdhost_mintsts_reg_t mintsts;
|
||||
volatile sdhost_rintsts_reg_t rintsts;
|
||||
volatile sdhost_status_reg_t status;
|
||||
@@ -1420,7 +1408,7 @@ typedef struct {
|
||||
volatile sdhost_tbbcnt_reg_t tbbcnt;
|
||||
volatile sdhost_debnce_reg_t debnce;
|
||||
volatile sdhost_usrid_reg_t usrid;
|
||||
volatile sdhost_verid_reg_t verid;
|
||||
volatile uint32_t verid;
|
||||
volatile sdhost_hcon_reg_t hcon;
|
||||
volatile sdhost_uhs_reg_t uhs;
|
||||
volatile sdhost_rst_n_reg_t rst_n;
|
||||
@@ -1446,6 +1434,9 @@ typedef struct {
|
||||
volatile sdhost_dll_conf_reg_t dll_conf;
|
||||
} sdmmc_dev_t;
|
||||
|
||||
extern sdmmc_dev_t SDMMC;
|
||||
|
||||
typedef sdhost_cmd_reg_t sdmmc_hw_cmd_t;
|
||||
|
||||
#ifndef __cplusplus
|
||||
_Static_assert(sizeof(sdmmc_dev_t) == 0x810, "Invalid size of sdmmc_dev_t structure");
|
||||
|
||||
Reference in New Issue
Block a user