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fix(cpu_region_protect): set DROM mask PMP entry to read-only

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PMP entry 3 (SOC_DROM_MASK_HIGH, TOR mode) in the memprot path
was incorrectly granted RW permission on esp32h21 and esp32c61.
The mask ROM data region is inherently read-only; remove the W bit.

Also added necessary tests to check voilations and re-enabled
tests for ESP32P4
This commit is contained in:
nilesh.kale
2026-04-13 10:27:58 +05:30
parent 338f341110
commit a6a2696972
6 changed files with 58 additions and 3 deletions
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components/esp_hw_support/port/esp32c61/cpu_region_protect.c
+1 -1
View File
@@ -147,7 +147,7 @@ void esp_cpu_configure_region_protection(void)
if ((drom_start & (SOC_CPU_PMP_REGION_GRANULARITY - 1)) == 0) {
PMP_ENTRY_SET(1, SOC_IROM_MASK_LOW, NONE);
PMP_ENTRY_SET(2, drom_start, PMP_TOR | RX);
PMP_ENTRY_SET(3, SOC_DROM_MASK_HIGH, PMP_TOR | RW);
PMP_ENTRY_SET(3, SOC_DROM_MASK_HIGH, PMP_TOR | R);
} else
#endif
{
components/esp_hw_support/port/esp32h21/cpu_region_protect.c
+1 -1
View File
@@ -139,7 +139,7 @@ void esp_cpu_configure_region_protection(void)
PMP_ENTRY_CFG_RESET(3);
PMP_ENTRY_SET(1, SOC_IROM_MASK_LOW, NONE);
PMP_ENTRY_SET(2, drom_start, PMP_TOR | RX);
PMP_ENTRY_SET(3, SOC_DROM_MASK_HIGH, PMP_TOR | RW);
PMP_ENTRY_SET(3, SOC_DROM_MASK_HIGH, PMP_TOR | R);
} else
#endif
{