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feat(cache): support cache preload hal api

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This commit is contained in:
armando
2026-03-10 15:03:05 +08:00
parent 638a47b704
commit a699805d39
22 changed files with 1090 additions and 44 deletions
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components/soc/esp32c6/register/soc/extmem_reg.h
+9 -1
View File
@@ -1,5 +1,5 @@
/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0 OR MIT
*/
@@ -24,6 +24,14 @@ extern "C" {
#define EXTMEM_L1_CACHE_SHUT_IBUS_M (BIT(0))
#define EXTMEM_L1_CACHE_SHUT_IBUS_V 0x1
#define EXTMEM_L1_CACHE_SHUT_IBUS_S 0
/* EXTMEM_L1_CACHE_UNDEF_OP : R/W ;bitpos:[11:8] ;default: 4'h0 ; */
/*description: Internal debug control field. bits[1:0]: Arbitration mode. 0: Round-robin, hold bus
until data fetch completes. 1: Round-robin, release bus after request is issued. 2/3: Random
arbitration..*/
#define EXTMEM_L1_CACHE_UNDEF_OP 0x0000000F
#define EXTMEM_L1_CACHE_UNDEF_OP_M ((EXTMEM_L1_CACHE_UNDEF_OP_V)<<(EXTMEM_L1_CACHE_UNDEF_OP_S))
#define EXTMEM_L1_CACHE_UNDEF_OP_V 0xF
#define EXTMEM_L1_CACHE_UNDEF_OP_S 8
#define EXTMEM_L1_CACHE_WRAP_AROUND_CTRL_REG (DR_REG_EXTMEM_BASE + 0x20)
/* EXTMEM_L1_CACHE_WRAP : R/W ;bitpos:[4] ;default: 1'h0 ; */
components/soc/esp32c6/register/soc/extmem_struct.h
+16 -4
View File
@@ -1,5 +1,5 @@
/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0 OR MIT
*/
@@ -33,7 +33,11 @@ typedef union {
*/
uint32_t l1_icache_shut_ibus3:1;
/** l1_icache_undef_op : HRO; bitpos: [7:4]; default: 0;
* Reserved
* Internal debug control field.
* bits[1:0]: Arbitration mode.
* 0: Round-robin, hold bus until data fetch completes.
* 1: Round-robin, release bus after request is issued.
* 2/3: Random arbitration.
*/
uint32_t l1_icache_undef_op:4;
uint32_t reserved_8:24;
@@ -68,7 +72,11 @@ typedef union {
uint32_t l1_cache_shut_dma:1;
uint32_t reserved_5:3;
/** l1_cache_undef_op : R/W; bitpos: [11:8]; default: 0;
* Reserved
* Internal debug control field.
* bits[1:0]: Arbitration mode.
* 0: Round-robin, hold bus until data fetch completes.
* 1: Round-robin, release bus after request is issued.
* 2/3: Random arbitration.
*/
uint32_t l1_cache_undef_op:4;
uint32_t reserved_12:20;
@@ -87,7 +95,11 @@ typedef union {
*/
uint32_t l2_cache_shut_dma:1;
/** l2_cache_undef_op : HRO; bitpos: [8:5]; default: 0;
* Reserved
* Internal debug control field.
* bits[1:0]: Arbitration mode.
* 0: Round-robin, hold bus until data fetch completes.
* 1: Round-robin, release bus after request is issued.
* 2/3: Random arbitration.
*/
uint32_t l2_cache_undef_op:4;
uint32_t reserved_9:23;