Mirrors/esp-idf
1
0
Fork 0
mirror of https://github.com/espressif/esp-idf.git synced 2026-10-02 11:10:54 +03:00
Code Issues Packages Projects Releases Wiki Activity

feat(cache): support cache preload hal api

Browse Source
This commit is contained in:
armando
2026-03-10 15:03:05 +08:00
parent 638a47b704
commit a699805d39
22 changed files with 1090 additions and 44 deletions
Download Patch File Download Diff File Expand all files Collapse all files
components/hal/esp32h4/include/hal/cache_ll.h
+76 -1
View File
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -34,6 +34,15 @@ extern "C" {
#define CACHE_LL_LEVEL_NUMS 1 //Number of cache levels
#define CACHE_LL_CACHE_AUTOLOAD (1<<0)
/**
* @brief Preload strategy
*/
typedef enum {
CACHE_LL_PRELOAD_UNTIL_FETCH_DONE = 0,
CACHE_LL_PRELOAD_AFTER_FETCH = 1,
CACHE_LL_PRELOAD_ARBITRARY = 2,
} cache_ll_preload_strategy_t;
/**
* @brief Check if L1 ICache autoload is enabled or not
*
@@ -681,6 +690,72 @@ static inline void cache_ll_unfreeze_cache(uint32_t cache_level, cache_type_t ty
}
}
/*------------------------------------------------------------------------------
* Cache Preload
*----------------------------------------------------------------------------*/
/**
* @brief Set the preload strategy (no-op)
*/
__attribute__((always_inline))
static inline void cache_ll_preload_set_strategy(uint32_t cache_level, cache_type_t type, uint32_t cache_id, cache_ll_preload_strategy_t strategy)
{
(void)cache_level;
(void)type;
(void)cache_id;
(void)strategy;
}
/**
* @brief Preload cache (L1 only)
*
* Starts preload for the given map and does not wait. Use cache_ll_preload_wait_done() to wait for completion.
*/
__attribute__((always_inline))
static inline void cache_ll_preload(uint32_t cache_level, cache_type_t type, uint32_t cache_id, uint32_t vaddr, uint32_t size, bool ascending)
{
(void)cache_id;
HAL_ASSERT(cache_level == CACHE_LL_LEVEL_EXT_MEM);
uint32_t map;
switch (type) {
case CACHE_TYPE_INSTRUCTION:
map = CACHE_MAP_ICACHE0 | CACHE_MAP_ICACHE1;
break;
case CACHE_TYPE_DATA:
map = CACHE_MAP_DCACHE;
break;
case CACHE_TYPE_ALL:
default:
map = CACHE_MAP_ALL;
break;
}
Cache_Start_Preload(map, vaddr, size, ascending ? 0 : 1);
}
/**
* @brief Wait until cache preload is done (L1 only)
*/
__attribute__((always_inline))
static inline void cache_ll_preload_wait_done(uint32_t cache_level, cache_type_t type, uint32_t cache_id)
{
(void)cache_id;
HAL_ASSERT(cache_level == CACHE_LL_LEVEL_EXT_MEM);
uint32_t map;
switch (type) {
case CACHE_TYPE_INSTRUCTION:
map = CACHE_MAP_ICACHE0 | CACHE_MAP_ICACHE1;
break;
case CACHE_TYPE_DATA:
map = CACHE_MAP_DCACHE;
break;
case CACHE_TYPE_ALL:
default:
map = CACHE_MAP_ALL;
break;
}
while (Cache_Preload_Done(map) == 0) {
}
}
/*------------------------------------------------------------------------------
* Cache Line Size
*----------------------------------------------------------------------------*/