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Merge branch 'bugfix/fix_chip_broken_bug_in_monitor_mode_S2' into 'master'

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ESP32S2/C3/C2: fixed S2 dangerous power parameters in sleep modes and support S2/C3/C2 different sleep mode

Closes IDF-4999, IDFGH-4893, and IDFGH-7938

See merge request espressif/esp-idf!19598
This commit is contained in:
Jiang Jiang Jian
2023-04-11 09:52:02 +08:00
parent 78a549a5fa 6c35ee3fc5
commit a624d8d061
8 changed files with 370 additions and 149 deletions
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components/soc/esp32c3/include/soc/rtc.h
+19 -11
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@@ -56,7 +56,6 @@ extern "C" {
/* Approximate mapping of voltages to RTC_CNTL_DBIAS_WAK, RTC_CNTL_DBIAS_SLP,
* RTC_CNTL_DIG_DBIAS_WAK, RTC_CNTL_DIG_DBIAS_SLP values.
*/
#define RTC_CNTL_DBIAS_SLP 5 //sleep dig_dbias & rtc_dbias
#define RTC_CNTL_DBIAS_0V90 13 //digital voltage
#define RTC_CNTL_DBIAS_0V95 16
#define RTC_CNTL_DBIAS_1V00 18
@@ -107,14 +106,27 @@ set sleep_init default param
#define RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_DEFAULT 5
#define RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_NODROP 0
#define RTC_CNTL_DBG_ATTEN_DEEPSLEEP_DEFAULT 15
#define RTC_CNTL_DBG_ATTEN_DEEPSLEEP_NODROP 0
#define RTC_CNTL_BIASSLP_SLEEP_DEFAULT 1
#define RTC_CNTL_BIASSLP_SLEEP_ON 0
#define RTC_CNTL_PD_CUR_SLEEP_DEFAULT 1
#define RTC_CNTL_PD_CUR_SLEEP_ON 0
#define RTC_CNTL_DG_VDD_DRV_B_SLP_DEFAULT 254
#define RTC_CNTL_DBG_ATTEN_MONITOR_DEFAULT 0
#define RTC_CNTL_BIASSLP_MONITOR_DEFAULT 0
#define RTC_CNTL_BIASSLP_SLEEP_ON 0
#define RTC_CNTL_BIASSLP_SLEEP_DEFAULT 1
#define RTC_CNTL_PD_CUR_MONITOR_DEFAULT 0
#define RTC_CNTL_PD_CUR_SLEEP_ON 0
#define RTC_CNTL_PD_CUR_SLEEP_DEFAULT 1
#define RTC_CNTL_DG_VDD_DRV_B_SLP_DEFAULT 254
/*
use together with RTC_CNTL_DBG_ATTEN_DEEPSLEEP_DEFAULT
*/
#define RTC_CNTL_RTC_DBIAS_DEEPSLEEP_0V7 25
/*
use together with RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_DEFAULT
*/
#define RTC_CNTL_RTC_DBIAS_LIGHTSLEEP_0V6 5
#define RTC_CNTL_DIG_DBIAS_LIGHTSLEEP_0V6 5
/*
The follow value is used to get a reasonable rtc voltage dbias value according to digital dbias & some other value
@@ -572,18 +584,14 @@ typedef struct {
uint32_t dig_peri_pd_en : 1; //!< power down digital peripherals
uint32_t deep_slp : 1; //!< power down digital domain
uint32_t wdt_flashboot_mod_en : 1; //!< enable WDT flashboot mode
uint32_t dig_dbias_wak : 5; //!< set bias for digital domain, in active mode
uint32_t dig_dbias_slp : 5; //!< set bias for digital domain, in sleep mode
uint32_t rtc_dbias_wak : 5; //!< set bias for RTC domain, in active mode
uint32_t rtc_dbias_slp : 5; //!< set bias for RTC domain, in sleep mode
uint32_t dbg_atten_monitor : 4; //!< voltage parameter, in monitor mode
uint32_t bias_sleep_monitor : 1; //!< circuit control parameter, in monitor mode
uint32_t dbg_atten_slp : 4; //!< voltage parameter, in sleep mode
uint32_t bias_sleep_slp : 1; //!< circuit control parameter, in sleep mode
uint32_t pd_cur_monitor : 1; //!< circuit control parameter, in monitor mode
uint32_t pd_cur_slp : 1; //!< circuit control parameter, in sleep mode
uint32_t vddsdio_pd_en : 1; //!< power down VDDSDIO regulator
uint32_t xtal_fpu : 1; //!< keep main XTAL powered up in sleep
uint32_t rtc_regulator_fpu : 1; //!< keep rtc regulator powered up in sleep
uint32_t deep_slp_reject : 1; //!< enable deep sleep reject
uint32_t light_slp_reject : 1; //!< enable light sleep reject
} rtc_sleep_config_t;