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Merge branch 'feature/efuse_rev_major_minor' into 'master'

Browse Source 
efuse: Adds major and minor versions

See merge request espressif/esp-idf!18255
This commit is contained in:
Michael (XIAO Xufeng)
2022-07-07 11:48:54 +08:00
parent 0d86ca59a6 0f8ff5aa15
commit a58362a429
77 changed files with 776 additions and 404 deletions
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components/esp_hw_support/include/esp_chip_info.h
+1 -1
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@@ -42,8 +42,8 @@ typedef enum {
typedef struct {
esp_chip_model_t model; //!< chip model, one of esp_chip_model_t
uint32_t features; //!< bit mask of CHIP_FEATURE_x feature flags
uint16_t revision; //!< chip revision number (in format MXX; where M - wafer major version, XX - wafer minor version)
uint8_t cores; //!< number of CPU cores
uint8_t revision; //!< chip revision number
} esp_chip_info_t;
/**
components/esp_hw_support/port/esp32/chip_info.c
+2 -2
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@@ -16,7 +16,7 @@ void esp_chip_info(esp_chip_info_t* out_info)
memset(out_info, 0, sizeof(*out_info));
out_info->model = CHIP_ESP32;
out_info->revision = efuse_hal_get_chip_revision();
out_info->revision = efuse_hal_chip_revision();
if (efuse_ll_get_disable_app_cpu() == 0) {
out_info->cores = 2;
@@ -42,6 +42,6 @@ void esp_chip_info(esp_chip_info_t* out_info)
#if CONFIG_ESP32_ECO3_CACHE_LOCK_FIX
inline bool soc_has_cache_lock_bug(void)
{
return (efuse_hal_get_chip_revision() == 3);
return (efuse_hal_get_major_chip_version() == 3);
}
#endif
components/esp_hw_support/port/esp32/rtc_clk.c
+4 -4
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@@ -45,7 +45,7 @@ static void rtc_clk_32k_enable_common(clk_ll_xtal32k_enable_mode_t mode)
SET_PERI_REG_MASK(RTC_IO_XTAL_32K_PAD_REG, RTC_IO_X32N_MUX_SEL | RTC_IO_X32P_MUX_SEL);
#ifdef CONFIG_RTC_EXT_CRYST_ADDIT_CURRENT
uint8_t chip_ver = efuse_hal_get_chip_revision();
uint8_t chip_ver = efuse_hal_get_major_chip_version();
// version0 and version1 need provide additional current to external XTAL.
if(chip_ver == 0 || chip_ver == 1) {
/* TOUCH sensor can provide additional current to external XTAL.
@@ -61,7 +61,7 @@ static void rtc_clk_32k_enable_common(clk_ll_xtal32k_enable_mode_t mode)
SET_PERI_REG_MASK(RTC_IO_TOUCH_PAD9_REG, RTC_IO_TOUCH_PAD9_XPD_M);
}
#elif defined CONFIG_RTC_EXT_CRYST_ADDIT_CURRENT_V2
uint8_t chip_ver = efuse_hal_get_chip_revision();
uint8_t chip_ver = efuse_hal_get_major_chip_version();
if(chip_ver == 0 || chip_ver == 1) {
/* TOUCH sensor can provide additional current to external XTAL.
In some case, X32N and X32P PAD don't have enough drive capability to start XTAL */
@@ -95,13 +95,13 @@ void rtc_clk_32k_enable(bool enable)
CLEAR_PERI_REG_MASK(RTC_IO_XTAL_32K_PAD_REG, RTC_IO_X32N_MUX_SEL | RTC_IO_X32P_MUX_SEL);
#ifdef CONFIG_RTC_EXT_CRYST_ADDIT_CURRENT
uint8_t chip_ver = efuse_hal_get_chip_revision();
uint8_t chip_ver = efuse_hal_get_major_chip_version();
if(chip_ver == 0 || chip_ver == 1) {
/* Power down TOUCH */
CLEAR_PERI_REG_MASK(RTC_IO_TOUCH_PAD9_REG, RTC_IO_TOUCH_PAD9_XPD_M);
}
#elif defined CONFIG_RTC_EXT_CRYST_ADDIT_CURRENT_V2
uint8_t chip_ver = efuse_hal_get_chip_revision();
uint8_t chip_ver = efuse_hal_get_major_chip_version();
if(chip_ver == 0 || chip_ver == 1) {
/* Power down TOUCH */
CLEAR_PERI_REG_MASK(RTC_IO_TOUCH_CFG_REG, RTC_IO_TOUCH_XPD_BIAS_M);
components/esp_hw_support/port/esp32c2/chip_info.c
+1 -1
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@@ -12,7 +12,7 @@ void esp_chip_info(esp_chip_info_t *out_info)
{
memset(out_info, 0, sizeof(*out_info));
out_info->model = CHIP_ESP32C2;
out_info->revision = efuse_hal_get_chip_revision();
out_info->revision = efuse_hal_chip_revision();
out_info->cores = 1;
out_info->features = CHIP_FEATURE_WIFI_BGN | CHIP_FEATURE_BLE;
}
components/esp_hw_support/port/esp32c2/rtc_init.c
+3 -2
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@@ -14,6 +14,7 @@
#include "soc/spi_mem_reg.h"
#include "soc/extmem_reg.h"
#include "soc/system_reg.h"
#include "hal/efuse_hal.h"
#include "regi2c_ctrl.h"
#include "soc/regi2c_dig_reg.h"
#include "soc/regi2c_lp_bias.h"
@@ -38,7 +39,7 @@ void rtc_init(rtc_config_t cfg)
if (cfg.cali_ocode) {
uint32_t rtc_calib_version = 0;
esp_err_t err = esp_efuse_read_field_blob(ESP_EFUSE_BLOCK2_VERSION, &rtc_calib_version, 3);
esp_err_t err = esp_efuse_read_field_blob(ESP_EFUSE_BLK_VERSION_MINOR, &rtc_calib_version, ESP_EFUSE_BLK_VERSION_MINOR[0]->bit_count); // IDF-5366
if (err != ESP_OK) {
rtc_calib_version = 0;
ESP_HW_LOGW(TAG, "efuse read fail, set default rtc_calib_version: %d\n", rtc_calib_version);
@@ -248,7 +249,7 @@ static void set_rtc_dig_dbias()
3. a reasonable rtc_dbias can be calculated by a certion formula.
*/
uint32_t rtc_dbias = 31, dig_dbias = 26;
uint8_t chip_version = esp_efuse_get_chip_ver();
uint8_t chip_version = efuse_hal_get_minor_chip_version();
if (chip_version >= 3) {
dig_dbias = get_dig_dbias_by_efuse(chip_version);
if (dig_dbias != 0) {
components/esp_hw_support/port/esp32c3/chip_info.c
+1 -1
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@@ -12,7 +12,7 @@ void esp_chip_info(esp_chip_info_t *out_info)
{
memset(out_info, 0, sizeof(*out_info));
out_info->model = CHIP_ESP32C3;
out_info->revision = efuse_hal_get_chip_revision();
out_info->revision = efuse_hal_chip_revision();
out_info->cores = 1;
out_info->features = CHIP_FEATURE_WIFI_BGN | CHIP_FEATURE_BLE;
}
components/esp_hw_support/port/esp32c3/rtc_init.c
+3 -2
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@@ -14,6 +14,7 @@
#include "soc/spi_mem_reg.h"
#include "soc/extmem_reg.h"
#include "soc/system_reg.h"
#include "hal/efuse_hal.h"
#include "regi2c_ctrl.h"
#include "soc/regi2c_dig_reg.h"
#include "soc/regi2c_lp_bias.h"
@@ -52,7 +53,7 @@ void rtc_init(rtc_config_t cfg)
if (cfg.cali_ocode) {
uint32_t rtc_calib_version = 0;
esp_err_t err = esp_efuse_read_field_blob(ESP_EFUSE_BLOCK2_VERSION, &rtc_calib_version, 3);
esp_err_t err = esp_efuse_read_field_blob(ESP_EFUSE_BLK_VERSION_MAJOR, &rtc_calib_version, ESP_EFUSE_BLK_VERSION_MAJOR[0]->bit_count); // IDF-5366
if (err != ESP_OK) {
rtc_calib_version = 0;
ESP_HW_LOGW(TAG, "efuse read fail, set default rtc_calib_version: %d\n", rtc_calib_version);
@@ -316,7 +317,7 @@ static void set_rtc_dig_dbias()
3. a reasonable rtc_dbias can be calculated by a certion formula.
*/
uint32_t rtc_dbias = 28, dig_dbias = 28;
uint8_t chip_version = esp_efuse_get_chip_ver();
uint8_t chip_version = efuse_hal_get_minor_chip_version();
if (chip_version >= 3) {
dig_dbias = get_dig_dbias_by_efuse(chip_version);
if (dig_dbias != 0) {
components/esp_hw_support/port/esp32c3/rtc_sleep.c
+2 -2
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@@ -21,7 +21,7 @@
#include "regi2c_ctrl.h"
#include "soc/regi2c_dig_reg.h"
#include "soc/regi2c_lp_bias.h"
#include "esp_efuse.h"
#include "hal/efuse_hal.h"
/**
* Configure whether certain peripherals are powered down in deep sleep
@@ -77,7 +77,7 @@ void rtc_sleep_get_default_config(uint32_t sleep_flags, rtc_sleep_config_t *out_
if (sleep_flags & RTC_SLEEP_PD_DIG) {
unsigned atten_deep_sleep = RTC_CNTL_DBG_ATTEN_DEEPSLEEP_DEFAULT;
#if CONFIG_ESP32C3_REV_MIN < 3
if (esp_efuse_get_chip_ver() < 3) {
if (efuse_hal_get_minor_chip_version() < 3) {
atten_deep_sleep = 0; /* workaround for deep sleep issue in high temp on ECO2 and below */
}
#endif
components/esp_hw_support/port/esp32h2/chip_info.c
+1 -1
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@@ -12,7 +12,7 @@ void esp_chip_info(esp_chip_info_t *out_info)
{
memset(out_info, 0, sizeof(*out_info));
out_info->model = CHIP_ESP32H2;
out_info->revision = efuse_hal_get_chip_revision();
out_info->revision = efuse_hal_chip_revision();
out_info->cores = 1;
out_info->features = CHIP_FEATURE_IEEE802154 | CHIP_FEATURE_BLE;
}
components/esp_hw_support/port/esp32s2/chip_info.c
+2
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@@ -7,6 +7,7 @@
#include <string.h>
#include "esp_chip_info.h"
#include "hal/efuse_ll.h"
#include "hal/efuse_hal.h"
void esp_chip_info(esp_chip_info_t *out_info)
{
@@ -15,6 +16,7 @@ void esp_chip_info(esp_chip_info_t *out_info)
memset(out_info, 0, sizeof(*out_info));
out_info->model = CHIP_ESP32S2;
out_info->revision = efuse_hal_chip_revision();
out_info->cores = 1;
out_info->features = CHIP_FEATURE_WIFI_BGN;
components/esp_hw_support/port/esp32s2/rtc_init.c
+1 -1
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@@ -152,7 +152,7 @@ void rtc_init(rtc_config_t cfg)
#if !CONFIG_IDF_ENV_FPGA
if (cfg.cali_ocode) {
uint32_t rtc_calib_version = 0;
esp_efuse_read_field_blob(ESP_EFUSE_BLOCK2_VERSION, &rtc_calib_version, 32);
esp_efuse_read_field_blob(ESP_EFUSE_BLK_VERSION_MINOR, &rtc_calib_version, ESP_EFUSE_BLK_VERSION_MINOR[0]->bit_count); // IDF-5366
if (rtc_calib_version == 2) {
set_ocode_by_efuse(rtc_calib_version);
} else {
components/esp_hw_support/port/esp32s3/chip_info.c
+2
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@@ -6,11 +6,13 @@
#include <string.h>
#include "esp_chip_info.h"
#include "hal/efuse_hal.h"
void esp_chip_info(esp_chip_info_t *out_info)
{
memset(out_info, 0, sizeof(*out_info));
out_info->model = CHIP_ESP32S3;
out_info->revision = efuse_hal_chip_revision();
out_info->cores = 2;
out_info->features = CHIP_FEATURE_WIFI_BGN | CHIP_FEATURE_BLE;
}
components/esp_hw_support/port/esp32s3/rtc_init.c
+1 -1
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@@ -74,7 +74,7 @@ void rtc_init(rtc_config_t cfg)
if (cfg.cali_ocode) {
uint32_t blk_ver_major = 0;
esp_err_t err = esp_efuse_read_field_blob(ESP_EFUSE_BLK_VER_MAJOR, &blk_ver_major, ESP_EFUSE_BLK_VER_MAJOR[0]->bit_count);
esp_err_t err = esp_efuse_read_field_blob(ESP_EFUSE_BLK_VERSION_MAJOR, &blk_ver_major, ESP_EFUSE_BLK_VERSION_MAJOR[0]->bit_count); // IDF-5366
if (err != ESP_OK) {
blk_ver_major = 0;
ESP_HW_LOGW(TAG, "efuse read fail, set default blk_ver_major: %d\n", blk_ver_major);