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fix(esp_driver_gpio): esp32c61 gpio number update 22 -> 25

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This commit is contained in:
wanckl
2024-11-08 10:36:20 +08:00
parent 5e056de1e7
commit a50c095df1
14 changed files with 483 additions and 56 deletions
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components/soc/esp32c61/gpio_periph.c
+3
View File
@@ -29,6 +29,9 @@ const uint32_t GPIO_HOLD_MASK[] = {
BIT(19), //GPIO19
BIT(20), //GPIO20
BIT(21), //GPIO21
BIT(22), //GPIO22
BIT(23), //GPIO23
BIT(24), //GPIO24
};
_Static_assert(sizeof(GPIO_HOLD_MASK) == SOC_GPIO_PIN_COUNT * sizeof(uint32_t), "Invalid size of GPIO_HOLD_MASK");
components/soc/esp32c61/include/soc/Kconfig.soc_caps.in
+4 -4
View File
@@ -301,7 +301,7 @@ config SOC_GPIO_PORT
config SOC_GPIO_PIN_COUNT
int
default 22
default 25
config SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER
bool
@@ -325,11 +325,11 @@ config SOC_LP_IO_CLOCK_IS_INDEPENDENT
config SOC_GPIO_IN_RANGE_MAX
int
default 21
default 24
config SOC_GPIO_OUT_RANGE_MAX
int
default 21
default 24
config SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP
bool
@@ -345,7 +345,7 @@ config SOC_GPIO_DEEP_SLEEP_WAKE_SUPPORTED_PIN_CNT
config SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK
hex
default 0x00000000003FFF80
default 0x1FFFF80
config SOC_GPIO_SUPPORT_FORCE_HOLD
bool
components/soc/esp32c61/include/soc/gpio_num.h
+3
View File
@@ -37,6 +37,9 @@ typedef enum {
GPIO_NUM_19 = 19, /*!< GPIO19, input and output */
GPIO_NUM_20 = 20, /*!< GPIO20, input and output */
GPIO_NUM_21 = 21, /*!< GPIO21, input and output */
GPIO_NUM_22 = 22, /*!< GPIO22, input and output */
GPIO_NUM_23 = 23, /*!< GPIO23, input and output */
GPIO_NUM_24 = 24, /*!< GPIO24, input and output */
GPIO_NUM_MAX,
} gpio_num_t;
components/soc/esp32c61/include/soc/soc_caps.h
+6 -6
View File
@@ -159,7 +159,7 @@
/*-------------------------- GPIO CAPS ---------------------------------------*/
// ESP32-C61 has 1 GPIO peripheral
#define SOC_GPIO_PORT 1U
#define SOC_GPIO_PIN_COUNT 22
#define SOC_GPIO_PIN_COUNT 25
#define SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER 1
#define SOC_GPIO_SUPPORT_PIN_HYS_FILTER 1
@@ -173,19 +173,19 @@
// LP IO peripherals have independent clock gating to manage
#define SOC_LP_IO_CLOCK_IS_INDEPENDENT (1)
#define SOC_GPIO_VALID_GPIO_MASK ((1U<<SOC_GPIO_PIN_COUNT) - 1)
#define SOC_GPIO_VALID_GPIO_MASK ((1ULL<<SOC_GPIO_PIN_COUNT) - 1)
#define SOC_GPIO_VALID_OUTPUT_GPIO_MASK SOC_GPIO_VALID_GPIO_MASK
#define SOC_GPIO_IN_RANGE_MAX 21
#define SOC_GPIO_OUT_RANGE_MAX 21
#define SOC_GPIO_IN_RANGE_MAX 24
#define SOC_GPIO_OUT_RANGE_MAX 24
// GPIO0~6 on ESP32C61 can support chip deep sleep wakeup
#define SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP (1)
#define SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK (0ULL | BIT0 | BIT1 | BIT2 | BIT3 | BIT4 | BIT5 | BIT6)
#define SOC_GPIO_DEEP_SLEEP_WAKE_SUPPORTED_PIN_CNT (7)
// digital I/O pad powered by VDD3P3_CPU or VDD_SPI(GPIO_NUM_7~GPIO_NUM_21)
#define SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK 0x00000000003FFF80ULL
// digital I/O pad powered by VDD3P3_CPU or VDD_SPI(GPIO_NUM_7~GPIO_NUM_24)
#define SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK 0x1FFFF80ULL
// Support to force hold all IOs
#define SOC_GPIO_SUPPORT_FORCE_HOLD (1)
components/soc/esp32c61/register/soc/gpio_reg.h
+375
View File
@@ -1844,6 +1844,225 @@ extern "C" {
#define GPIO_PIN21_INT_ENA_V 0x0000001FU
#define GPIO_PIN21_INT_ENA_S 13
/** GPIO_PIN22_REG register
* GPIO22 configuration register
*/
#define GPIO_PIN22_REG (DR_REG_GPIO_BASE + 0x11c)
/** GPIO_PIN22_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
* Configures whether or not to synchronize GPIO input data on either edge of IO MUX
* operating clock for the second-level synchronization.\\
* 0: Not synchronize\\
* 1: Synchronize on falling edge\\
* 2: Synchronize on rising edge\\
* 3: Synchronize on rising edge\\
*/
#define GPIO_PIN22_SYNC2_BYPASS 0x00000003U
#define GPIO_PIN22_SYNC2_BYPASS_M (GPIO_PIN22_SYNC2_BYPASS_V << GPIO_PIN22_SYNC2_BYPASS_S)
#define GPIO_PIN22_SYNC2_BYPASS_V 0x00000003U
#define GPIO_PIN22_SYNC2_BYPASS_S 0
/** GPIO_PIN22_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
* Configures to select pin drive mode. \\
* 0: Normal output\\
* 1: Open drain output \\
*/
#define GPIO_PIN22_PAD_DRIVER (BIT(2))
#define GPIO_PIN22_PAD_DRIVER_M (GPIO_PIN22_PAD_DRIVER_V << GPIO_PIN22_PAD_DRIVER_S)
#define GPIO_PIN22_PAD_DRIVER_V 0x00000001U
#define GPIO_PIN22_PAD_DRIVER_S 2
/** GPIO_PIN22_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
* Configures whether or not to synchronize GPIO input data on either edge of IO MUX
* operating clock for the first-level synchronization.\\
* 0: Not synchronize\\
* 1: Synchronize on falling edge\\
* 2: Synchronize on rising edge\\
* 3: Synchronize on rising edge\\
*/
#define GPIO_PIN22_SYNC1_BYPASS 0x00000003U
#define GPIO_PIN22_SYNC1_BYPASS_M (GPIO_PIN22_SYNC1_BYPASS_V << GPIO_PIN22_SYNC1_BYPASS_S)
#define GPIO_PIN22_SYNC1_BYPASS_V 0x00000003U
#define GPIO_PIN22_SYNC1_BYPASS_S 3
/** GPIO_PIN22_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
* Configures GPIO interrupt type.\\
* 0: GPIO interrupt disabled\\
* 1: Rising edge trigger\\
* 2: Falling edge trigger\\
* 3: Any edge trigger\\
* 4: Low level trigger\\
* 5: High level trigger\\
*/
#define GPIO_PIN22_INT_TYPE 0x00000007U
#define GPIO_PIN22_INT_TYPE_M (GPIO_PIN22_INT_TYPE_V << GPIO_PIN22_INT_TYPE_S)
#define GPIO_PIN22_INT_TYPE_V 0x00000007U
#define GPIO_PIN22_INT_TYPE_S 7
/** GPIO_PIN22_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
* Configures whether or not to enable GPIO wake-up function.\\
* 0: Disable\\
* 1: Enable\\
* This function only wakes up the CPU from Light-sleep. \\
*/
#define GPIO_PIN22_WAKEUP_ENABLE (BIT(10))
#define GPIO_PIN22_WAKEUP_ENABLE_M (GPIO_PIN22_WAKEUP_ENABLE_V << GPIO_PIN22_WAKEUP_ENABLE_S)
#define GPIO_PIN22_WAKEUP_ENABLE_V 0x00000001U
#define GPIO_PIN22_WAKEUP_ENABLE_S 10
/** GPIO_PIN22_INT_ENA : R/W; bitpos: [17:13]; default: 0;
* Configures whether or not to enable CPU interrupt.
*
* - bit13: Configures whether or not to enable CPU interrupt:\\
* 0: Disable\\
* 1: Enable\\
* - bit14 ~ bit17: invalid
*/
#define GPIO_PIN22_INT_ENA 0x0000001FU
#define GPIO_PIN22_INT_ENA_M (GPIO_PIN22_INT_ENA_V << GPIO_PIN22_INT_ENA_S)
#define GPIO_PIN22_INT_ENA_V 0x0000001FU
#define GPIO_PIN22_INT_ENA_S 13
/** GPIO_PIN23_REG register
* GPIO23 configuration register
*/
#define GPIO_PIN23_REG (DR_REG_GPIO_BASE + 0x120)
/** GPIO_PIN23_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
* Configures whether or not to synchronize GPIO input data on either edge of IO MUX
* operating clock for the second-level synchronization.\\
* 0: Not synchronize\\
* 1: Synchronize on falling edge\\
* 2: Synchronize on rising edge\\
* 3: Synchronize on rising edge\\
*/
#define GPIO_PIN23_SYNC2_BYPASS 0x00000003U
#define GPIO_PIN23_SYNC2_BYPASS_M (GPIO_PIN23_SYNC2_BYPASS_V << GPIO_PIN23_SYNC2_BYPASS_S)
#define GPIO_PIN23_SYNC2_BYPASS_V 0x00000003U
#define GPIO_PIN23_SYNC2_BYPASS_S 0
/** GPIO_PIN23_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
* Configures to select pin drive mode. \\
* 0: Normal output\\
* 1: Open drain output \\
*/
#define GPIO_PIN23_PAD_DRIVER (BIT(2))
#define GPIO_PIN23_PAD_DRIVER_M (GPIO_PIN23_PAD_DRIVER_V << GPIO_PIN23_PAD_DRIVER_S)
#define GPIO_PIN23_PAD_DRIVER_V 0x00000001U
#define GPIO_PIN23_PAD_DRIVER_S 2
/** GPIO_PIN23_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
* Configures whether or not to synchronize GPIO input data on either edge of IO MUX
* operating clock for the first-level synchronization.\\
* 0: Not synchronize\\
* 1: Synchronize on falling edge\\
* 2: Synchronize on rising edge\\
* 3: Synchronize on rising edge\\
*/
#define GPIO_PIN23_SYNC1_BYPASS 0x00000003U
#define GPIO_PIN23_SYNC1_BYPASS_M (GPIO_PIN23_SYNC1_BYPASS_V << GPIO_PIN23_SYNC1_BYPASS_S)
#define GPIO_PIN23_SYNC1_BYPASS_V 0x00000003U
#define GPIO_PIN23_SYNC1_BYPASS_S 3
/** GPIO_PIN23_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
* Configures GPIO interrupt type.\\
* 0: GPIO interrupt disabled\\
* 1: Rising edge trigger\\
* 2: Falling edge trigger\\
* 3: Any edge trigger\\
* 4: Low level trigger\\
* 5: High level trigger\\
*/
#define GPIO_PIN23_INT_TYPE 0x00000007U
#define GPIO_PIN23_INT_TYPE_M (GPIO_PIN23_INT_TYPE_V << GPIO_PIN23_INT_TYPE_S)
#define GPIO_PIN23_INT_TYPE_V 0x00000007U
#define GPIO_PIN23_INT_TYPE_S 7
/** GPIO_PIN23_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
* Configures whether or not to enable GPIO wake-up function.\\
* 0: Disable\\
* 1: Enable\\
* This function only wakes up the CPU from Light-sleep. \\
*/
#define GPIO_PIN23_WAKEUP_ENABLE (BIT(10))
#define GPIO_PIN23_WAKEUP_ENABLE_M (GPIO_PIN23_WAKEUP_ENABLE_V << GPIO_PIN23_WAKEUP_ENABLE_S)
#define GPIO_PIN23_WAKEUP_ENABLE_V 0x00000001U
#define GPIO_PIN23_WAKEUP_ENABLE_S 10
/** GPIO_PIN23_INT_ENA : R/W; bitpos: [17:13]; default: 0;
* Configures whether or not to enable CPU interrupt.
*
* - bit13: Configures whether or not to enable CPU interrupt:\\
* 0: Disable\\
* 1: Enable\\
* - bit14 ~ bit17: invalid
*/
#define GPIO_PIN23_INT_ENA 0x0000001FU
#define GPIO_PIN23_INT_ENA_M (GPIO_PIN23_INT_ENA_V << GPIO_PIN23_INT_ENA_S)
#define GPIO_PIN23_INT_ENA_V 0x0000001FU
#define GPIO_PIN23_INT_ENA_S 13
/** GPIO_PIN24_REG register
* GPIO24 configuration register
*/
#define GPIO_PIN24_REG (DR_REG_GPIO_BASE + 0x124)
/** GPIO_PIN24_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
* Configures whether or not to synchronize GPIO input data on either edge of IO MUX
* operating clock for the second-level synchronization.\\
* 0: Not synchronize\\
* 1: Synchronize on falling edge\\
* 2: Synchronize on rising edge\\
* 3: Synchronize on rising edge\\
*/
#define GPIO_PIN24_SYNC2_BYPASS 0x00000003U
#define GPIO_PIN24_SYNC2_BYPASS_M (GPIO_PIN24_SYNC2_BYPASS_V << GPIO_PIN24_SYNC2_BYPASS_S)
#define GPIO_PIN24_SYNC2_BYPASS_V 0x00000003U
#define GPIO_PIN24_SYNC2_BYPASS_S 0
/** GPIO_PIN24_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
* Configures to select pin drive mode. \\
* 0: Normal output\\
* 1: Open drain output \\
*/
#define GPIO_PIN24_PAD_DRIVER (BIT(2))
#define GPIO_PIN24_PAD_DRIVER_M (GPIO_PIN24_PAD_DRIVER_V << GPIO_PIN24_PAD_DRIVER_S)
#define GPIO_PIN24_PAD_DRIVER_V 0x00000001U
#define GPIO_PIN24_PAD_DRIVER_S 2
/** GPIO_PIN24_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
* Configures whether or not to synchronize GPIO input data on either edge of IO MUX
* operating clock for the first-level synchronization.\\
* 0: Not synchronize\\
* 1: Synchronize on falling edge\\
* 2: Synchronize on rising edge\\
* 3: Synchronize on rising edge\\
*/
#define GPIO_PIN24_SYNC1_BYPASS 0x00000003U
#define GPIO_PIN24_SYNC1_BYPASS_M (GPIO_PIN24_SYNC1_BYPASS_V << GPIO_PIN24_SYNC1_BYPASS_S)
#define GPIO_PIN24_SYNC1_BYPASS_V 0x00000003U
#define GPIO_PIN24_SYNC1_BYPASS_S 3
/** GPIO_PIN24_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
* Configures GPIO interrupt type.\\
* 0: GPIO interrupt disabled\\
* 1: Rising edge trigger\\
* 2: Falling edge trigger\\
* 3: Any edge trigger\\
* 4: Low level trigger\\
* 5: High level trigger\\
*/
#define GPIO_PIN24_INT_TYPE 0x00000007U
#define GPIO_PIN24_INT_TYPE_M (GPIO_PIN24_INT_TYPE_V << GPIO_PIN24_INT_TYPE_S)
#define GPIO_PIN24_INT_TYPE_V 0x00000007U
#define GPIO_PIN24_INT_TYPE_S 7
/** GPIO_PIN24_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
* Configures whether or not to enable GPIO wake-up function.\\
* 0: Disable\\
* 1: Enable\\
* This function only wakes up the CPU from Light-sleep. \\
*/
#define GPIO_PIN24_WAKEUP_ENABLE (BIT(10))
#define GPIO_PIN24_WAKEUP_ENABLE_M (GPIO_PIN24_WAKEUP_ENABLE_V << GPIO_PIN24_WAKEUP_ENABLE_S)
#define GPIO_PIN24_WAKEUP_ENABLE_V 0x00000001U
#define GPIO_PIN24_WAKEUP_ENABLE_S 10
/** GPIO_PIN24_INT_ENA : R/W; bitpos: [17:13]; default: 0;
* Configures whether or not to enable CPU interrupt.
*
* - bit13: Configures whether or not to enable CPU interrupt:\\
* 0: Disable\\
* 1: Enable\\
* - bit14 ~ bit17: invalid
*/
#define GPIO_PIN24_INT_ENA 0x0000001FU
#define GPIO_PIN24_INT_ENA_M (GPIO_PIN24_INT_ENA_V << GPIO_PIN24_INT_ENA_S)
#define GPIO_PIN24_INT_ENA_V 0x0000001FU
#define GPIO_PIN24_INT_ENA_S 13
/** GPIO_FUNC0_IN_SEL_CFG_REG register
* Configuration register for input signal 0
*/
@@ -4782,6 +5001,162 @@ extern "C" {
#define GPIO_FUNC21_OE_INV_SEL_V 0x00000001U
#define GPIO_FUNC21_OE_INV_SEL_S 11
/** GPIO_FUNC22_OUT_SEL_CFG_REG register
* Configuration register for GPIO22 output
*/
#define GPIO_FUNC22_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb1c)
/** GPIO_FUNC22_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
* Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be
* output from GPIO22.\\
* 0: Select signal 0\\
* 1: Select signal 1\\
* ......\\
* 254: Select signal 254\\
* 255: Select signal 255\\
* Or\\
* 256: Bit 22 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value
* and output enable.
*
* For the detailed signal list, see Table <a
* href=tab:iomuxgpio-periph-signals-via-gpio-matrix">link</a>.
* "
*/
#define GPIO_FUNC22_OUT_SEL 0x000001FFU
#define GPIO_FUNC22_OUT_SEL_M (GPIO_FUNC22_OUT_SEL_V << GPIO_FUNC22_OUT_SEL_S)
#define GPIO_FUNC22_OUT_SEL_V 0x000001FFU
#define GPIO_FUNC22_OUT_SEL_S 0
/** GPIO_FUNC22_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
* Configures whether or not to invert the output value.\\
* 0: Not invert\\
* 1: Invert\\
*/
#define GPIO_FUNC22_OUT_INV_SEL (BIT(9))
#define GPIO_FUNC22_OUT_INV_SEL_M (GPIO_FUNC22_OUT_INV_SEL_V << GPIO_FUNC22_OUT_INV_SEL_S)
#define GPIO_FUNC22_OUT_INV_SEL_V 0x00000001U
#define GPIO_FUNC22_OUT_INV_SEL_S 9
/** GPIO_FUNC22_OE_SEL : R/W; bitpos: [10]; default: 0;
* Configures to select the source of output enable signal.\\
* 0: Use output enable signal from peripheral.\\
* 1: Force the output enable signal to be sourced from bit 22 of GPIO_ENABLE_REG. \\
*/
#define GPIO_FUNC22_OE_SEL (BIT(10))
#define GPIO_FUNC22_OE_SEL_M (GPIO_FUNC22_OE_SEL_V << GPIO_FUNC22_OE_SEL_S)
#define GPIO_FUNC22_OE_SEL_V 0x00000001U
#define GPIO_FUNC22_OE_SEL_S 10
/** GPIO_FUNC22_OE_INV_SEL : R/W; bitpos: [11]; default: 0;
* Configures whether or not to invert the output enable signal.\\
* 0: Not invert\\
* 1: Invert\\
*/
#define GPIO_FUNC22_OE_INV_SEL (BIT(11))
#define GPIO_FUNC22_OE_INV_SEL_M (GPIO_FUNC22_OE_INV_SEL_V << GPIO_FUNC22_OE_INV_SEL_S)
#define GPIO_FUNC22_OE_INV_SEL_V 0x00000001U
#define GPIO_FUNC22_OE_INV_SEL_S 11
/** GPIO_FUNC23_OUT_SEL_CFG_REG register
* Configuration register for GPIO23 output
*/
#define GPIO_FUNC23_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb20)
/** GPIO_FUNC23_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
* Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be
* output from GPIO23.\\
* 0: Select signal 0\\
* 1: Select signal 1\\
* ......\\
* 254: Select signal 254\\
* 255: Select signal 255\\
* Or\\
* 256: Bit 23 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value
* and output enable.
*
* For the detailed signal list, see Table <a
* href=tab:iomuxgpio-periph-signals-via-gpio-matrix">link</a>.
* "
*/
#define GPIO_FUNC23_OUT_SEL 0x000001FFU
#define GPIO_FUNC23_OUT_SEL_M (GPIO_FUNC23_OUT_SEL_V << GPIO_FUNC23_OUT_SEL_S)
#define GPIO_FUNC23_OUT_SEL_V 0x000001FFU
#define GPIO_FUNC23_OUT_SEL_S 0
/** GPIO_FUNC23_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
* Configures whether or not to invert the output value.\\
* 0: Not invert\\
* 1: Invert\\
*/
#define GPIO_FUNC23_OUT_INV_SEL (BIT(9))
#define GPIO_FUNC23_OUT_INV_SEL_M (GPIO_FUNC23_OUT_INV_SEL_V << GPIO_FUNC23_OUT_INV_SEL_S)
#define GPIO_FUNC23_OUT_INV_SEL_V 0x00000001U
#define GPIO_FUNC23_OUT_INV_SEL_S 9
/** GPIO_FUNC23_OE_SEL : R/W; bitpos: [10]; default: 0;
* Configures to select the source of output enable signal.\\
* 0: Use output enable signal from peripheral.\\
* 1: Force the output enable signal to be sourced from bit 23 of GPIO_ENABLE_REG. \\
*/
#define GPIO_FUNC23_OE_SEL (BIT(10))
#define GPIO_FUNC23_OE_SEL_M (GPIO_FUNC23_OE_SEL_V << GPIO_FUNC23_OE_SEL_S)
#define GPIO_FUNC23_OE_SEL_V 0x00000001U
#define GPIO_FUNC23_OE_SEL_S 10
/** GPIO_FUNC23_OE_INV_SEL : R/W; bitpos: [11]; default: 0;
* Configures whether or not to invert the output enable signal.\\
* 0: Not invert\\
* 1: Invert\\
*/
#define GPIO_FUNC23_OE_INV_SEL (BIT(11))
#define GPIO_FUNC23_OE_INV_SEL_M (GPIO_FUNC23_OE_INV_SEL_V << GPIO_FUNC23_OE_INV_SEL_S)
#define GPIO_FUNC23_OE_INV_SEL_V 0x00000001U
#define GPIO_FUNC23_OE_INV_SEL_S 11
/** GPIO_FUNC24_OUT_SEL_CFG_REG register
* Configuration register for GPIO24 output
*/
#define GPIO_FUNC24_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb24)
/** GPIO_FUNC24_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
* Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be
* output from GPIO24.\\
* 0: Select signal 0\\
* 1: Select signal 1\\
* ......\\
* 254: Select signal 254\\
* 255: Select signal 255\\
* Or\\
* 256: Bit 24 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value
* and output enable.
*
* For the detailed signal list, see Table <a
* href=tab:iomuxgpio-periph-signals-via-gpio-matrix">link</a>.
* "
*/
#define GPIO_FUNC24_OUT_SEL 0x000001FFU
#define GPIO_FUNC24_OUT_SEL_M (GPIO_FUNC24_OUT_SEL_V << GPIO_FUNC24_OUT_SEL_S)
#define GPIO_FUNC24_OUT_SEL_V 0x000001FFU
#define GPIO_FUNC24_OUT_SEL_S 0
/** GPIO_FUNC24_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
* Configures whether or not to invert the output value.\\
* 0: Not invert\\
* 1: Invert\\
*/
#define GPIO_FUNC24_OUT_INV_SEL (BIT(9))
#define GPIO_FUNC24_OUT_INV_SEL_M (GPIO_FUNC24_OUT_INV_SEL_V << GPIO_FUNC24_OUT_INV_SEL_S)
#define GPIO_FUNC24_OUT_INV_SEL_V 0x00000001U
#define GPIO_FUNC24_OUT_INV_SEL_S 9
/** GPIO_FUNC24_OE_SEL : R/W; bitpos: [10]; default: 0;
* Configures to select the source of output enable signal.\\
* 0: Use output enable signal from peripheral.\\
* 1: Force the output enable signal to be sourced from bit 24 of GPIO_ENABLE_REG. \\
*/
#define GPIO_FUNC24_OE_SEL (BIT(10))
#define GPIO_FUNC24_OE_SEL_M (GPIO_FUNC24_OE_SEL_V << GPIO_FUNC24_OE_SEL_S)
#define GPIO_FUNC24_OE_SEL_V 0x00000001U
#define GPIO_FUNC24_OE_SEL_S 10
/** GPIO_FUNC24_OE_INV_SEL : R/W; bitpos: [11]; default: 0;
* Configures whether or not to invert the output enable signal.\\
* 0: Not invert\\
* 1: Invert\\
*/
#define GPIO_FUNC24_OE_INV_SEL (BIT(11))
#define GPIO_FUNC24_OE_INV_SEL_M (GPIO_FUNC24_OE_INV_SEL_V << GPIO_FUNC24_OE_INV_SEL_S)
#define GPIO_FUNC24_OE_INV_SEL_V 0x00000001U
#define GPIO_FUNC24_OE_INV_SEL_S 11
/** GPIO_CLOCK_GATE_REG register
* GPIO clock gate register
*/
components/soc/esp32c61/register/soc/gpio_struct.h
+4 -4
View File
@@ -468,12 +468,12 @@ typedef struct {
uint32_t reserved_0a8[3];
volatile gpio_status_next_reg_t status_next;
uint32_t reserved_0b8[3];
volatile gpio_pinn_reg_t pinn[22]; // 0-21 are fanned out, 22-24 are not fanned out but padded out, 25-28 are not padded out. Only 0-21 are available.
uint32_t reserved_11c[106];
volatile gpio_pinn_reg_t pinn[25]; // 0-24 are fanned out, 25-28 are not padded out. Only 0-24 are available.
uint32_t reserved_128[103];
volatile gpio_func_in_sel_cfg_reg_t func_in_sel_cfg[256]; //0-255. reserved: 1-5, 18-26, 36-40, 44-45, 48-63, 70-71, 75-81, 84-96, 101-117, 122-255;
uint32_t reserved_4ac[256];
volatile gpio_funcn_out_sel_cfg_reg_t funcn_out_sel_cfg[22];
uint32_t reserved_b1c[183];
volatile gpio_funcn_out_sel_cfg_reg_t funcn_out_sel_cfg[25];
uint32_t reserved_b28[180];
volatile gpio_clock_gate_reg_t clock_gate;
volatile gpio_date_reg_t date;
} gpio_dev_t;
components/soc/esp32c61/register/soc/io_mux_reg.h
+16 -1
View File
@@ -117,6 +117,9 @@ extern "C" {
#define IO_MUX_GPIO19_REG PERIPHS_IO_MUX_U_PAD_SPIHD
#define IO_MUX_GPIO20_REG PERIPHS_IO_MUX_U_PAD_SPICLK
#define IO_MUX_GPIO21_REG PERIPHS_IO_MUX_U_PAD_SPID
#define IO_MUX_GPIO22_REG PERIPHS_IO_MUX_U_PAD_GPIO22
#define IO_MUX_GPIO23_REG PERIPHS_IO_MUX_U_PAD_GPIO23
#define IO_MUX_GPIO24_REG PERIPHS_IO_MUX_U_PAD_GPIO24
#define PIN_FUNC_GPIO 1
@@ -130,7 +133,7 @@ extern "C" {
#define EXT_OSC_SLOW_GPIO_NUM 0
#define MAX_RTC_GPIO_NUM 6
#define MAX_PAD_GPIO_NUM 21
#define MAX_PAD_GPIO_NUM 24
#define MAX_GPIO_NUM 28
#define HIGH_IO_HOLD_BIT_SHIFT 32
@@ -232,6 +235,18 @@ extern "C" {
#define FUNC_SPID_GPIO21 1
#define FUNC_SPID_SPID 0
#define PERIPHS_IO_MUX_U_PAD_GPIO22 (REG_IO_MUX_BASE + 0x58)
#define FUNC_GPIO22_GPIO22 1
#define FUNC_GPIO22_GPIO22_0 0
#define PERIPHS_IO_MUX_U_PAD_GPIO23 (REG_IO_MUX_BASE + 0x5C)
#define FUNC_GPIO23_GPIO23 1
#define FUNC_GPIO23_GPIO23_0 0
#define PERIPHS_IO_MUX_U_PAD_GPIO24 (REG_IO_MUX_BASE + 0x60)
#define FUNC_GPIO24_GPIO24 1
#define FUNC_GPIO24_GPIO24_0 0
/** IO_MUX_DATE_REG register
* Version control register
*/
components/soc/esp32c61/register/soc/io_mux_struct.h
+2 -2
View File
@@ -129,8 +129,8 @@ typedef union {
typedef struct {
volatile io_mux_gpion_reg_t gpion[22];
uint32_t reserved_058[105];
volatile io_mux_gpion_reg_t gpion[25];
uint32_t reserved_064[102];
volatile io_mux_date_reg_t date;
} io_mux_dev_t;
components/soc/esp32c61/rtc_io_periph.c
+3
View File
@@ -29,4 +29,7 @@ const int rtc_io_num_map[SOC_GPIO_PIN_COUNT] = {
-1,//GPIO19
-1,//GPIO20
-1,//GPIO21
-1,//GPIO22
-1,//GPIO23
-1,//GPIO24
};