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feat(spi_flash): Adjust flash clock to real 80M clock, and support 32bit address on eco1

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C.S.M
2024-08-01 18:12:51 +08:00
committed by BOT
parent 660de3d5af
commit a4fbcae397
18 changed files with 242 additions and 29 deletions
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components/esp_rom/patches/esp_rom_spiflash.c
+34 -1
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -14,6 +14,9 @@
#elif CONFIG_IDF_TARGET_ESP32S3
#include "esp32s3/rom/spi_flash.h"
#include "esp32s3/rom/opi_flash.h"
#elif CONFIG_IDF_TARGET_ESP32P4
#include "esp32p4/rom/spi_flash.h"
#include "esp32p4/rom/opi_flash.h"
#endif
#define SPI_IDX 1
@@ -725,6 +728,36 @@ void esp_rom_opiflash_cache_mode_config(esp_rom_spiflash_read_mode_t mode, const
}
}
#elif CONFIG_IDF_TARGET_ESP32P4
extern void esp_rom_spi_set_address_bit_len(int spi, int addr_bits);
void esp_rom_opiflash_cache_mode_config(esp_rom_spiflash_read_mode_t mode, const esp_rom_opiflash_spi0rd_t *cache)
{
esp_rom_spi_set_op_mode(0, mode);
if (cache) {
esp_rom_spi_set_address_bit_len(0, cache->addr_bit_len);
// Patch for ROM function `esp_rom_opiflash_cache_mode_config`, because when dummy is 0,
// `SPI_MEM_USR_DUMMY` should be 0. `esp_rom_opiflash_cache_mode_config` doesn't handle this
// properly.
if (cache->dummy_bit_len == 0) {
REG_CLR_BIT(SPI_MEM_C_USER_REG, SPI_MEM_C_USR_DUMMY);
} else {
REG_SET_BIT(SPI_MEM_C_USER_REG, SPI_MEM_C_USR_DUMMY);
REG_SET_FIELD(SPI_MEM_C_USER1_REG, SPI_MEM_C_USR_DUMMY_CYCLELEN, cache->dummy_bit_len - 1 + rom_spiflash_legacy_data->dummy_len_plus[0]);
}
REG_SET_FIELD(SPI_MEM_C_USER2_REG, SPI_MEM_C_USR_COMMAND_VALUE, cache->cmd);
REG_SET_FIELD(SPI_MEM_C_USER2_REG, SPI_MEM_C_USR_COMMAND_BITLEN, cache->cmd_bit_len - 1);
REG_SET_FIELD(SPI_MEM_C_DDR_REG, SPI_MEM_C_FMEM__VAR_DUMMY, cache->var_dummy_en);
// Make sure CACHE-FLASH control dummy always be high level
REG_SET_BIT(SPI_MEM_C_CTRL_REG, SPI_MEM_C_FDUMMY_RIN);
REG_SET_BIT(SPI_MEM_C_CTRL_REG, SPI_MEM_C_WP_REG);
REG_SET_BIT(SPI_MEM_C_CTRL_REG, SPI_MEM_C_D_POL);
REG_SET_BIT(SPI_MEM_C_CTRL_REG, SPI_MEM_C_Q_POL);
}
}
#endif // IDF_TARGET
#endif // CONFIG_SPI_FLASH_ROM_DRIVER_PATCH