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change(esp_hw_support): refactor pmu/esp_sleep param struct

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This commit is contained in:
hebinglin
2026-07-29 15:23:09 +08:00
parent 33591e16b6
commit a4889bd73d
36 changed files with 212 additions and 267 deletions
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components/esp_hw_support/include/esp_private/esp_pmu.h
+14 -9
View File
@@ -198,6 +198,18 @@ typedef struct {
pmu_context_t * PMU_instance(void);
/**
* @brief Runtime pmu sleep extra arguments
*/
typedef struct {
uint32_t sleep_flags; //!< Power domains to power down and sleep sub-mode flags
uint32_t clk_flags[2]; //!< Sleep clock ICG flags: [0]=bits[31:0], [1]=bits[63:32]
uint32_t adjustment; //!< Total software and hardware time overhead (us)
soc_rtc_slow_clk_src_t slowclk_src; //!< RTC slow clock source used by PMU timing
uint32_t slowclk_period; //!< Recalibrated slow clock period (us, Q13.19)
uint32_t fastclk_period; //!< Recalibrated fast clock period (us, Q13.19)
} pmu_sleep_extra_args_t;
typedef enum pmu_sleep_protect_mode {
PMU_SLEEP_PROTECT_HP_SLEEP = 0,
PMU_SLEEP_PROTECT_XTAL,
@@ -267,19 +279,12 @@ uint32_t pmu_sleep_calculate_hw_wait_time(uint32_t sleep_flags, soc_rtc_slow_clk
/**
* @brief Get default sleep configuration
* @param config pmu_sleep_config instance
* @param sleep_flags flags indicates the power domain that will be powered down and the sleep submode
* @param clk_flags indicates the clock ICG cell that will be ungated
* @param adjustment total software and hardware time overhead
* @param slowclk_src slow clock source of pmu
* @param slowclk_period re-calibrated slow clock period in microseconds,
* Q13.19 fixed point format
* @param fastclk_period re-calibrated fast clock period in microseconds,
* Q13.19 fixed point format
* @param args pmu sleep runtime arguments
* @param dslp configuration for deep sleep mode
* @return hardware time overhead in us
*/
const pmu_sleep_config_t* pmu_sleep_config_default(pmu_sleep_config_t *config, uint32_t sleep_flags, pmu_sleep_clk_icg_flags_t clk_flags, uint32_t adjustment, soc_rtc_slow_clk_src_t slowclk_src, uint32_t slowclk_period, uint32_t fastclk_period, bool dslp);
const pmu_sleep_config_t* pmu_sleep_config_default(pmu_sleep_config_t *config, pmu_sleep_extra_args_t *args, bool dslp);
/**
* @brief Prepare the chip to enter sleep mode
components/esp_hw_support/include/esp_private/esp_sleep_internal.h
+7
View File
@@ -32,6 +32,13 @@ typedef struct {
void esp_sleep_set_sleep_context(esp_sleep_context_t *sleep_ctx);
#endif
/**
* @brief Sleep internal runtime arguments
*/
typedef struct {
uint32_t clk_flags[2]; //!< Sleep clock ICG flags.
} esp_sleep_extra_args_t;
typedef enum {
ESP_SLEEP_RTC_USE_RC_FAST_MODE, //!< The mode requested by RTC peripherals to keep RC_FAST clock on during sleep (both HP_SLEEP and LP_SLEEP mode). (Will override the RC_FAST domain config by esp_sleep_pd_config)
ESP_SLEEP_DIG_USE_RC_FAST_MODE, //!< The mode requested by digital peripherals to keep RC_FAST clock on during sleep (both HP_SLEEP and LP_SLEEP mode). (!!! Only valid for lightsleep, will override the RC_FAST domain config by esp_sleep_pd_config)
components/esp_hw_support/include/esp_private/sleep_clock_icg.h
+4 -1
View File
@@ -23,8 +23,11 @@ extern "C" {
/**
* @brief Convert sleep clock ICG reference counts to PMU ICG flags for HP sleep mode
*
* @param clk_icg0_flags ICG flags bits[31:0]
* @param clk_icg1_flags ICG flags bits[63:32] (0 if the target only has 32-bit ICG)
*/
pmu_sleep_clk_icg_flags_t esp_sleep_clock_get_clk_icg_flags(void);
void esp_sleep_clock_get_clk_icg_flags(uint32_t *clk_icg0_flags, uint32_t *clk_icg1_flags);
#endif /* SOC_PM_SUPPORT_PMU_CLK_ICG */
components/esp_hw_support/lowpower/port/esp32c5/sleep_clock_icg.c
+6 -8
View File
@@ -23,24 +23,22 @@
static int16_t s_sleep_clock_icg_refs[ESP_SLEEP_CLOCK_MAX];
SLEEP_CLOCK_ICG_FN_ATTR uint32_t esp_sleep_clock_get_clk_icg_flags(void)
SLEEP_CLOCK_ICG_FN_ATTR void esp_sleep_clock_get_clk_icg_flags(uint32_t *clk_icg0_flags, uint32_t *clk_icg1_flags)
{
uint32_t icg_flags = 0;
if (s_sleep_clock_icg_refs[ESP_SLEEP_CLOCK_IOMUX] > 0) {
icg_flags |= PMU_SLEEP_CLK_ICG_BIT(PMU_ICG_FUNC_ENA_IOMUX);
*clk_icg0_flags |= PMU_SLEEP_CLK_ICG_BIT(PMU_ICG_FUNC_ENA_IOMUX);
}
if (s_sleep_clock_icg_refs[ESP_SLEEP_CLOCK_LEDC0] > 0) {
icg_flags |= PMU_SLEEP_CLK_ICG_BIT(PMU_ICG_FUNC_ENA_LEDC0);
*clk_icg0_flags |= PMU_SLEEP_CLK_ICG_BIT(PMU_ICG_FUNC_ENA_LEDC0);
}
if (s_sleep_clock_icg_refs[ESP_SLEEP_CLOCK_UART0] > 0) {
icg_flags |= PMU_SLEEP_CLK_ICG_BIT(PMU_ICG_FUNC_ENA_UART0);
*clk_icg0_flags |= PMU_SLEEP_CLK_ICG_BIT(PMU_ICG_FUNC_ENA_UART0);
}
if (s_sleep_clock_icg_refs[ESP_SLEEP_CLOCK_UART1] > 0) {
icg_flags |= PMU_SLEEP_CLK_ICG_BIT(PMU_ICG_FUNC_ENA_UART1);
*clk_icg0_flags |= PMU_SLEEP_CLK_ICG_BIT(PMU_ICG_FUNC_ENA_UART1);
}
return icg_flags;
*clk_icg1_flags = 0;
}
esp_err_t esp_sleep_clock_config(esp_sleep_clock_t clock, esp_sleep_clock_option_t option)
components/esp_hw_support/lowpower/port/esp32c6/sleep_clock_icg.c
+7 -9
View File
@@ -23,21 +23,19 @@
static int16_t s_sleep_clock_icg_refs[ESP_SLEEP_CLOCK_MAX];
SLEEP_CLOCK_ICG_FN_ATTR uint32_t esp_sleep_clock_get_clk_icg_flags(void)
SLEEP_CLOCK_ICG_FN_ATTR void esp_sleep_clock_get_clk_icg_flags(uint32_t *clk_icg0_flags, uint32_t *clk_icg1_flags)
{
uint32_t icg_flags = 0;
if (s_sleep_clock_icg_refs[ESP_SLEEP_CLOCK_IOMUX] > 0) {
icg_flags |= PMU_SLEEP_CLK_ICG_BIT(PMU_ICG_FUNC_ENA_IOMUX);
*clk_icg0_flags |= PMU_SLEEP_CLK_ICG_BIT(PMU_ICG_FUNC_ENA_IOMUX);
}
if (s_sleep_clock_icg_refs[ESP_SLEEP_CLOCK_LEDC0] > 0) {
icg_flags |= PMU_SLEEP_CLK_ICG_BIT(PMU_ICG_FUNC_ENA_LEDC0);
*clk_icg0_flags |= PMU_SLEEP_CLK_ICG_BIT(PMU_ICG_FUNC_ENA_LEDC0);
}
if (s_sleep_clock_icg_refs[ESP_SLEEP_CLOCK_UART0] > 0) {
icg_flags |= PMU_SLEEP_CLK_ICG_BIT(PMU_ICG_FUNC_ENA_UART0);
*clk_icg0_flags |= PMU_SLEEP_CLK_ICG_BIT(PMU_ICG_FUNC_ENA_UART0);
}
if (s_sleep_clock_icg_refs[ESP_SLEEP_CLOCK_UART1] > 0) {
icg_flags |= PMU_SLEEP_CLK_ICG_BIT(PMU_ICG_FUNC_ENA_UART1);
*clk_icg0_flags |= PMU_SLEEP_CLK_ICG_BIT(PMU_ICG_FUNC_ENA_UART1);
}
#if SOC_BLE_USE_WIFI_PWR_CLK_WORKAROUND
/* Starting from C6ECO1 and later versions, when BLE RTC is configured to use
@@ -45,11 +43,11 @@ SLEEP_CLOCK_ICG_FN_ATTR uint32_t esp_sleep_clock_get_clk_icg_flags(void)
* As all 32 bits of ICG_FUNC are occupied, the ESP_SLEEP_CLOCK_BT_USE_WIFI_PWR_CLK
* has been remapped to PMU_ICG_FUNC_ENA_RETENTION.*/
if (s_sleep_clock_icg_refs[ESP_SLEEP_CLOCK_BT_USE_WIFI_PWR_CLK] > 0) {
icg_flags |= PMU_SLEEP_CLK_ICG_BIT(PMU_ICG_FUNC_ENA_RETENTION);
*clk_icg0_flags |= PMU_SLEEP_CLK_ICG_BIT(PMU_ICG_FUNC_ENA_RETENTION);
}
#endif
return icg_flags;
*clk_icg1_flags = 0;
}
esp_err_t esp_sleep_clock_config(esp_sleep_clock_t clock, esp_sleep_clock_option_t option)
components/esp_hw_support/lowpower/port/esp32c61/sleep_clock_icg.c
+7 -9
View File
@@ -23,29 +23,27 @@
static int16_t s_sleep_clock_icg_refs[ESP_SLEEP_CLOCK_MAX];
SLEEP_CLOCK_ICG_FN_ATTR uint32_t esp_sleep_clock_get_clk_icg_flags(void)
SLEEP_CLOCK_ICG_FN_ATTR void esp_sleep_clock_get_clk_icg_flags(uint32_t *clk_icg0_flags, uint32_t *clk_icg1_flags)
{
uint32_t icg_flags = 0;
if (s_sleep_clock_icg_refs[ESP_SLEEP_CLOCK_IOMUX] > 0) {
icg_flags |= PMU_SLEEP_CLK_ICG_BIT(PMU_ICG_FUNC_ENA_IOMUX);
*clk_icg0_flags |= PMU_SLEEP_CLK_ICG_BIT(PMU_ICG_FUNC_ENA_IOMUX);
}
if (s_sleep_clock_icg_refs[ESP_SLEEP_CLOCK_LEDC0] > 0) {
icg_flags |= PMU_SLEEP_CLK_ICG_BIT(PMU_ICG_FUNC_ENA_LEDC0);
*clk_icg0_flags |= PMU_SLEEP_CLK_ICG_BIT(PMU_ICG_FUNC_ENA_LEDC0);
}
if (s_sleep_clock_icg_refs[ESP_SLEEP_CLOCK_UART0] > 0) {
icg_flags |= PMU_SLEEP_CLK_ICG_BIT(PMU_ICG_FUNC_ENA_UART0);
*clk_icg0_flags |= PMU_SLEEP_CLK_ICG_BIT(PMU_ICG_FUNC_ENA_UART0);
}
if (s_sleep_clock_icg_refs[ESP_SLEEP_CLOCK_UART1] > 0) {
icg_flags |= PMU_SLEEP_CLK_ICG_BIT(PMU_ICG_FUNC_ENA_UART1);
*clk_icg0_flags |= PMU_SLEEP_CLK_ICG_BIT(PMU_ICG_FUNC_ENA_UART1);
}
#if SOC_UART_HP_NUM > 2
if (s_sleep_clock_icg_refs[ESP_SLEEP_CLOCK_UART2] > 0) {
icg_flags |= PMU_SLEEP_CLK_ICG_BIT(PMU_ICG_FUNC_ENA_UART2);
*clk_icg0_flags |= PMU_SLEEP_CLK_ICG_BIT(PMU_ICG_FUNC_ENA_UART2);
}
#endif
return icg_flags;
*clk_icg1_flags = 0;
}
esp_err_t esp_sleep_clock_config(esp_sleep_clock_t clock, esp_sleep_clock_option_t option)
components/esp_hw_support/lowpower/port/esp32h2/sleep_clock_icg.c
+6 -8
View File
@@ -23,24 +23,22 @@
static int16_t s_sleep_clock_icg_refs[ESP_SLEEP_CLOCK_MAX];
SLEEP_CLOCK_ICG_FN_ATTR uint32_t esp_sleep_clock_get_clk_icg_flags(void)
SLEEP_CLOCK_ICG_FN_ATTR void esp_sleep_clock_get_clk_icg_flags(uint32_t *clk_icg0_flags, uint32_t *clk_icg1_flags)
{
uint32_t icg_flags = 0;
if (s_sleep_clock_icg_refs[ESP_SLEEP_CLOCK_IOMUX] > 0) {
icg_flags |= PMU_SLEEP_CLK_ICG_BIT(PMU_ICG_FUNC_ENA_IOMUX);
*clk_icg0_flags |= PMU_SLEEP_CLK_ICG_BIT(PMU_ICG_FUNC_ENA_IOMUX);
}
if (s_sleep_clock_icg_refs[ESP_SLEEP_CLOCK_LEDC0] > 0) {
icg_flags |= PMU_SLEEP_CLK_ICG_BIT(PMU_ICG_FUNC_ENA_LEDC0);
*clk_icg0_flags |= PMU_SLEEP_CLK_ICG_BIT(PMU_ICG_FUNC_ENA_LEDC0);
}
if (s_sleep_clock_icg_refs[ESP_SLEEP_CLOCK_UART0] > 0) {
icg_flags |= PMU_SLEEP_CLK_ICG_BIT(PMU_ICG_FUNC_ENA_UART0);
*clk_icg0_flags |= PMU_SLEEP_CLK_ICG_BIT(PMU_ICG_FUNC_ENA_UART0);
}
if (s_sleep_clock_icg_refs[ESP_SLEEP_CLOCK_UART1] > 0) {
icg_flags |= PMU_SLEEP_CLK_ICG_BIT(PMU_ICG_FUNC_ENA_UART1);
*clk_icg0_flags |= PMU_SLEEP_CLK_ICG_BIT(PMU_ICG_FUNC_ENA_UART1);
}
return icg_flags;
*clk_icg1_flags = 0;
}
esp_err_t esp_sleep_clock_config(esp_sleep_clock_t clock, esp_sleep_clock_option_t option)
components/esp_hw_support/lowpower/port/esp32h21/sleep_clock_icg.c
+6 -8
View File
@@ -23,24 +23,22 @@
static int16_t s_sleep_clock_icg_refs[ESP_SLEEP_CLOCK_MAX];
SLEEP_CLOCK_ICG_FN_ATTR uint32_t esp_sleep_clock_get_clk_icg_flags(void)
SLEEP_CLOCK_ICG_FN_ATTR void esp_sleep_clock_get_clk_icg_flags(uint32_t *clk_icg0_flags, uint32_t *clk_icg1_flags)
{
uint32_t icg_flags = 0;
if (s_sleep_clock_icg_refs[ESP_SLEEP_CLOCK_IOMUX] > 0) {
icg_flags |= PMU_SLEEP_CLK_ICG_BIT(PMU_ICG_FUNC_ENA_IOMUX);
*clk_icg0_flags |= PMU_SLEEP_CLK_ICG_BIT(PMU_ICG_FUNC_ENA_IOMUX);
}
if (s_sleep_clock_icg_refs[ESP_SLEEP_CLOCK_LEDC0] > 0) {
icg_flags |= PMU_SLEEP_CLK_ICG_BIT(PMU_ICG_FUNC_ENA_LEDC0);
*clk_icg0_flags |= PMU_SLEEP_CLK_ICG_BIT(PMU_ICG_FUNC_ENA_LEDC0);
}
if (s_sleep_clock_icg_refs[ESP_SLEEP_CLOCK_UART0] > 0) {
icg_flags |= PMU_SLEEP_CLK_ICG_BIT(PMU_ICG_FUNC_ENA_UART0);
*clk_icg0_flags |= PMU_SLEEP_CLK_ICG_BIT(PMU_ICG_FUNC_ENA_UART0);
}
if (s_sleep_clock_icg_refs[ESP_SLEEP_CLOCK_UART1] > 0) {
icg_flags |= PMU_SLEEP_CLK_ICG_BIT(PMU_ICG_FUNC_ENA_UART1);
*clk_icg0_flags |= PMU_SLEEP_CLK_ICG_BIT(PMU_ICG_FUNC_ENA_UART1);
}
return icg_flags;
*clk_icg1_flags = 0;
}
esp_err_t esp_sleep_clock_config(esp_sleep_clock_t clock, esp_sleep_clock_option_t option)
components/esp_hw_support/lowpower/port/esp32h4/sleep_clock_icg.c
+6 -8
View File
@@ -23,24 +23,22 @@
static int16_t s_sleep_clock_icg_refs[ESP_SLEEP_CLOCK_MAX];
SLEEP_CLOCK_ICG_FN_ATTR uint32_t esp_sleep_clock_get_clk_icg_flags(void)
SLEEP_CLOCK_ICG_FN_ATTR void esp_sleep_clock_get_clk_icg_flags(uint32_t *clk_icg0_flags, uint32_t *clk_icg1_flags)
{
uint32_t icg_flags = 0;
if (s_sleep_clock_icg_refs[ESP_SLEEP_CLOCK_IOMUX] > 0) {
icg_flags |= PMU_SLEEP_CLK_ICG_BIT(PMU_ICG_FUNC_ENA_IOMUX);
*clk_icg0_flags |= PMU_SLEEP_CLK_ICG_BIT(PMU_ICG_FUNC_ENA_IOMUX);
}
if (s_sleep_clock_icg_refs[ESP_SLEEP_CLOCK_LEDC0] > 0) {
icg_flags |= PMU_SLEEP_CLK_ICG_BIT(PMU_ICG_FUNC_ENA_LEDC0);
*clk_icg0_flags |= PMU_SLEEP_CLK_ICG_BIT(PMU_ICG_FUNC_ENA_LEDC0);
}
if (s_sleep_clock_icg_refs[ESP_SLEEP_CLOCK_UART0] > 0) {
icg_flags |= PMU_SLEEP_CLK_ICG_BIT(PMU_ICG_FUNC_ENA_UART0);
*clk_icg0_flags |= PMU_SLEEP_CLK_ICG_BIT(PMU_ICG_FUNC_ENA_UART0);
}
if (s_sleep_clock_icg_refs[ESP_SLEEP_CLOCK_UART1] > 0) {
icg_flags |= PMU_SLEEP_CLK_ICG_BIT(PMU_ICG_FUNC_ENA_UART1);
*clk_icg0_flags |= PMU_SLEEP_CLK_ICG_BIT(PMU_ICG_FUNC_ENA_UART1);
}
return icg_flags;
*clk_icg1_flags = 0;
}
esp_err_t esp_sleep_clock_config(esp_sleep_clock_t clock, esp_sleep_clock_option_t option)
components/esp_hw_support/lowpower/port/esp32p4/sleep_clock_icg.c
+9 -11
View File
@@ -26,39 +26,37 @@ ESP_LOG_ATTR_TAG(TAG, "sleep_clock_icg");
static int16_t s_sleep_clock_icg_refs[ESP_SLEEP_CLOCK_MAX];
SLEEP_CLOCK_ICG_FN_ATTR uint32_t esp_sleep_clock_get_clk_icg_flags(void)
SLEEP_CLOCK_ICG_FN_ATTR void esp_sleep_clock_get_clk_icg_flags(uint32_t *clk_icg0_flags, uint32_t *clk_icg1_flags)
{
uint32_t icg_flags = 0;
if (s_sleep_clock_icg_refs[ESP_SLEEP_CLOCK_IOMUX] > 0) {
icg_flags |= PMU_SLEEP_CLK_ICG_BIT(PMU_ICG_FUNC_ENA_IOMUX);
*clk_icg0_flags |= PMU_SLEEP_CLK_ICG_BIT(PMU_ICG_FUNC_ENA_IOMUX);
}
if (s_sleep_clock_icg_refs[ESP_SLEEP_CLOCK_LEDC0] > 0) {
icg_flags |= PMU_SLEEP_CLK_ICG_BIT(PMU_ICG_FUNC_ENA_LEDC0);
*clk_icg0_flags |= PMU_SLEEP_CLK_ICG_BIT(PMU_ICG_FUNC_ENA_LEDC0);
}
if (s_sleep_clock_icg_refs[ESP_SLEEP_CLOCK_UART0] > 0) {
icg_flags |= PMU_SLEEP_CLK_ICG_BIT(PMU_ICG_FUNC_ENA_UART0);
*clk_icg0_flags |= PMU_SLEEP_CLK_ICG_BIT(PMU_ICG_FUNC_ENA_UART0);
}
if (s_sleep_clock_icg_refs[ESP_SLEEP_CLOCK_UART1] > 0) {
icg_flags |= PMU_SLEEP_CLK_ICG_BIT(PMU_ICG_FUNC_ENA_UART1);
*clk_icg0_flags |= PMU_SLEEP_CLK_ICG_BIT(PMU_ICG_FUNC_ENA_UART1);
}
#if SOC_UART_HP_NUM > 2
if (s_sleep_clock_icg_refs[ESP_SLEEP_CLOCK_UART2] > 0) {
icg_flags |= PMU_SLEEP_CLK_ICG_BIT(PMU_ICG_FUNC_ENA_UART2);
*clk_icg0_flags |= PMU_SLEEP_CLK_ICG_BIT(PMU_ICG_FUNC_ENA_UART2);
}
#endif
#if SOC_UART_HP_NUM > 3
if (s_sleep_clock_icg_refs[ESP_SLEEP_CLOCK_UART3] > 0) {
icg_flags |= PMU_SLEEP_CLK_ICG_BIT(PMU_ICG_FUNC_ENA_UART3);
*clk_icg0_flags |= PMU_SLEEP_CLK_ICG_BIT(PMU_ICG_FUNC_ENA_UART3);
}
#endif
#if SOC_UART_HP_NUM > 4
if (s_sleep_clock_icg_refs[ESP_SLEEP_CLOCK_UART4] > 0) {
icg_flags |= PMU_SLEEP_CLK_ICG_BIT(PMU_ICG_FUNC_ENA_UART4);
*clk_icg0_flags |= PMU_SLEEP_CLK_ICG_BIT(PMU_ICG_FUNC_ENA_UART4);
}
#endif
return icg_flags;
*clk_icg1_flags = 0;
}
esp_err_t esp_sleep_clock_config(esp_sleep_clock_t clock, esp_sleep_clock_option_t option)
components/esp_hw_support/lowpower/port/esp32s31/sleep_clock_icg.c
+13 -10
View File
@@ -23,34 +23,37 @@
static int16_t s_sleep_clock_icg_refs[ESP_SLEEP_CLOCK_MAX];
SLEEP_CLOCK_ICG_FN_ATTR uint64_t esp_sleep_clock_get_clk_icg_flags(void)
SLEEP_CLOCK_ICG_FN_ATTR void esp_sleep_clock_get_clk_icg_flags(uint32_t *clk_icg0_flags, uint32_t *clk_icg1_flags)
{
uint64_t icg_flags = 0;
if (s_sleep_clock_icg_refs[ESP_SLEEP_CLOCK_IOMUX] > 0) {
icg_flags |= PMU_SLEEP_CLK_ICG_BIT(PMU_ICG_FUNC_ENA_IOMUX);
*clk_icg0_flags |= PMU_SLEEP_CLK_ICG_FUNC_LO(PMU_SLEEP_CLK_ICG_BIT(PMU_ICG_FUNC_ENA_IOMUX));
*clk_icg1_flags |= PMU_SLEEP_CLK_ICG_FUNC_HI(PMU_SLEEP_CLK_ICG_BIT(PMU_ICG_FUNC_ENA_IOMUX));
}
if (s_sleep_clock_icg_refs[ESP_SLEEP_CLOCK_LEDC0] > 0) {
icg_flags |= PMU_SLEEP_CLK_ICG_BIT(PMU_ICG_FUNC_ENA_LEDC0);
*clk_icg0_flags |= PMU_SLEEP_CLK_ICG_FUNC_LO(PMU_SLEEP_CLK_ICG_BIT(PMU_ICG_FUNC_ENA_LEDC0));
*clk_icg1_flags |= PMU_SLEEP_CLK_ICG_FUNC_HI(PMU_SLEEP_CLK_ICG_BIT(PMU_ICG_FUNC_ENA_LEDC0));
}
if (s_sleep_clock_icg_refs[ESP_SLEEP_CLOCK_UART0] > 0) {
icg_flags |= PMU_SLEEP_CLK_ICG_BIT(PMU_ICG_FUNC_ENA_UART0);
*clk_icg0_flags |= PMU_SLEEP_CLK_ICG_FUNC_LO(PMU_SLEEP_CLK_ICG_BIT(PMU_ICG_FUNC_ENA_UART0));
*clk_icg1_flags |= PMU_SLEEP_CLK_ICG_FUNC_HI(PMU_SLEEP_CLK_ICG_BIT(PMU_ICG_FUNC_ENA_UART0));
}
if (s_sleep_clock_icg_refs[ESP_SLEEP_CLOCK_UART1] > 0) {
icg_flags |= PMU_SLEEP_CLK_ICG_BIT(PMU_ICG_FUNC_ENA_UART1);
*clk_icg0_flags |= PMU_SLEEP_CLK_ICG_FUNC_LO(PMU_SLEEP_CLK_ICG_BIT(PMU_ICG_FUNC_ENA_UART1));
*clk_icg1_flags |= PMU_SLEEP_CLK_ICG_FUNC_HI(PMU_SLEEP_CLK_ICG_BIT(PMU_ICG_FUNC_ENA_UART1));
}
#if SOC_UART_HP_NUM > 2
if (s_sleep_clock_icg_refs[ESP_SLEEP_CLOCK_UART2] > 0) {
icg_flags |= PMU_SLEEP_CLK_ICG_BIT(PMU_ICG_FUNC_ENA_UART2);
*clk_icg0_flags |= PMU_SLEEP_CLK_ICG_FUNC_LO(PMU_SLEEP_CLK_ICG_BIT(PMU_ICG_FUNC_ENA_UART2));
*clk_icg1_flags |= PMU_SLEEP_CLK_ICG_FUNC_HI(PMU_SLEEP_CLK_ICG_BIT(PMU_ICG_FUNC_ENA_UART2));
}
#endif
#if SOC_UART_HP_NUM > 3
if (s_sleep_clock_icg_refs[ESP_SLEEP_CLOCK_UART3] > 0) {
icg_flags |= PMU_SLEEP_CLK_ICG_BIT(PMU_ICG_FUNC_ENA_UART3);
*clk_icg0_flags |= PMU_SLEEP_CLK_ICG_FUNC_LO(PMU_SLEEP_CLK_ICG_BIT(PMU_ICG_FUNC_ENA_UART3));
*clk_icg1_flags |= PMU_SLEEP_CLK_ICG_FUNC_HI(PMU_SLEEP_CLK_ICG_BIT(PMU_ICG_FUNC_ENA_UART3));
}
#endif
return icg_flags;
}
esp_err_t esp_sleep_clock_config(esp_sleep_clock_t clock, esp_sleep_clock_option_t option)
components/esp_hw_support/port/esp32c5/pmu_sleep.c
+12 -19
View File
@@ -188,14 +188,15 @@ uint32_t pmu_sleep_calculate_hw_wait_time(uint32_t sleep_flags, soc_rtc_slow_clk
static inline pmu_sleep_param_config_t * pmu_sleep_param_config_default(
pmu_sleep_param_config_t *param,
pmu_sleep_power_config_t *power, /* We'll use the runtime power parameter to determine some hardware parameters */
const uint32_t sleep_flags,
const uint32_t adjustment,
soc_rtc_slow_clk_src_t slowclk_src,
const uint32_t slowclk_period,
const uint32_t fastclk_period
pmu_sleep_extra_args_t *args
)
{
const pmu_sleep_machine_constant_t *mc = (pmu_sleep_machine_constant_t *)PMU_instance()->mc;
const uint32_t sleep_flags = args->sleep_flags;
const uint32_t adjustment = args->adjustment;
const soc_rtc_slow_clk_src_t slowclk_src = args->slowclk_src;
const uint32_t slowclk_period = args->slowclk_period;
const uint32_t fastclk_period = args->fastclk_period;
#if (SOC_PM_PMU_MIN_SLP_SLOW_CLK_CYCLE_FIXED && SOC_PM_SUPPORT_PMU_MODEM_STATE && CONFIG_ESP_WIFI_ENHANCED_LIGHT_SLEEP)
const uint32_t slowclk_period_fixed = (slowclk_src == SOC_RTC_SLOW_CLK_SRC_RC_SLOW) ? rtc_clk_freq_to_period(SOC_CLK_RC_SLOW_FREQ_APPROX) : slowclk_period;
@@ -231,23 +232,15 @@ static inline pmu_sleep_param_config_t * pmu_sleep_param_config_default(
return param;
}
const pmu_sleep_config_t* pmu_sleep_config_default(
pmu_sleep_config_t *config,
uint32_t sleep_flags,
pmu_sleep_clk_icg_flags_t clk_flags,
uint32_t adjustment,
soc_rtc_slow_clk_src_t slowclk_src,
uint32_t slowclk_period,
uint32_t fastclk_period,
bool dslp
)
const pmu_sleep_config_t* pmu_sleep_config_default(pmu_sleep_config_t *config, pmu_sleep_extra_args_t *args, bool dslp)
{
const uint32_t sleep_flags = args->sleep_flags;
pmu_sleep_power_config_t power_default = PMU_SLEEP_POWER_CONFIG_DEFAULT(sleep_flags);
if (dslp) {
config->param.lp_sys.analog_wait_target_cycle = rtc_time_us_to_slowclk(PMU_LP_ANALOG_WAIT_TARGET_TIME_DSLP_US, slowclk_period);
config->param.lp_sys.analog_wait_target_cycle = rtc_time_us_to_slowclk(PMU_LP_ANALOG_WAIT_TARGET_TIME_DSLP_US, args->slowclk_period);
pmu_sleep_digital_config_t digital_default = PMU_SLEEP_DIGITAL_DSLP_CONFIG_DEFAULT(sleep_flags, clk_flags);
pmu_sleep_digital_config_t digital_default = PMU_SLEEP_DIGITAL_DSLP_CONFIG_DEFAULT(sleep_flags, args->clk_flags);
config->digital = digital_default;
@@ -257,7 +250,7 @@ const pmu_sleep_config_t* pmu_sleep_config_default(
config->analog = analog_default;
} else {
pmu_sleep_digital_config_t digital_default = PMU_SLEEP_DIGITAL_LSLP_CONFIG_DEFAULT(sleep_flags, clk_flags);
pmu_sleep_digital_config_t digital_default = PMU_SLEEP_DIGITAL_LSLP_CONFIG_DEFAULT(sleep_flags, args->clk_flags);
config->digital = digital_default;
pmu_sleep_analog_config_t analog_default = PMU_SLEEP_ANALOG_LSLP_CONFIG_DEFAULT(sleep_flags);
@@ -297,7 +290,7 @@ const pmu_sleep_config_t* pmu_sleep_config_default(
config->power = power_default;
pmu_sleep_param_config_t param_default = PMU_SLEEP_PARAM_CONFIG_DEFAULT(sleep_flags);
config->param = *pmu_sleep_param_config_default(&param_default, &power_default, sleep_flags, adjustment, slowclk_src, slowclk_period, fastclk_period);
config->param = *pmu_sleep_param_config_default(&param_default, &power_default, args);
return config;
}
components/esp_hw_support/port/esp32c5/private_include/pmu_param.h
+1 -1
View File
@@ -332,7 +332,7 @@ typedef struct {
.dig_pad_slp_sel = ((sleep_flags) & PMU_SLEEP_PD_TOP) ? 0 : 1, \
.dig_pause_wdt = ((sleep_flags) & RTC_SLEEP_USE_RTC_WDT) ? 0 : 1, \
}, \
.icg_func = (uint32_t)(clk_flags) \
.icg_func = (clk_flags)[0] \
}
#define PMU_SLEEP_DIGITAL_DSLP_CONFIG_DEFAULT(sleep_flags, clk_flags) { \
components/esp_hw_support/port/esp32c6/pmu_sleep.c
+13 -20
View File
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -176,14 +176,15 @@ uint32_t pmu_sleep_calculate_hw_wait_time(uint32_t sleep_flags, soc_rtc_slow_clk
static inline pmu_sleep_param_config_t * pmu_sleep_param_config_default(
pmu_sleep_param_config_t *param,
pmu_sleep_power_config_t *power, /* We'll use the runtime power parameter to determine some hardware parameters */
const uint32_t sleep_flags,
const uint32_t adjustment,
soc_rtc_slow_clk_src_t slowclk_src,
const uint32_t slowclk_period,
const uint32_t fastclk_period
pmu_sleep_extra_args_t *args
)
{
const pmu_sleep_machine_constant_t *mc = (pmu_sleep_machine_constant_t *)PMU_instance()->mc;
const uint32_t sleep_flags = args->sleep_flags;
const uint32_t adjustment = args->adjustment;
const soc_rtc_slow_clk_src_t slowclk_src = args->slowclk_src;
const uint32_t slowclk_period = args->slowclk_period;
const uint32_t fastclk_period = args->fastclk_period;
#if (SOC_PM_PMU_MIN_SLP_SLOW_CLK_CYCLE_FIXED && SOC_PM_SUPPORT_PMU_MODEM_STATE && CONFIG_ESP_WIFI_ENHANCED_LIGHT_SLEEP)
const uint32_t slowclk_period_fixed = (slowclk_src == SOC_RTC_SLOW_CLK_SRC_RC_SLOW) ? rtc_clk_freq_to_period(SOC_CLK_RC_SLOW_FREQ_APPROX) : slowclk_period;
@@ -215,27 +216,19 @@ static inline pmu_sleep_param_config_t * pmu_sleep_param_config_default(
return param;
}
const pmu_sleep_config_t* pmu_sleep_config_default(
pmu_sleep_config_t *config,
uint32_t sleep_flags,
pmu_sleep_clk_icg_flags_t clk_flags,
uint32_t adjustment,
soc_rtc_slow_clk_src_t slowclk_src,
uint32_t slowclk_period,
uint32_t fastclk_period,
bool dslp
)
const pmu_sleep_config_t* pmu_sleep_config_default(pmu_sleep_config_t *config, pmu_sleep_extra_args_t *args, bool dslp)
{
const uint32_t sleep_flags = args->sleep_flags;
pmu_sleep_power_config_t power_default = PMU_SLEEP_POWER_CONFIG_DEFAULT(sleep_flags);
config->power = power_default;
pmu_sleep_param_config_t param_default = PMU_SLEEP_PARAM_CONFIG_DEFAULT(sleep_flags);
config->param = *pmu_sleep_param_config_default(&param_default, &power_default, sleep_flags, adjustment, slowclk_src, slowclk_period, fastclk_period);
config->param = *pmu_sleep_param_config_default(&param_default, &power_default, args);
if (dslp) {
config->param.lp_sys.analog_wait_target_cycle = rtc_time_us_to_slowclk(PMU_LP_ANALOG_WAIT_TARGET_TIME_DSLP_US, slowclk_period);
config->param.lp_sys.analog_wait_target_cycle = rtc_time_us_to_slowclk(PMU_LP_ANALOG_WAIT_TARGET_TIME_DSLP_US, args->slowclk_period);
pmu_sleep_digital_config_t digital_default = PMU_SLEEP_DIGITAL_DSLP_CONFIG_DEFAULT(sleep_flags, clk_flags);
pmu_sleep_digital_config_t digital_default = PMU_SLEEP_DIGITAL_DSLP_CONFIG_DEFAULT(sleep_flags, args->clk_flags);
config->digital = digital_default;
pmu_sleep_analog_config_t analog_default = PMU_SLEEP_ANALOG_DSLP_CONFIG_DEFAULT(sleep_flags);
@@ -244,7 +237,7 @@ const pmu_sleep_config_t* pmu_sleep_config_default(
config->analog = analog_default;
} else {
pmu_sleep_digital_config_t digital_default = PMU_SLEEP_DIGITAL_LSLP_CONFIG_DEFAULT(sleep_flags, clk_flags);
pmu_sleep_digital_config_t digital_default = PMU_SLEEP_DIGITAL_LSLP_CONFIG_DEFAULT(sleep_flags, args->clk_flags);
config->digital = digital_default;
pmu_sleep_analog_config_t analog_default = PMU_SLEEP_ANALOG_LSLP_CONFIG_DEFAULT(sleep_flags);
components/esp_hw_support/port/esp32c6/private_include/pmu_param.h
+1 -1
View File
@@ -328,7 +328,7 @@ typedef struct {
.dig_pad_slp_sel = ((sleep_flags) & PMU_SLEEP_PD_TOP) ? 0 : 1, \
.dig_pause_wdt = ((sleep_flags) & RTC_SLEEP_USE_RTC_WDT) ? 0 : 1, \
}, \
.icg_func = (uint32_t)(clk_flags) \
.icg_func = (clk_flags)[0] \
}
#define PMU_SLEEP_DIGITAL_DSLP_CONFIG_DEFAULT(sleep_flags, clk_flags) { \
components/esp_hw_support/port/esp32c61/pmu_sleep.c
+12 -19
View File
@@ -182,14 +182,15 @@ uint32_t pmu_sleep_calculate_hw_wait_time(uint32_t sleep_flags, soc_rtc_slow_clk
static inline pmu_sleep_param_config_t * pmu_sleep_param_config_default(
pmu_sleep_param_config_t *param,
pmu_sleep_power_config_t *power, /* We'll use the runtime power parameter to determine some hardware parameters */
const uint32_t sleep_flags,
const uint32_t adjustment,
soc_rtc_slow_clk_src_t slowclk_src,
const uint32_t slowclk_period,
const uint32_t fastclk_period
pmu_sleep_extra_args_t *args
)
{
const pmu_sleep_machine_constant_t *mc = (pmu_sleep_machine_constant_t *)PMU_instance()->mc;
const uint32_t sleep_flags = args->sleep_flags;
const uint32_t adjustment = args->adjustment;
const soc_rtc_slow_clk_src_t slowclk_src = args->slowclk_src;
const uint32_t slowclk_period = args->slowclk_period;
const uint32_t fastclk_period = args->fastclk_period;
#if (SOC_PM_PMU_MIN_SLP_SLOW_CLK_CYCLE_FIXED && SOC_PM_SUPPORT_PMU_MODEM_STATE && CONFIG_ESP_WIFI_ENHANCED_LIGHT_SLEEP)
const uint32_t slowclk_period_fixed = (slowclk_src == SOC_RTC_SLOW_CLK_SRC_RC_SLOW) ? rtc_clk_freq_to_period(SOC_CLK_RC_SLOW_FREQ_APPROX) : slowclk_period;
@@ -225,27 +226,19 @@ static inline pmu_sleep_param_config_t * pmu_sleep_param_config_default(
return param;
}
const pmu_sleep_config_t* pmu_sleep_config_default(
pmu_sleep_config_t *config,
uint32_t sleep_flags,
pmu_sleep_clk_icg_flags_t clk_flags,
uint32_t adjustment,
soc_rtc_slow_clk_src_t slowclk_src,
uint32_t slowclk_period,
uint32_t fastclk_period,
bool dslp
)
const pmu_sleep_config_t* pmu_sleep_config_default(pmu_sleep_config_t *config, pmu_sleep_extra_args_t *args, bool dslp)
{
const uint32_t sleep_flags = args->sleep_flags;
pmu_sleep_power_config_t power_default = PMU_SLEEP_POWER_CONFIG_DEFAULT(sleep_flags);
config->power = power_default;
pmu_sleep_param_config_t param_default = PMU_SLEEP_PARAM_CONFIG_DEFAULT(sleep_flags);
config->param = *pmu_sleep_param_config_default(&param_default, &power_default, sleep_flags, adjustment, slowclk_src, slowclk_period, fastclk_period);
config->param = *pmu_sleep_param_config_default(&param_default, &power_default, args);
if (dslp) {
config->param.lp_sys.analog_wait_target_cycle = rtc_time_us_to_slowclk(PMU_LP_ANALOG_WAIT_TARGET_TIME_DSLP_US, slowclk_period);
config->param.lp_sys.analog_wait_target_cycle = rtc_time_us_to_slowclk(PMU_LP_ANALOG_WAIT_TARGET_TIME_DSLP_US, args->slowclk_period);
pmu_sleep_digital_config_t digital_default = PMU_SLEEP_DIGITAL_DSLP_CONFIG_DEFAULT(sleep_flags, clk_flags);
pmu_sleep_digital_config_t digital_default = PMU_SLEEP_DIGITAL_DSLP_CONFIG_DEFAULT(sleep_flags, args->clk_flags);
config->digital = digital_default;
pmu_sleep_analog_config_t analog_default = PMU_SLEEP_ANALOG_DSLP_CONFIG_DEFAULT(sleep_flags);
@@ -253,7 +246,7 @@ const pmu_sleep_config_t* pmu_sleep_config_default(
analog_default.lp_sys[LP(SLEEP)].analog.dbias = get_dslp_lp_dbias();
config->analog = analog_default;
} else {
pmu_sleep_digital_config_t digital_default = PMU_SLEEP_DIGITAL_LSLP_CONFIG_DEFAULT(sleep_flags, clk_flags);
pmu_sleep_digital_config_t digital_default = PMU_SLEEP_DIGITAL_LSLP_CONFIG_DEFAULT(sleep_flags, args->clk_flags);
config->digital = digital_default;
pmu_sleep_analog_config_t analog_default = PMU_SLEEP_ANALOG_LSLP_CONFIG_DEFAULT(sleep_flags);
components/esp_hw_support/port/esp32c61/private_include/pmu_param.h
+1 -1
View File
@@ -328,7 +328,7 @@ typedef struct {
.dig_pad_slp_sel = ((sleep_flags) & PMU_SLEEP_PD_TOP) ? 0 : 1, \
.dig_pause_wdt = ((sleep_flags) & RTC_SLEEP_USE_RTC_WDT) ? 0 : 1, \
}, \
.icg_func = (uint32_t)(clk_flags) \
.icg_func = (clk_flags)[0] \
}
#define PMU_SLEEP_DIGITAL_DSLP_CONFIG_DEFAULT(sleep_flags, clk_flags) { \
components/esp_hw_support/port/esp32h2/pmu_sleep.c
+9 -18
View File
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -101,13 +101,12 @@ uint32_t pmu_sleep_calculate_hw_wait_time(uint32_t sleep_flags, soc_rtc_slow_clk
static inline pmu_sleep_param_config_t * pmu_sleep_param_config_default(
pmu_sleep_param_config_t *param,
pmu_sleep_power_config_t *power, /* We'll use the runtime power parameter to determine some hardware parameters */
const uint32_t sleep_flags,
const uint32_t adjustment,
const uint32_t slowclk_period,
const uint32_t fastclk_period
pmu_sleep_extra_args_t *args
)
{
const pmu_sleep_machine_constant_t *mc = (pmu_sleep_machine_constant_t *)PMU_instance()->mc;
const uint32_t slowclk_period = args->slowclk_period;
const uint32_t fastclk_period = args->fastclk_period;
param->hp_sys.min_slp_slow_clk_cycle = rtc_time_us_to_slowclk(mc->hp.min_slp_time_us, slowclk_period);
param->hp_sys.analog_wait_target_cycle = rtc_time_us_to_fastclk(mc->hp.analog_wait_time_us, fastclk_period);
@@ -128,20 +127,12 @@ static inline pmu_sleep_param_config_t * pmu_sleep_param_config_default(
return param;
}
const pmu_sleep_config_t* pmu_sleep_config_default(
pmu_sleep_config_t *config,
uint32_t sleep_flags,
pmu_sleep_clk_icg_flags_t clk_flags,
uint32_t adjustment,
soc_rtc_slow_clk_src_t slowclk_src,
uint32_t slowclk_period,
uint32_t fastclk_period,
bool dslp
)
const pmu_sleep_config_t* pmu_sleep_config_default(pmu_sleep_config_t *config, pmu_sleep_extra_args_t *args, bool dslp)
{
const uint32_t sleep_flags = args->sleep_flags;
pmu_sleep_power_config_t power_default = PMU_SLEEP_POWER_CONFIG_DEFAULT(sleep_flags);
if (dslp) {
pmu_sleep_digital_config_t digital_default = PMU_SLEEP_DIGITAL_DSLP_CONFIG_DEFAULT(sleep_flags, clk_flags);
pmu_sleep_digital_config_t digital_default = PMU_SLEEP_DIGITAL_DSLP_CONFIG_DEFAULT(sleep_flags, args->clk_flags);
config->digital = digital_default;
pmu_sleep_analog_config_t analog_default = PMU_SLEEP_ANALOG_DSLP_CONFIG_DEFAULT(sleep_flags);
@@ -153,7 +144,7 @@ const pmu_sleep_config_t* pmu_sleep_config_default(
power_default.lp_sys[PMU_MODE_LP_SLEEP].dig_power.bod_source_sel = 1;
}
} else {
pmu_sleep_digital_config_t digital_default = PMU_SLEEP_DIGITAL_LSLP_CONFIG_DEFAULT(sleep_flags, clk_flags);
pmu_sleep_digital_config_t digital_default = PMU_SLEEP_DIGITAL_LSLP_CONFIG_DEFAULT(sleep_flags, args->clk_flags);
config->digital = digital_default;
pmu_sleep_analog_config_t analog_default = PMU_SLEEP_ANALOG_LSLP_CONFIG_DEFAULT(sleep_flags);
@@ -176,7 +167,7 @@ const pmu_sleep_config_t* pmu_sleep_config_default(
}
config->power = power_default;
pmu_sleep_param_config_t param_default = PMU_SLEEP_PARAM_CONFIG_DEFAULT(sleep_flags);
config->param = *pmu_sleep_param_config_default(&param_default, &power_default, sleep_flags, adjustment, slowclk_period, fastclk_period);
config->param = *pmu_sleep_param_config_default(&param_default, &power_default, args);
return config;
}
components/esp_hw_support/port/esp32h2/private_include/pmu_param.h
+1 -1
View File
@@ -320,7 +320,7 @@ typedef struct {
.dig_pad_slp_sel = ((sleep_flags) & PMU_SLEEP_PD_TOP) ? 0 : 1, \
.dig_pause_wdt = ((sleep_flags) & RTC_SLEEP_USE_RTC_WDT) ? 0 : 1, \
}, \
.icg_func = (uint32_t)(clk_flags) \
.icg_func = (clk_flags)[0] \
}
#define PMU_SLEEP_DIGITAL_DSLP_CONFIG_DEFAULT(sleep_flags, clk_flags) { \
components/esp_hw_support/port/esp32h21/pmu_sleep.c
+8 -17
View File
@@ -110,13 +110,12 @@ uint32_t pmu_sleep_calculate_hw_wait_time(uint32_t sleep_flags, soc_rtc_slow_clk
static inline pmu_sleep_param_config_t * pmu_sleep_param_config_default(
pmu_sleep_param_config_t *param,
pmu_sleep_power_config_t *power, /* We'll use the runtime power parameter to determine some hardware parameters */
const uint32_t sleep_flags,
const uint32_t adjustment,
const uint32_t slowclk_period,
const uint32_t fastclk_period
pmu_sleep_extra_args_t *args
)
{
const pmu_sleep_machine_constant_t *mc = (pmu_sleep_machine_constant_t *)PMU_instance()->mc;
const uint32_t slowclk_period = args->slowclk_period;
const uint32_t fastclk_period = args->fastclk_period;
param->hp_sys.min_slp_slow_clk_cycle = rtc_time_us_to_slowclk(mc->hp.min_slp_time_us, slowclk_period);
param->hp_sys.analog_wait_target_cycle = rtc_time_us_to_fastclk(mc->hp.analog_wait_time_us, fastclk_period);
@@ -141,32 +140,24 @@ static inline pmu_sleep_param_config_t * pmu_sleep_param_config_default(
return param;
}
const pmu_sleep_config_t* pmu_sleep_config_default(
pmu_sleep_config_t *config,
uint32_t sleep_flags,
pmu_sleep_clk_icg_flags_t clk_flags,
uint32_t adjustment,
soc_rtc_slow_clk_src_t slowclk_src,
uint32_t slowclk_period,
uint32_t fastclk_period,
bool dslp
)
const pmu_sleep_config_t* pmu_sleep_config_default(pmu_sleep_config_t *config, pmu_sleep_extra_args_t *args, bool dslp)
{
const uint32_t sleep_flags = args->sleep_flags;
pmu_sleep_power_config_t power_default = PMU_SLEEP_POWER_CONFIG_DEFAULT(sleep_flags);
config->power = power_default;
pmu_sleep_param_config_t param_default = PMU_SLEEP_PARAM_CONFIG_DEFAULT(sleep_flags);
config->param = *pmu_sleep_param_config_default(&param_default, &power_default, sleep_flags, adjustment, slowclk_period, fastclk_period);
config->param = *pmu_sleep_param_config_default(&param_default, &power_default, args);
if (dslp) {
pmu_sleep_digital_config_t digital_default = PMU_SLEEP_DIGITAL_DSLP_CONFIG_DEFAULT(sleep_flags, clk_flags);
pmu_sleep_digital_config_t digital_default = PMU_SLEEP_DIGITAL_DSLP_CONFIG_DEFAULT(sleep_flags, args->clk_flags);
config->digital = digital_default;
pmu_sleep_analog_config_t analog_default = PMU_SLEEP_ANALOG_DSLP_CONFIG_DEFAULT(sleep_flags);
analog_default.lp_sys[LP(SLEEP)].analog.dbias = get_slp_lp_dbias();
config->analog = analog_default;
} else {
pmu_sleep_digital_config_t digital_default = PMU_SLEEP_DIGITAL_LSLP_CONFIG_DEFAULT(sleep_flags, clk_flags);
pmu_sleep_digital_config_t digital_default = PMU_SLEEP_DIGITAL_LSLP_CONFIG_DEFAULT(sleep_flags, args->clk_flags);
config->digital = digital_default;
pmu_sleep_analog_config_t analog_default = PMU_SLEEP_ANALOG_LSLP_CONFIG_DEFAULT(sleep_flags);
components/esp_hw_support/port/esp32h21/private_include/pmu_param.h
+1 -1
View File
@@ -356,7 +356,7 @@ typedef struct {
.dig_pad_slp_sel = ((sleep_flags) & PMU_SLEEP_PD_TOP) ? 0 : 1, \
.dig_pause_wdt = ((sleep_flags) & RTC_SLEEP_USE_RTC_WDT) ? 0 : 1, \
}, \
.icg_func = (uint32_t)(clk_flags) \
.icg_func = (clk_flags)[0] \
}
#define PMU_SLEEP_DIGITAL_DSLP_CONFIG_DEFAULT(sleep_flags, clk_flags) { \
components/esp_hw_support/port/esp32h4/pmu_sleep.c
+9 -18
View File
@@ -95,13 +95,12 @@ uint32_t pmu_sleep_calculate_hw_wait_time(uint32_t sleep_flags, soc_rtc_slow_clk
static inline pmu_sleep_param_config_t * pmu_sleep_param_config_default(
pmu_sleep_param_config_t *param,
pmu_sleep_power_config_t *power, /* We'll use the runtime power parameter to determine some hardware parameters */
const uint32_t sleep_flags,
const uint32_t adjustment,
const uint32_t slowclk_period,
const uint32_t fastclk_period
pmu_sleep_extra_args_t *args
)
{
const pmu_sleep_machine_constant_t *mc = (pmu_sleep_machine_constant_t *)PMU_instance()->mc;
const uint32_t slowclk_period = args->slowclk_period;
const uint32_t fastclk_period = args->fastclk_period;
param->hp_sys.min_slp_slow_clk_cycle = rtc_time_us_to_slowclk(mc->hp.min_slp_time_us, slowclk_period);
param->hp_sys.analog_wait_target_cycle = rtc_time_us_to_fastclk(mc->hp.analog_wait_time_us, fastclk_period);
@@ -126,34 +125,26 @@ static inline pmu_sleep_param_config_t * pmu_sleep_param_config_default(
return param;
}
const pmu_sleep_config_t* pmu_sleep_config_default(
pmu_sleep_config_t *config,
uint32_t sleep_flags,
pmu_sleep_clk_icg_flags_t clk_flags,
uint32_t adjustment,
soc_rtc_slow_clk_src_t slowclk_src,
uint32_t slowclk_period,
uint32_t fastclk_period,
bool dslp
)
const pmu_sleep_config_t* pmu_sleep_config_default(pmu_sleep_config_t *config, pmu_sleep_extra_args_t *args, bool dslp)
{
const uint32_t sleep_flags = args->sleep_flags;
pmu_sleep_power_config_t power_default = PMU_SLEEP_POWER_CONFIG_DEFAULT(sleep_flags);
config->power = power_default;
pmu_sleep_param_config_t param_default = PMU_SLEEP_PARAM_CONFIG_DEFAULT(sleep_flags);
config->param = *pmu_sleep_param_config_default(&param_default, &power_default, sleep_flags, adjustment, slowclk_period, fastclk_period);
config->param = *pmu_sleep_param_config_default(&param_default, &power_default, args);
if (dslp) {
config->param.lp_sys.analog_wait_target_cycle = rtc_time_us_to_slowclk(PMU_LP_ANALOG_WAIT_TARGET_TIME_DSLP_US, slowclk_period);
config->param.lp_sys.analog_wait_target_cycle = rtc_time_us_to_slowclk(PMU_LP_ANALOG_WAIT_TARGET_TIME_DSLP_US, args->slowclk_period);
pmu_sleep_digital_config_t digital_default = PMU_SLEEP_DIGITAL_DSLP_CONFIG_DEFAULT(sleep_flags, clk_flags);
pmu_sleep_digital_config_t digital_default = PMU_SLEEP_DIGITAL_DSLP_CONFIG_DEFAULT(sleep_flags, args->clk_flags);
config->digital = digital_default;
pmu_sleep_analog_config_t analog_default = PMU_SLEEP_ANALOG_DSLP_CONFIG_DEFAULT(sleep_flags);
config->analog = analog_default;
} else {
pmu_sleep_digital_config_t digital_default = PMU_SLEEP_DIGITAL_LSLP_CONFIG_DEFAULT(sleep_flags, clk_flags);
pmu_sleep_digital_config_t digital_default = PMU_SLEEP_DIGITAL_LSLP_CONFIG_DEFAULT(sleep_flags, args->clk_flags);
config->digital = digital_default;
pmu_sleep_analog_config_t analog_default = PMU_SLEEP_ANALOG_LSLP_CONFIG_DEFAULT(sleep_flags);
components/esp_hw_support/port/esp32h4/private_include/pmu_param.h
+1 -1
View File
@@ -369,7 +369,7 @@ typedef struct {
.dig_pad_slp_sel = ((sleep_flags) & PMU_SLEEP_PD_TOP) ? 0 : 1, \
.dig_pause_wdt = ((sleep_flags) & RTC_SLEEP_USE_RTC_WDT) ? 0 : 1, \
}, \
.icg_func = (uint32_t)(clk_flags) \
.icg_func = (clk_flags)[0] \
}
#define PMU_SLEEP_DIGITAL_DSLP_CONFIG_DEFAULT(sleep_flags, clk_flags) { \
components/esp_hw_support/port/esp32p4/pmu_sleep.c
+9 -19
View File
@@ -129,14 +129,12 @@ uint32_t pmu_sleep_calculate_hw_wait_time(uint32_t sleep_flags, soc_rtc_slow_clk
static inline pmu_sleep_param_config_t * pmu_sleep_param_config_default(
pmu_sleep_param_config_t *param,
pmu_sleep_power_config_t *power, /* We'll use the runtime power parameter to determine some hardware parameters */
const uint32_t sleep_flags,
const uint32_t adjustment,
soc_rtc_slow_clk_src_t slowclk_src,
const uint32_t slowclk_period,
const uint32_t fastclk_period
pmu_sleep_extra_args_t *args
)
{
const pmu_sleep_machine_constant_t *mc = (pmu_sleep_machine_constant_t *)PMU_instance()->mc;
const uint32_t slowclk_period = args->slowclk_period;
const uint32_t fastclk_period = args->fastclk_period;
param->hp_sys.min_slp_slow_clk_cycle = rtc_time_us_to_slowclk(mc->hp.min_slp_time_us, slowclk_period);
param->hp_sys.analog_wait_target_cycle = rtc_time_us_to_slowclk(mc->hp.analog_wait_time_us, slowclk_period);
@@ -157,25 +155,17 @@ static inline pmu_sleep_param_config_t * pmu_sleep_param_config_default(
return param;
}
const pmu_sleep_config_t* pmu_sleep_config_default(
pmu_sleep_config_t *config,
uint32_t sleep_flags,
pmu_sleep_clk_icg_flags_t clk_flags,
uint32_t adjustment,
soc_rtc_slow_clk_src_t slowclk_src,
uint32_t slowclk_period,
uint32_t fastclk_period,
bool dslp
)
const pmu_sleep_config_t* pmu_sleep_config_default(pmu_sleep_config_t *config, pmu_sleep_extra_args_t *args, bool dslp)
{
const uint32_t sleep_flags = args->sleep_flags;
pmu_sleep_power_config_t power_default = PMU_SLEEP_POWER_CONFIG_DEFAULT(sleep_flags);
#if !CONFIG_ESP32P4_SELECTS_REV_LESS_V3
power_default.hp_sys.dig_power.cpu_pd_en = (sleep_flags & PMU_SLEEP_PD_CPU) ? 1 : 0;
#endif
if (dslp) {
config->param.lp_sys.analog_wait_target_cycle = rtc_time_us_to_slowclk(PMU_LP_ANALOG_WAIT_TARGET_TIME_DSLP_US, slowclk_period);
config->param.lp_sys.analog_wait_target_cycle = rtc_time_us_to_slowclk(PMU_LP_ANALOG_WAIT_TARGET_TIME_DSLP_US, args->slowclk_period);
pmu_sleep_digital_config_t digital_default = PMU_SLEEP_DIGITAL_DSLP_CONFIG_DEFAULT(sleep_flags, clk_flags);
pmu_sleep_digital_config_t digital_default = PMU_SLEEP_DIGITAL_DSLP_CONFIG_DEFAULT(sleep_flags, args->clk_flags);
config->digital = digital_default;
pmu_sleep_analog_config_t analog_default = PMU_SLEEP_ANALOG_DSLP_CONFIG_DEFAULT(sleep_flags);
@@ -192,7 +182,7 @@ const pmu_sleep_config_t* pmu_sleep_config_default(
}
} else {
// Get light sleep digital_default
pmu_sleep_digital_config_t digital_default = PMU_SLEEP_DIGITAL_LSLP_CONFIG_DEFAULT(sleep_flags, clk_flags);
pmu_sleep_digital_config_t digital_default = PMU_SLEEP_DIGITAL_LSLP_CONFIG_DEFAULT(sleep_flags, args->clk_flags);
config->digital = digital_default;
// Get light sleep analog default
@@ -247,7 +237,7 @@ const pmu_sleep_config_t* pmu_sleep_config_default(
config->power = power_default;
pmu_sleep_param_config_t param_default = PMU_SLEEP_PARAM_CONFIG_DEFAULT(sleep_flags);
config->param = *pmu_sleep_param_config_default(&param_default, &power_default, sleep_flags, adjustment, slowclk_src, slowclk_period, fastclk_period);
config->param = *pmu_sleep_param_config_default(&param_default, &power_default, args);
return config;
}
components/esp_hw_support/port/esp32p4/private_include/pmu_param.h
+2 -2
View File
@@ -357,7 +357,7 @@ typedef struct {
.lp_pad_hold_all = (sleep_flags & PMU_SLEEP_PD_LP_PERIPH) ? 1 : 0, \
.dig_pause_wdt = ((sleep_flags) & RTC_SLEEP_USE_RTC_WDT) ? 0 : 1, \
}, \
.icg_func = { 0, (uint32_t)(clk_flags) } \
.icg_func = { (clk_flags)[1], (clk_flags)[0] } \
}
#else // !CONFIG_ESP32P4_SELECTS_REV_LESS_V3
#define PMU_SLEEP_DIGITAL_DSLP_CONFIG_DEFAULT(sleep_flags, clk_flags) { \
@@ -373,7 +373,7 @@ typedef struct {
.dig_pad_slp_sel = 0, \
.dig_pause_wdt = ((sleep_flags) & RTC_SLEEP_USE_RTC_WDT) ? 0 : 1, \
}, \
.icg_func = { 0, (uint32_t)(clk_flags) } \
.icg_func = { (clk_flags)[1], (clk_flags)[0] } \
}
#endif
components/esp_hw_support/port/esp32s31/pmu_sleep.c
+11 -18
View File
@@ -151,14 +151,15 @@ uint32_t pmu_sleep_calculate_hw_wait_time(uint32_t sleep_flags, soc_rtc_slow_clk
static inline pmu_sleep_param_config_t * pmu_sleep_param_config_default(
pmu_sleep_param_config_t *param,
pmu_sleep_power_config_t *power, /* We'll use the runtime power parameter to determine some hardware parameters */
const uint32_t sleep_flags,
const uint32_t adjustment,
soc_rtc_slow_clk_src_t slowclk_src,
const uint32_t slowclk_period,
const uint32_t fastclk_period
pmu_sleep_extra_args_t *args
)
{
const pmu_sleep_machine_constant_t *mc = (pmu_sleep_machine_constant_t *)PMU_instance()->mc;
const uint32_t sleep_flags = args->sleep_flags;
const uint32_t adjustment = args->adjustment;
const soc_rtc_slow_clk_src_t slowclk_src = args->slowclk_src;
const uint32_t slowclk_period = args->slowclk_period;
const uint32_t fastclk_period = args->fastclk_period;
#if (SOC_PM_PMU_MIN_SLP_SLOW_CLK_CYCLE_FIXED && CONFIG_ESP_WIFI_ENHANCED_LIGHT_SLEEP)
const uint32_t slowclk_period_fixed = (slowclk_src == SOC_RTC_SLOW_CLK_SRC_RC_SLOW) ? rtc_clk_freq_to_period(SOC_CLK_RC_SLOW_FREQ_APPROX) : slowclk_period;
@@ -194,21 +195,13 @@ static inline pmu_sleep_param_config_t * pmu_sleep_param_config_default(
return param;
}
const pmu_sleep_config_t* pmu_sleep_config_default(
pmu_sleep_config_t *config,
uint32_t sleep_flags,
pmu_sleep_clk_icg_flags_t clk_flags,
uint32_t adjustment,
soc_rtc_slow_clk_src_t slowclk_src,
uint32_t slowclk_period,
uint32_t fastclk_period,
bool dslp
)
const pmu_sleep_config_t* pmu_sleep_config_default(pmu_sleep_config_t *config, pmu_sleep_extra_args_t *args, bool dslp)
{
const uint32_t sleep_flags = args->sleep_flags;
pmu_sleep_power_config_t power_default = PMU_SLEEP_POWER_CONFIG_DEFAULT(sleep_flags);
if (dslp) {
config->param.lp_sys.analog_wait_target_cycle = rtc_time_us_to_slowclk(PMU_LP_ANALOG_WAIT_TARGET_TIME_DSLP_US, slowclk_period);
config->param.lp_sys.analog_wait_target_cycle = rtc_time_us_to_slowclk(PMU_LP_ANALOG_WAIT_TARGET_TIME_DSLP_US, args->slowclk_period);
pmu_sleep_digital_config_t digital_default = PMU_SLEEP_DIGITAL_DSLP_CONFIG_DEFAULT(sleep_flags);
config->digital = digital_default;
@@ -217,7 +210,7 @@ const pmu_sleep_config_t* pmu_sleep_config_default(
config->analog = analog_default;
} else {
// Get light sleep digital_default
pmu_sleep_digital_config_t digital_default = PMU_SLEEP_DIGITAL_LSLP_CONFIG_DEFAULT(sleep_flags, clk_flags);
pmu_sleep_digital_config_t digital_default = PMU_SLEEP_DIGITAL_LSLP_CONFIG_DEFAULT(sleep_flags, args->clk_flags);
config->digital = digital_default;
// Get light sleep analog default
@@ -258,7 +251,7 @@ const pmu_sleep_config_t* pmu_sleep_config_default(
config->power = power_default;
pmu_sleep_param_config_t param_default = PMU_SLEEP_PARAM_CONFIG_DEFAULT(sleep_flags);
config->param = *pmu_sleep_param_config_default(&param_default, &power_default, sleep_flags, adjustment, slowclk_src, slowclk_period, fastclk_period);
config->param = *pmu_sleep_param_config_default(&param_default, &power_default, args);
return config;
}
components/esp_hw_support/port/esp32s31/private_include/pmu_param.h
+1 -2
View File
@@ -351,8 +351,7 @@ typedef struct {
.c_channel = (sleep_flags & PMU_SLEEP_PD_TOP) ? 0 : 1 \
}, \
.icg_func = { \
.clock = { PMU_SLEEP_CLK_ICG_FUNC_LO(clk_flags), \
PMU_SLEEP_CLK_ICG_FUNC_HI(clk_flags) } \
.clock = { (clk_flags)[0], (clk_flags)[1] } \
}, \
}
components/esp_hw_support/sleep_modes.c
+27 -12
View File
@@ -18,7 +18,6 @@
#include "esp_private/esp_clk_tree_common.h"
#include "esp_private/esp_clk_utils.h"
#include "esp_private/esp_sleep_internal.h"
#include "esp_private/sleep_clock_icg.h"
#include "esp_private/esp_timer_private.h"
#include "esp_private/rtc_clk.h"
#include "soc/rtc.h"
@@ -169,6 +168,10 @@
#include "esp_private/sleep_clock.h"
#endif
#if SOC_PM_SUPPORT_PMU_CLK_ICG
#include "esp_private/sleep_clock_icg.h"
#endif
#if SOC_PM_RETENTION_SW_TRIGGER_REGDMA
#include "esp_private/sleep_retention.h"
#endif
@@ -1024,7 +1027,7 @@ static esp_err_t FORCE_IRAM_ATTR esp_sleep_start_safe(uint32_t sleep_flags, uint
return result;
}
static esp_err_t SLEEP_FN_ATTR esp_sleep_start(uint32_t sleep_flags, esp_sleep_mode_t mode, bool allow_sleep_rejection)
static esp_err_t SLEEP_FN_ATTR esp_sleep_start(uint32_t sleep_flags, esp_sleep_mode_t mode, bool allow_sleep_rejection, esp_sleep_extra_args_t *args)
{
// Stop UART output so that output is not lost due to APB frequency change.
// For light sleep, suspend UART output — it will resume after wakeup.
@@ -1165,12 +1168,18 @@ static esp_err_t SLEEP_FN_ATTR esp_sleep_start(uint32_t sleep_flags, esp_sleep_m
}
#endif
pmu_sleep_extra_args_t sleep_extra_args = {
.sleep_flags = sleep_flags,
.clk_flags = { args->clk_flags[0], args->clk_flags[1] },
.adjustment = s_config.sleep_time_adjustment,
.slowclk_src = rtc_clk_slow_src_get(),
.slowclk_period = s_config.rtc_clk_cal_period,
.fastclk_period = s_config.fast_clk_cal_period
};
pmu_sleep_config_t config;
pmu_sleep_clk_icg_flags_t clk_flags = deep_sleep ? 0 : esp_sleep_clock_get_clk_icg_flags();
pmu_sleep_init(pmu_sleep_config_default(&config, sleep_flags, clk_flags, s_config.sleep_time_adjustment,
rtc_clk_slow_src_get(), s_config.rtc_clk_cal_period, s_config.fast_clk_cal_period,
deep_sleep), deep_sleep);
pmu_sleep_init(pmu_sleep_config_default(&config, &sleep_extra_args, deep_sleep), deep_sleep);
#else
(void) args;
rtc_sleep_config_t config;
rtc_sleep_get_default_config(sleep_flags, &config);
rtc_sleep_init(config);
@@ -1318,9 +1327,9 @@ static esp_err_t FORCE_IRAM_ATTR deep_sleep_start(bool allow_sleep_rejection)
}
#endif // ESP_ROM_SUPPORT_DEEP_SLEEP_WAKEUP_STUB
esp_sleep_extra_args_t extra_args = { 0 };
// Decide which power domains can be powered down
uint32_t pd_flags = get_power_down_flags();
// Re-calibrate the RTC clock
sleep_low_power_clock_calibration(true);
@@ -1371,7 +1380,7 @@ static esp_err_t FORCE_IRAM_ATTR deep_sleep_start(bool allow_sleep_rejection)
uint32_t sleep_flags = get_sleep_flags(force_pd_flags | pd_flags, true);
// Enter sleep
esp_err_t err = ESP_OK;
if (esp_sleep_start(sleep_flags, ESP_SLEEP_MODE_DEEP_SLEEP, allow_sleep_rejection) == ESP_ERR_SLEEP_REJECT) {
if (esp_sleep_start(sleep_flags, ESP_SLEEP_MODE_DEEP_SLEEP, allow_sleep_rejection, &extra_args) == ESP_ERR_SLEEP_REJECT) {
err = ESP_ERR_SLEEP_REJECT;
#if CONFIG_ESP_SLEEP_CACHE_SAFE_ASSERTION
/* Cache Resume 2: if CONFIG_ESP_SLEEP_CACHE_SAFE_ASSERTION is enabled, cache has been suspended in esp_sleep_start */
@@ -1425,17 +1434,19 @@ esp_err_t FORCE_IRAM_ATTR esp_deep_sleep_try_to_start(void)
* Placed into IRAM as flash may need some time to be powered on.
*/
static esp_err_t esp_light_sleep_inner(uint32_t sleep_flags,
uint32_t flash_enable_time_us) __attribute__((noinline));
uint32_t flash_enable_time_us,
esp_sleep_extra_args_t *args) __attribute__((noinline));
static SLEEP_FN_ATTR esp_err_t esp_light_sleep_inner(uint32_t sleep_flags,
uint32_t flash_enable_time_us)
uint32_t flash_enable_time_us,
esp_sleep_extra_args_t *args)
{
#if SOC_CONFIGURABLE_VDDSDIO_SUPPORTED
rtc_vddsdio_config_t vddsdio_config = rtc_vddsdio_get_config();
#endif
// Enter sleep
esp_err_t reject = esp_sleep_start(sleep_flags, ESP_SLEEP_MODE_LIGHT_SLEEP, true);
esp_err_t reject = esp_sleep_start(sleep_flags, ESP_SLEEP_MODE_LIGHT_SLEEP, true, args);
#if SOC_CONFIGURABLE_VDDSDIO_SUPPORTED
// If VDDSDIO regulator was controlled by RTC registers before sleep,
@@ -1595,6 +1606,10 @@ esp_err_t esp_light_sleep_start(void)
uint32_t pd_flags = get_power_down_flags();
// Append flags to indicate the sleep sub-mode and modify the pd_flags according to sub-mode attributes.
uint32_t sleep_flags = get_sleep_flags(pd_flags, false);
esp_sleep_extra_args_t extra_args = { 0 };
#if SOC_PM_SUPPORT_PMU_CLK_ICG
esp_sleep_clock_get_clk_icg_flags(&extra_args.clk_flags[0], &extra_args.clk_flags[1]);
#endif
// Re-calibrate the RTC clock
sleep_low_power_clock_calibration(false);
@@ -1744,7 +1759,7 @@ esp_err_t esp_light_sleep_start(void)
#endif
else {
// Enter sleep, then wait for flash to be ready on wakeup
err = esp_light_sleep_inner(sleep_flags, flash_enable_time_us);
err = esp_light_sleep_inner(sleep_flags, flash_enable_time_us, &extra_args);
}
// light sleep wakeup flag only makes sense after a successful light sleep
components/soc/esp32c5/include/soc/pmu_icg_mapping.h
+1 -2
View File
@@ -73,8 +73,7 @@
extern "C" {
#endif
typedef uint32_t pmu_sleep_clk_icg_flags_t;
#define PMU_SLEEP_CLK_ICG_BIT(b) (((pmu_sleep_clk_icg_flags_t)1) << (b))
#define PMU_SLEEP_CLK_ICG_BIT(b) (((uint32_t)1) << (b))
#ifdef __cplusplus
}
components/soc/esp32c6/include/soc/pmu_icg_mapping.h
+1 -2
View File
@@ -72,8 +72,7 @@
extern "C" {
#endif
typedef uint32_t pmu_sleep_clk_icg_flags_t;
#define PMU_SLEEP_CLK_ICG_BIT(b) (((pmu_sleep_clk_icg_flags_t)1) << (b))
#define PMU_SLEEP_CLK_ICG_BIT(b) (((uint32_t)1) << (b))
#ifdef __cplusplus
}
components/soc/esp32c61/include/soc/pmu_icg_mapping.h
+1 -2
View File
@@ -60,8 +60,7 @@
extern "C" {
#endif
typedef uint32_t pmu_sleep_clk_icg_flags_t;
#define PMU_SLEEP_CLK_ICG_BIT(b) (((pmu_sleep_clk_icg_flags_t)1) << (b))
#define PMU_SLEEP_CLK_ICG_BIT(b) (((uint32_t)1) << (b))
#ifdef __cplusplus
}
components/soc/esp32h2/include/soc/pmu_icg_mapping.h
+1 -2
View File
@@ -69,8 +69,7 @@
extern "C" {
#endif
typedef uint32_t pmu_sleep_clk_icg_flags_t;
#define PMU_SLEEP_CLK_ICG_BIT(b) (((pmu_sleep_clk_icg_flags_t)1) << (b))
#define PMU_SLEEP_CLK_ICG_BIT(b) (((uint32_t)1) << (b))
#ifdef __cplusplus
}
components/soc/esp32h21/include/soc/pmu_icg_mapping.h
+1 -2
View File
@@ -71,8 +71,7 @@
extern "C" {
#endif
typedef uint32_t pmu_sleep_clk_icg_flags_t;
#define PMU_SLEEP_CLK_ICG_BIT(b) (((pmu_sleep_clk_icg_flags_t)1) << (b))
#define PMU_SLEEP_CLK_ICG_BIT(b) (((uint32_t)1) << (b))
#ifdef __cplusplus
}
components/soc/esp32h4/include/soc/pmu_icg_mapping.h
+1 -2
View File
@@ -72,8 +72,7 @@
extern "C" {
#endif
typedef uint32_t pmu_sleep_clk_icg_flags_t;
#define PMU_SLEEP_CLK_ICG_BIT(b) (((pmu_sleep_clk_icg_flags_t)1) << (b))
#define PMU_SLEEP_CLK_ICG_BIT(b) (((uint32_t)1) << (b))
#ifdef __cplusplus
}
components/soc/esp32p4/include/soc/pmu_icg_mapping.h
+1 -2
View File
@@ -68,8 +68,7 @@
extern "C" {
#endif
typedef uint32_t pmu_sleep_clk_icg_flags_t;
#define PMU_SLEEP_CLK_ICG_BIT(b) (((pmu_sleep_clk_icg_flags_t)1) << (b))
#define PMU_SLEEP_CLK_ICG_BIT(b) (((uint32_t)1) << (b))
#ifdef __cplusplus
}
components/soc/esp32s31/include/soc/pmu_icg_mapping.h
+1 -2
View File
@@ -107,8 +107,7 @@
extern "C" {
#endif
typedef uint64_t pmu_sleep_clk_icg_flags_t;
#define PMU_SLEEP_CLK_ICG_BIT(b) (((pmu_sleep_clk_icg_flags_t)1) << (b))
#define PMU_SLEEP_CLK_ICG_BIT(b) (((uint64_t)1) << (b))
#define PMU_SLEEP_CLK_ICG_FUNC_LO(f) ((uint32_t)(f))
#define PMU_SLEEP_CLK_ICG_FUNC_HI(f) ((uint32_t)((f) >> 32))