feat(lcd): support rgb and i80 lcd on s31

components/esp_hal_lcd/esp32p4/include/hal/lcd_ll.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2026 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -17,6 +17,7 @@
 #include "soc/hp_sys_clkrst_struct.h"
 
 #define LCD_LL_GET(_attr)       LCD_LL_ ## _attr
+#define LCD_LL_SUPPORT(_feat)   LCD_LL_SUPPORT_ ## _feat
 #define LCD_LL_RGB_BUS_WIDTH    24
 #define LCD_LL_RGB_PANEL_NUM    1
 #define LCD_LL_I80_BUS_WIDTH    24
@@ -45,7 +46,10 @@ extern "C" {
 #define LCD_LL_CLK_FRAC_DIV_N_MAX  256 // LCD_CLK = LCD_CLK_S / (N + b/a), the N register is 8 bit-width
 #define LCD_LL_CLK_FRAC_DIV_AB_MAX 64  // LCD_CLK = LCD_CLK_S / (N + b/a), the a/b register is 6 bit-width
 #define LCD_LL_PCLK_DIV_MAX        64  // LCD_PCLK = LCD_CLK / MO, the MO register is 6 bit-width
-#define LCD_LL_FIFO_DEPTH          8   // Async FIFO depth
+
+typedef enum {
+    LCD_LL_MEM_LP_MODE_SHUT_DOWN,
+} lcd_ll_mem_lp_mode_t;
 
 /**
  * @brief LCD data byte swizzle mode
@@ -172,6 +176,65 @@ static inline void lcd_ll_set_group_clock_coeff(lcd_cam_dev_t *dev, int div_num,
         lcd_ll_set_group_clock_coeff(__VA_ARGS__); \
     } while(0)
 
+/**
+ * @brief Force power on the LCD memory block, regardless of the outside PMU logic
+ *
+ * @param dev Peripheral instance address
+ */
+static inline void lcd_ll_mem_force_power_on(lcd_cam_dev_t *dev)
+{
+    (void)dev;
+    // P4 does not have transfer buffer
+}
+
+/**
+ * @brief Force the LCD memory block into low power mode, regardless of the outside PMU logic
+ *
+ * @param dev Peripheral instance address
+ */
+static inline void lcd_ll_mem_force_low_power(lcd_cam_dev_t *dev)
+{
+    (void)dev;
+    // P4 does not have transfer buffer
+}
+
+/**
+ * @brief Power control the LCD memory block by the outside PMU logic
+ *
+ * @param dev Peripheral instance address
+ * @param mode LCD memory low power mode in low power stage
+ */
+static inline void lcd_ll_mem_power_by_pmu(lcd_cam_dev_t *dev)
+{
+    (void)dev;
+    // P4 does not have transfer buffer
+}
+
+/**
+ * @brief Set low power mode for LCD memory block
+ *
+ * @param dev Peripheral instance address
+ * @param mode LCD memory low power mode in low power stage
+ */
+static inline void lcd_ll_mem_set_low_power_mode(lcd_cam_dev_t *dev, lcd_ll_mem_lp_mode_t mode)
+{
+    (void)dev;
+    HAL_ASSERT(mode == LCD_LL_MEM_LP_MODE_SHUT_DOWN);
+}
+
+/**
+ * @brief Enable the transfer buffer(memory block) for LCD module
+ *
+ * @param dev Peripheral instance address
+ * @param en True to enable, False to disable
+ */
+static inline void lcd_ll_enable_trans_buffer(lcd_cam_dev_t *dev, bool en)
+{
+    (void)dev;
+    (void)en;
+    // P4 does not have transfer buffer
+}
+
 /**
  * @brief Set the PCLK clock level state when there's no transaction undergoing
  *

components/esp_hal_lcd/esp32p4/lcd_periph.c

@@ -85,18 +85,16 @@ const soc_lcd_rgb_signal_desc_t soc_lcd_rgb_signals[1] = {
 /**
  * LCD_CAM Registers to be saved during sleep retention
  * - LCD Clock Configuration registers: LCDCAM_LCD_CLOCK_REG (0x0)
- * - LCD RGB/YUV Configuration registers: LCDCAM_LCD_RGB_YUV_REG (0x10)
  * - LCD User Configuration registers: LCDCAM_LCD_USER_REG (0x14), LCDCAM_LCD_MISC_REG (0x18)
- * - LCD Control registers: LCDCAM_LCD_CTRL_REG (0x1c), LCDCAM_LCD_CTRL1_REG (0x20), LCDCAM_LCD_CTRL2_REG (0x24)
- * - LCD Command Value registers: LCDCAM_LCD_FIRST_CMD_VAL_REG (0x28), LCDCAM_LCD_LATTER_CMD_VAL_REG (0x2c)
+ * - LCD Control registers: LCDCAM_LCD_CTRL_REG (0x1c) (Note: lcd_rgb_mode_en is in this register)
  * - LCD Delay Mode Configuration registers: LCDCAM_LCD_DLY_MODE_CFG1_REG (0x30), LCDCAM_LCD_DLY_MODE_CFG2_REG (0x38)
  * - LCD DMA Interrupt Enable register: LCDCAM_LC_DMA_INT_ENA_REG (0x64)
  *
  *  NOTE: Only I80 LCD supports sleep retention, not RGB LCD.
  */
-#define LCD_RETENTION_REGS_CNT 12
+#define LCD_RETENTION_REGS_CNT 7
 #define LCD_RETENTION_REGS_BASE (DR_REG_LCDCAM_BASE + 0x0)
-static const uint32_t lcd_cam_regs_map[4] = {0x2005ff1, 0x0, 0x0, 0x0};
+static const uint32_t lcd_cam_regs_map[4] = {0x20050e1, 0x0, 0x0, 0x0};
 static const regdma_entries_config_t lcd_regs_retention[] = {
     // backup stage: save configuration registers
     // restore stage: restore the configuration registers