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fix(esp_hw_support): fix ESP32-S31 CPU/DFS clk_tree refcount and keep clock source during DFS

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wuzhenghui
2026-08-20 16:00:52 +08:00
parent 4b34a6b250
commit a3b62bc3c4
13 changed files with 235 additions and 157 deletions
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components/esp_hal_mspi/esp32s31/include/hal/mspi_ll.h
+25 -1
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@@ -48,7 +48,7 @@ extern "C" {
#define MSPI_LL_PERIPH_NUM 4
#define MSPI_TIMING_LL_MSPI_ID_0 0
#define MSPI_TIMING_LL_MSPI_ID_1 1
#define MSPI_TIMING_LL_FLASH_CORE_80M_CLK_DIV 4
#define MSPI_TIMING_LL_FLASH_CORE_80M_CLK_DIV 4 // clk src is 320M CPLL
// PSRAM frequency should be constrained by AXI frequency to avoid FIFO underflow.
#define MSPI_TIMING_LL_PSRAM_FREQ_AXI_CONSTRAINED 1
@@ -218,6 +218,30 @@ static inline void _mspi_timing_ll_set_flash_clk_src(uint32_t mspi_id, soc_perip
HP_SYS_CLKRST.flash_ctrl0.reg_flash_clk_src_sel = clk_val;
}
/**
* @brief Get FLASH clock source
*
* @param mspi_id mspi_id
*
* @return clock source, see valid sources in type `soc_periph_flash_clk_src_t`
*/
__attribute__((always_inline))
static inline soc_periph_flash_clk_src_t _mspi_timing_ll_get_flash_clk_src(uint32_t mspi_id)
{
HAL_ASSERT(mspi_id == MSPI_TIMING_LL_MSPI_ID_0);
switch (HP_SYS_CLKRST.flash_ctrl0.reg_flash_clk_src_sel) {
case 0:
return FLASH_CLK_SRC_XTAL;
case 1:
return FLASH_CLK_SRC_BBPLL;
case 2:
return FLASH_CLK_SRC_CPLL;
default:
HAL_ASSERT(false);
return FLASH_CLK_SRC_XTAL;
}
}
/**
* Set MSPI Flash core clock
*