diff --git a/components/soc/esp32p4/include/soc/system_periph_retention.h b/components/soc/esp32p4/include/soc/system_periph_retention.h index 590c7ed3aaf..805c5a8de5e 100644 --- a/components/soc/esp32p4/include/soc/system_periph_retention.h +++ b/components/soc/esp32p4/include/soc/system_periph_retention.h @@ -32,7 +32,7 @@ extern const regdma_entries_config_t intr_matrix_regs_retention[INT_MTX_RETENTIO * This is an internal function of the sleep retention driver, and is not * useful for external use. */ -#define CACHE_RETENTION_LINK_LEN 10 +#define CACHE_RETENTION_LINK_LEN 12 extern const regdma_entries_config_t cache_regs_retention[CACHE_RETENTION_LINK_LEN]; /** diff --git a/components/soc/esp32p4/system_retention_periph.c b/components/soc/esp32p4/system_retention_periph.c index c5e10eee4d7..2a9d3ddc1cd 100644 --- a/components/soc/esp32p4/system_retention_periph.c +++ b/components/soc/esp32p4/system_retention_periph.c @@ -46,17 +46,23 @@ static const uint32_t l1_cache_regs_map[4] = {0x7, 0x0, 0xc000000, 0x0}; CACHE_L2_CACHE_ACS_FAIL_CTRL_REG & CACHE_L2_CACHE_ACS_FAIL_INT_ENA_REG */ #define L2_CACHE_RETENTION_REGS_CNT (6) #define L2_CACHE_RETENTION_REGS_BASE (CACHE_L2_CACHE_CTRL_REG) +#define L1_CACHE_ACS_FAIL_INR_CLR (CACHE_L1_ICACHE0_FAIL_INT_CLR | CACHE_L1_ICACHE1_FAIL_INT_CLR | CACHE_L1_ICACHE2_FAIL_INT_CLR | CACHE_L1_ICACHE3_FAIL_INT_CLR |CACHE_L1_DCACHE_FAIL_INT_CLR) +#define L1_CACHE_ACS_FAIL_INR_CLR_M (CACHE_L1_ICACHE0_FAIL_INT_CLR_M | CACHE_L1_ICACHE1_FAIL_INT_CLR_M | CACHE_L1_ICACHE2_FAIL_INT_CLR_M | CACHE_L1_ICACHE3_FAIL_INT_CLR_M |CACHE_L1_DCACHE_FAIL_INT_CLR_M) + static const uint32_t l2_cache_regs_map[4] = {0xc000000f, 0x0, 0x0, 0x0}; const regdma_entries_config_t cache_regs_retention[] = { - [0] = { - .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_CACHE_LINK(0x00), L1_CACHE_RETENTION_REGS_BASE, L1_CACHE_RETENTION_REGS_BASE, \ + // Clear the cache error status, since the auto clock gating added to the cache after version v3, it may falsely report cache acs fail when the module is reset. + [0] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_CACHE_LINK(0x00), CACHE_L1_CACHE_ACS_FAIL_INT_CLR_REG, L1_CACHE_ACS_FAIL_INR_CLR, L1_CACHE_ACS_FAIL_INR_CLR_M, 1, 0), .owner = ENTRY(0) }, + [1] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_CACHE_LINK(0x01), CACHE_L2_CACHE_ACS_FAIL_INT_CLR_REG, CACHE_L2_CACHE_FAIL_INT_CLR, CACHE_L2_CACHE_FAIL_INT_CLR_M, 1, 0), .owner = ENTRY(0) }, + [2] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_CACHE_LINK(0x02), L1_CACHE_RETENTION_REGS_BASE, L1_CACHE_RETENTION_REGS_BASE, \ L1_CACHE_RETENTION_REGS_CNT, 0, 0, \ l1_cache_regs_map[0], l1_cache_regs_map[1], \ l1_cache_regs_map[2], l1_cache_regs_map[3]), \ .owner = ENTRY(0) }, - [1] = { - .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_CACHE_LINK(0x01), \ + [3] = { + .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_CACHE_LINK(0x03), \ L2_CACHE_RETENTION_REGS_BASE, L2_CACHE_RETENTION_REGS_BASE, \ L2_CACHE_RETENTION_REGS_CNT, 0, 0, \ l2_cache_regs_map[0], l2_cache_regs_map[1], \ @@ -64,15 +70,15 @@ const regdma_entries_config_t cache_regs_retention[] = { .owner = ENTRY(0) }, // Invalidate L1 Cache - [2] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_CACHE_LINK(0x02), CACHE_SYNC_ADDR_REG, 0, CACHE_SYNC_ADDR_M, 1, 0), .owner = ENTRY(0) }, - [3] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_CACHE_LINK(0x03), CACHE_SYNC_SIZE_REG, 0, CACHE_SYNC_SIZE_M, 1, 0), .owner = ENTRY(0) }, - [4] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_CACHE_LINK(0x04), CACHE_SYNC_MAP_REG, CACHE_MAP_L1_CACHE_MASK, CACHE_SYNC_MAP_M, 1, 0), .owner = ENTRY(0) }, - [5] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_CACHE_LINK(0x05), CACHE_SYNC_CTRL_REG, 0, CACHE_SYNC_RGID_M, 1, 0), .owner = ENTRY(0) }, - [6] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_CACHE_LINK(0x06), CACHE_SYNC_CTRL_REG, CACHE_INVALIDATE_ENA, CACHE_INVALIDATE_ENA_M, 1, 0), .owner = ENTRY(0) }, - [7] = { .config = REGDMA_LINK_WAIT_INIT(REGDMA_CACHE_LINK(0x07), CACHE_SYNC_CTRL_REG, CACHE_SYNC_DONE, CACHE_SYNC_DONE_M, 1, 0), .owner = ENTRY(0) }, + [4] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_CACHE_LINK(0x04), CACHE_SYNC_ADDR_REG, 0, CACHE_SYNC_ADDR_M, 1, 0), .owner = ENTRY(0) }, + [5] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_CACHE_LINK(0x05), CACHE_SYNC_SIZE_REG, 0, CACHE_SYNC_SIZE_M, 1, 0), .owner = ENTRY(0) }, + [6] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_CACHE_LINK(0x06), CACHE_SYNC_MAP_REG, CACHE_MAP_L1_CACHE_MASK, CACHE_SYNC_MAP_M, 1, 0), .owner = ENTRY(0) }, + [7] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_CACHE_LINK(0x07), CACHE_SYNC_CTRL_REG, 0, CACHE_SYNC_RGID_M, 1, 0), .owner = ENTRY(0) }, + [8] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_CACHE_LINK(0x08), CACHE_SYNC_CTRL_REG, CACHE_INVALIDATE_ENA, CACHE_INVALIDATE_ENA_M, 1, 0), .owner = ENTRY(0) }, + [9] = { .config = REGDMA_LINK_WAIT_INIT(REGDMA_CACHE_LINK(0x09), CACHE_SYNC_CTRL_REG, CACHE_SYNC_DONE, CACHE_SYNC_DONE_M, 1, 0), .owner = ENTRY(0) }, // Reset L2 CACHE SYNC - [8] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_CACHE_LINK(0x08), CACHE_L2_CACHE_SYNC_RST_CTRL_REG, CACHE_L2_CACHE_SYNC_RST, CACHE_L2_CACHE_SYNC_RST_M, 1, 0), .owner = ENTRY(0) }, - [9] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_CACHE_LINK(0x09), CACHE_L2_CACHE_SYNC_RST_CTRL_REG, 0, CACHE_L2_CACHE_SYNC_RST_M, 1, 0), .owner = ENTRY(0) }, + [10] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_CACHE_LINK(0x10), CACHE_L2_CACHE_SYNC_RST_CTRL_REG, CACHE_L2_CACHE_SYNC_RST, CACHE_L2_CACHE_SYNC_RST_M, 1, 0), .owner = ENTRY(0) }, + [11] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_CACHE_LINK(0x11), CACHE_L2_CACHE_SYNC_RST_CTRL_REG, 0, CACHE_L2_CACHE_SYNC_RST_M, 1, 0), .owner = ENTRY(0) }, }; _Static_assert(ARRAY_SIZE(cache_regs_retention) == CACHE_RETENTION_LINK_LEN, "Inconsistent L2 CACHE retention link length definitions");