feat(cam): add esp32s3 dvp cam support

components/soc/esp32s3/cam_periph.c

@@ -0,0 +1,40 @@
+/*
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "soc/gpio_sig_map.h"
+#include "soc/cam_periph.h"
+
+const cam_signal_conn_t cam_periph_signals = {
+    .buses = {
+        [0] = {
+            .module = PERIPH_LCD_CAM_MODULE,
+            .irq_id = ETS_LCD_CAM_INTR_SOURCE,
+            .data_sigs = {
+                CAM_DATA_IN0_IDX,
+                CAM_DATA_IN1_IDX,
+                CAM_DATA_IN2_IDX,
+                CAM_DATA_IN3_IDX,
+                CAM_DATA_IN4_IDX,
+                CAM_DATA_IN5_IDX,
+                CAM_DATA_IN6_IDX,
+                CAM_DATA_IN7_IDX,
+                CAM_DATA_IN8_IDX,
+                CAM_DATA_IN9_IDX,
+                CAM_DATA_IN10_IDX,
+                CAM_DATA_IN11_IDX,
+                CAM_DATA_IN12_IDX,
+                CAM_DATA_IN13_IDX,
+                CAM_DATA_IN14_IDX,
+                CAM_DATA_IN15_IDX
+            },
+            .hsync_sig = CAM_H_SYNC_IDX,
+            .vsync_sig = CAM_V_SYNC_IDX,
+            .pclk_sig = CAM_PCLK_IDX,
+            .de_sig = CAM_H_ENABLE_IDX,
+            .clk_sig = CAM_CLK_IDX
+        }
+    }
+};

components/soc/esp32s3/include/soc/Kconfig.soc_caps.in

@@ -63,6 +63,10 @@ config SOC_LCDCAM_SUPPORTED
     bool
     default y
 
+config SOC_LCDCAM_CAM_SUPPORTED
+    bool
+    default y
+
 config SOC_LCDCAM_I80_LCD_SUPPORTED
     bool
     default y
@@ -1486,3 +1490,15 @@ config SOC_ULP_HAS_ADC
 config SOC_PHY_COMBO_MODULE
     bool
     default y
+
+config SOC_LCDCAM_CAM_SUPPORT_RGB_YUV_CONV
+    bool
+    default y
+
+config SOC_LCDCAM_CAM_PERIPH_NUM
+    int
+    default 1
+
+config SOC_LCDCAM_CAM_DATA_WIDTH_MAX
+    int
+    default 16

components/soc/esp32s3/include/soc/clk_tree_defs.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -21,7 +21,7 @@ extern "C" {
  *
  * 2) External 40MHz Crystal Clock: XTAL
  *
- * 3) Internal 136kHz RC Oscillator: RC_SLOW (usually referrred as RTC in TRM or reg. description)
+ * 3) Internal 136kHz RC Oscillator: RC_SLOW (usually referred as RTC in TRM or reg. description)
  *
  *    This RC oscillator generates a ~136kHz clock signal output as the RC_SLOW_CLK. The exact frequency of this clock
  *    can be computed in runtime through calibration.
@@ -187,6 +187,23 @@ typedef enum {
     LCD_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the default choice */
 } soc_periph_lcd_clk_src_t;
 
+//////////////////////////////////////////////////LCD///////////////////////////////////////////////////////////////////
+
+/**
+ * @brief Array initializer for all supported clock sources of CAM
+ */
+#define SOC_CAM_CLKS {SOC_MOD_CLK_PLL_F160M, SOC_MOD_CLK_PLL_D2, SOC_MOD_CLK_XTAL}
+
+/**
+ * @brief Type of CAM clock source
+ */
+typedef enum {
+    CAM_CLK_SRC_PLL160M = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the source clock */
+    CAM_CLK_SRC_PLL240M = SOC_MOD_CLK_PLL_D2,    /*!< Select PLL_D2 as the source clock */
+    CAM_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL,         /*!< Select XTAL as the source clock */
+    CAM_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_D2,    /*!< Select PLL_D2 as the default choice */
+} soc_periph_cam_clk_src_t;
+
 //////////////////////////////////////////////////RMT///////////////////////////////////////////////////////////////////
 
 /**

components/soc/esp32s3/include/soc/soc_caps.h

@@ -32,6 +32,7 @@
 #define SOC_AHB_GDMA_SUPPORTED          1
 #define SOC_GPTIMER_SUPPORTED           1
 #define SOC_LCDCAM_SUPPORTED            1
+#define SOC_LCDCAM_CAM_SUPPORTED        1 // support the camera driver based on the LCD_CAM peripheral
 #define SOC_LCDCAM_I80_LCD_SUPPORTED    1
 #define SOC_LCDCAM_RGB_LCD_SUPPORTED    1
 #define SOC_MCPWM_SUPPORTED             1
@@ -584,3 +585,8 @@
 
 /*------------------------------------- PHY CAPS -------------------------------------*/
 #define SOC_PHY_COMBO_MODULE                  (1) /*!< Support Wi-Fi and BLE*/
+
+/*--------------------------- CAM ---------------------------------*/
+#define SOC_LCDCAM_CAM_SUPPORT_RGB_YUV_CONV         (1)
+#define SOC_LCDCAM_CAM_PERIPH_NUM                   (1U)
+#define SOC_LCDCAM_CAM_DATA_WIDTH_MAX               (16U)