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feat(esp_security): support s31 security clock management

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This commit is contained in:
wuzhenghui
2026-07-22 16:32:45 +08:00
parent c7de92feda
commit a04dc898db
25 changed files with 508 additions and 43 deletions
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components/esp_security/src/esp32c5/esp_crypto_clk.h
+4 -5
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@@ -1,20 +1,19 @@
/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2024-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/soc.h"
#include "soc/pcr_reg.h"
#pragma once
#include <stdbool.h>
#include "hal/sec_ll.h"
#include "soc/clk_tree_defs.h"
void esp_crypto_common_clk_enable(bool enable);
static inline void esp_crypto_clk_init(void)
{
// Set crypto clock (`clk_sec`) to use 480M SPLL clock
REG_SET_FIELD(PCR_SEC_CONF_REG, PCR_SEC_CLK_SEL, 0x2);
sec_ll_crypto_clk_src_sel(SOC_MOD_CLK_SPLL);
}
components/esp_security/src/esp32c61/esp_crypto_clk.h
+4 -5
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@@ -1,20 +1,19 @@
/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2024-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/soc.h"
#include "soc/pcr_reg.h"
#pragma once
#include <stdbool.h>
#include "hal/sec_ll.h"
#include "soc/clk_tree_defs.h"
void esp_crypto_common_clk_enable(bool enable);
static inline void esp_crypto_clk_init(void)
{
// Set crypto clock (`clk_sec`) to use 480M SPLL clock
REG_SET_FIELD(PCR_SEC_CONF_REG, PCR_SEC_CLK_SEL, 0x2);
sec_ll_crypto_clk_src_sel(SOC_MOD_CLK_SPLL);
}
components/esp_security/src/esp32h2/esp_crypto_clk.h
+4 -5
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@@ -1,20 +1,19 @@
/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2024-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/soc.h"
#include "soc/pcr_reg.h"
#pragma once
#include <stdbool.h>
#include "hal/sec_ll.h"
#include "soc/clk_tree_defs.h"
void esp_crypto_common_clk_enable(bool enable);
static inline void esp_crypto_clk_init(void)
{
// Set crypto clock (`clk_sec`) to use 96M PLL clock
REG_SET_FIELD(PCR_SEC_CONF_REG, PCR_SEC_CLK_SEL, 0x3);
sec_ll_crypto_clk_src_sel(SOC_MOD_CLK_PLL_F96M);
}
components/esp_security/src/esp32h21/esp_crypto_clk.h
+3 -2
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2024-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -7,6 +7,7 @@
#include "soc/soc.h"
#include "soc/pcr_reg.h"
#include "esp_private/esp_clk_tree_common.h"
#include "hal/sec_ll.h"
#pragma once
@@ -18,5 +19,5 @@ static inline void esp_crypto_clk_init(void)
{
// Set crypto clock (`clk_sec`) to use 96M PLL clock
esp_clk_tree_enable_src(SOC_MOD_CLK_PLL_F96M, true);
REG_SET_FIELD(PCR_SEC_CONF_REG, PCR_SEC_CLK_SEL, 0x3);
sec_ll_crypto_clk_src_sel(SOC_MOD_CLK_PLL_F96M);
}
components/esp_security/src/esp32h4/esp_crypto_clk.h
+3 -2
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -7,6 +7,7 @@
#include "soc/soc.h"
#include "soc/pcr_reg.h"
#include "esp_private/esp_clk_tree_common.h"
#include "hal/sec_ll.h"
#pragma once
@@ -18,5 +19,5 @@ static inline void esp_crypto_clk_init(void)
{
// Set crypto clock (`clk_sec`) to use 96M PLL clock
esp_clk_tree_enable_src(SOC_MOD_CLK_PLL_F96M, true);
REG_SET_FIELD(PCR_SEC_CONF_REG, PCR_SEC_CLK_SEL, 0x3);
sec_ll_crypto_clk_src_sel(SOC_MOD_CLK_PLL_F96M);
}
components/esp_security/src/esp32p4/esp_crypto_clk.h
+6 -5
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@@ -1,14 +1,15 @@
/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2024-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/soc.h"
#include "soc/hp_sys_clkrst_reg.h"
#include "esp_private/esp_clk_tree_common.h"
#pragma once
#include <stdbool.h>
#include "hal/sec_ll.h"
#include "soc/clk_tree_defs.h"
#include "esp_private/esp_clk_tree_common.h"
void esp_crypto_common_clk_enable(bool enable);
@@ -16,5 +17,5 @@ static inline void esp_crypto_clk_init(void)
{
// Set crypto clock (`clk_sec`) to use 240M PLL clock
esp_clk_tree_enable_src(SOC_MOD_CLK_PLL_F240M, true);
REG_SET_FIELD(HP_SYS_CLKRST_PERI_CLK_CTRL25_REG, HP_SYS_CLKRST_REG_CRYPTO_CLK_SRC_SEL, 0x2);
sec_ll_crypto_clk_src_sel(SOC_MOD_CLK_PLL_F240M);
}
components/esp_security/src/esp32s31/esp_crypto_clk.c
+33 -13
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@@ -4,35 +4,55 @@
* SPDX-License-Identifier: Apache-2.0
*/
#include "esp_attr.h"
#include "esp_crypto_clk.h"
#include "soc/clk_tree_defs.h"
#include "soc/hp_sys_clkrst_struct.h"
#include "hal/clk_gate_ll.h"
#include "esp_private/esp_clk_tree_common.h"
#if !NON_OS_BUILD
#include "esp_private/critical_section.h"
#endif
#if !NON_OS_BUILD
DEFINE_CRIT_SECTION_LOCK_STATIC(s_crypto_common_clk_mux);
#define CRYPTO_CLK_LOCK() esp_os_enter_critical_safe(&s_crypto_common_clk_mux)
#define CRYPTO_CLK_UNLOCK() esp_os_exit_critical_safe(&s_crypto_common_clk_mux)
#else
#define CRYPTO_CLK_LOCK()
#define CRYPTO_CLK_UNLOCK()
#endif
static int s_crypto_common_clk_ref_cnt;
static void esp_crypto_pll_f240m_enable(bool enable)
{
#if !NON_OS_BUILD
esp_clk_tree_enable_src(SOC_MOD_CLK_PLL_F240M, enable);
#else
/* Bootloader: BBPLL is already on; no esp_clk_tree in NON_OS. */
_clk_gate_ll_ref_240m_clk_en(enable);
#endif
}
FORCE_INLINE_ATTR void esp_crypto_periph_clk_enable(bool enable)
{
HP_SYS_CLKRST.crypto_ctrl0.reg_crypto_sys_clk_en = enable;
HP_SYS_CLKRST.crypto_ctrl0.reg_crypto_sec_clk_en = enable;
}
void esp_crypto_common_clk_enable(bool enable)
{
#if !NON_OS_BUILD
esp_os_enter_critical_safe(&s_crypto_common_clk_mux);
#endif
CRYPTO_CLK_LOCK();
if (enable) {
if (s_crypto_common_clk_ref_cnt++ == 0) {
HP_SYS_CLKRST.crypto_ctrl0.reg_crypto_sys_clk_en = 1;
HP_SYS_CLKRST.crypto_ctrl0.reg_crypto_sec_clk_en = 1;
}
} else {
if (s_crypto_common_clk_ref_cnt > 0 && --s_crypto_common_clk_ref_cnt == 0) {
HP_SYS_CLKRST.crypto_ctrl0.reg_crypto_sec_clk_en = 0;
HP_SYS_CLKRST.crypto_ctrl0.reg_crypto_sys_clk_en = 0;
/* Parent: PLL_F240M (see esp_crypto_clk_init() REG_CRYPTO_CLK_SRC_SEL). */
esp_crypto_pll_f240m_enable(true);
esp_crypto_periph_clk_enable(true);
}
} else if (s_crypto_common_clk_ref_cnt > 0 && --s_crypto_common_clk_ref_cnt == 0) {
esp_crypto_periph_clk_enable(false);
esp_crypto_pll_f240m_enable(false);
}
#if !NON_OS_BUILD
esp_os_exit_critical_safe(&s_crypto_common_clk_mux);
#endif
CRYPTO_CLK_UNLOCK();
}
components/esp_security/src/esp32s31/esp_crypto_clk.h
+3 -4
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@@ -7,14 +7,13 @@
#pragma once
#include <stdbool.h>
#include "soc/soc.h"
#include "soc/hp_sys_clkrst_reg.h"
#include "soc/hp_sys_clkrst_struct.h"
#include "hal/sec_ll.h"
#include "soc/clk_tree_defs.h"
static inline void esp_crypto_clk_init(void)
{
// Set crypto clock (`clk_sec`) to use 240M PLL clock
REG_SET_FIELD(HP_SYS_CLKRST_CRYPTO_CTRL0_REG, HP_SYS_CLKRST_REG_CRYPTO_CLK_SRC_SEL, 0x2);
sec_ll_crypto_clk_src_sel(SOC_MOD_CLK_PLL_F240M);
}
void esp_crypto_common_clk_enable(bool enable);