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Merge branch 'feat/enable_esp32p4_auto_clock_gate_v5.4' into 'release/v5.4'

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feat(esp_hw_support): enable auto clock gating for multi peripherals (v5.4)

See merge request espressif/esp-idf!38443
This commit is contained in:
Jiang Jiang Jian
2025-04-17 17:13:40 +08:00
parent 9c9d5cc1a2 7643f77225
commit 9f8548bb2d
4 changed files with 61 additions and 2 deletions
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components/esp_system/port/soc/esp32p4/clk.c
+22 -1
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -32,10 +32,12 @@
#include "soc/usb_serial_jtag_reg.h"
#include "soc/trace_struct.h"
#include "hal/adc_ll.h"
#include "hal/aes_ll.h"
#include "hal/assist_debug_ll.h"
#include "hal/ds_ll.h"
#include "hal/ecc_ll.h"
#include "hal/emac_ll.h"
#include "hal/etm_ll.h"
#include "hal/gdma_ll.h"
#include "hal/hmac_ll.h"
@@ -248,6 +250,25 @@ __attribute__((weak)) void esp_perip_clk_init(void)
|| (rst_reason == RESET_REASON_SYS_BROWN_OUT) || (rst_reason == RESET_REASON_SYS_RWDT) || (rst_reason == RESET_REASON_SYS_SUPER_WDT)
|| (rst_reason == RESET_REASON_CORE_SW) || (rst_reason == RESET_REASON_CORE_MWDT) || (rst_reason == RESET_REASON_CORE_RWDT) || (rst_reason == RESET_REASON_CORE_PWR_GLITCH) || (rst_reason == RESET_REASON_CORE_EFUSE_CRC) || (rst_reason == RESET_REASON_CORE_USB_JTAG) || (rst_reason == RESET_REASON_CORE_USB_UART)
) {
// Not gate HP_SYS_CLKRST_REG_L2MEM_MEM_CLK_FORCE_ON since the hardware will not automatically ungate when DMA accesses L2 MEM.
REG_CLR_BIT(HP_SYS_CLKRST_CLK_FORCE_ON_CTRL0_REG, HP_SYS_CLKRST_REG_CPUICM_GATED_CLK_FORCE_ON
| HP_SYS_CLKRST_REG_TCM_CPU_CLK_FORCE_ON
| HP_SYS_CLKRST_REG_BUSMON_CPU_CLK_FORCE_ON
| HP_SYS_CLKRST_REG_L1CACHE_CPU_CLK_FORCE_ON
| HP_SYS_CLKRST_REG_L1CACHE_D_CPU_CLK_FORCE_ON
| HP_SYS_CLKRST_REG_L1CACHE_I0_CPU_CLK_FORCE_ON
| HP_SYS_CLKRST_REG_L1CACHE_I1_CPU_CLK_FORCE_ON
| HP_SYS_CLKRST_REG_TRACE_CPU_CLK_FORCE_ON
| HP_SYS_CLKRST_REG_TRACE_SYS_CLK_FORCE_ON
| HP_SYS_CLKRST_REG_L1CACHE_MEM_CLK_FORCE_ON
| HP_SYS_CLKRST_REG_L1CACHE_D_MEM_CLK_FORCE_ON
| HP_SYS_CLKRST_REG_L1CACHE_I0_MEM_CLK_FORCE_ON
| HP_SYS_CLKRST_REG_L1CACHE_I1_MEM_CLK_FORCE_ON
| HP_SYS_CLKRST_REG_L2CACHE_MEM_CLK_FORCE_ON);
_adc_ll_sar1_clock_force_en(false);
_adc_ll_sar2_clock_force_en(false);
_emac_ll_clock_force_en(false);
// hp_sys_clkrst register gets reset only if chip reset or pmu powers down hp
// but at core reset and above, we will also disable HP modules' clock gating to save power consumption
_gdma_ll_enable_bus_clock(0, false);