Mirrors/esp-idf
1
0
Fork 0
mirror of https://github.com/espressif/esp-idf.git synced 2026-10-03 03:31:41 +03:00
Code Issues Packages Projects Releases Wiki Activity

fix(esp_eth): fixed ESP32P4 EMAC REF RMII CLK output mode

Browse Source 
fixed units returned and used by periph_rtc_mpll_freq_set function
This commit is contained in:
Ondrej Kosta
2025-04-01 08:34:45 +02:00
parent 07f4ff8c00
commit 9f4acf245a
14 changed files with 282 additions and 36 deletions
Download Patch File Download Diff File Expand all files Collapse all files
components/soc/esp32p4/include/soc/clk_tree_defs.h
+1
View File
@@ -145,6 +145,7 @@ typedef enum {
// For digital domain: peripherals
SOC_MOD_CLK_PLL_F20M, /*!< PLL_F20M_CLK is derived from SPLL (clock gating + default divider 24), its default frequency is 20MHz */
SOC_MOD_CLK_PLL_F25M, /*!< PLL_F25M_CLK is derived from MPLL (clock gating + configurable divider), it will have a frequency of 25MHz */
SOC_MOD_CLK_PLL_F50M, /*!< PLL_F50M_CLK is derived from MPLL (clock gating + configurable divider 10), it will have a frequency of 50MHz */
SOC_MOD_CLK_PLL_F80M, /*!< PLL_F80M_CLK is derived from SPLL (clock gating + default divider 6), its default frequency is 80MHz */
SOC_MOD_CLK_PLL_F160M, /*!< PLL_F160M_CLK is derived from SPLL (clock gating + default divider 3), its default frequency is 160MHz */
SOC_MOD_CLK_PLL_F240M, /*!< PLL_F240M_CLK is derived from SPLL (clock gating + default divider 2), its default frequency is 240MHz */