fix(esp_eth): fixed ESP32P4 EMAC REF RMII CLK output mode

fixed units returned and used by periph_rtc_mpll_freq_set function

components/esp_hw_support/include/esp_private/esp_clk_tree_common.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -7,6 +7,7 @@
 #pragma once
 
 #include <stdint.h>
+#include <stdbool.h>
 #include "esp_clk_tree.h"
 #include "soc/soc_caps.h"
 
@@ -74,6 +75,23 @@ uint32_t esp_clk_tree_lp_slow_get_freq_hz(esp_clk_tree_src_freq_precision_t prec
  */
 uint32_t esp_clk_tree_lp_fast_get_freq_hz(esp_clk_tree_src_freq_precision_t precision);
 
+/**
+ * @brief Enable / Disable the clock gate of the clock source
+ *
+ * @param[in] clk_src Clock source available to modules, in soc_module_clk_t
+ * @param[in] enable  Enable / Disable the clock gate
+ *
+ * @note !!! WARNING !!!
+ *       There's no reference counter to protect the clock source status, the caller should use the interface
+ *       with CAUTION to disable the clock source to avoid damaging other peripherals that are dependent on
+ *       the clock source.
+ *
+ * @return
+ *      - ESP_OK               Success
+ *      - ESP_ERR_INVALID_ARG  Parameter error
+ */
+esp_err_t esp_clk_tree_enable_src(soc_module_clk_t clk_src, bool enable);
+
 #ifdef __cplusplus
 }
 #endif