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fix(esp_eth): fixed ESP32P4 EMAC REF RMII CLK output mode

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fixed units returned and used by periph_rtc_mpll_freq_set function
This commit is contained in:
Ondrej Kosta
2025-04-01 08:34:45 +02:00
parent 07f4ff8c00
commit 9f4acf245a
14 changed files with 282 additions and 36 deletions
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components/esp_eth/src/mac/esp_eth_mac_esp.c
+6 -3
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2019-2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2019-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -22,6 +22,7 @@
#endif // CONFIG_IDF_TARGET_ESP32
#include "hal/clk_tree_ll.h"
#include "esp_private/esp_clk.h"
#include "esp_private/esp_clk_tree_common.h"
#include "freertos/FreeRTOS.h"
#include "freertos/task.h"
#include "freertos/semphr.h"
@@ -395,11 +396,13 @@ static esp_err_t emac_config_pll_clock(emac_esp32_t *emac)
}
// Set divider of MPLL clock
if (real_freq > RMII_CLK_HZ) {
int32_t div = real_freq / RMII_CLK_HZ - 1;
uint32_t div = real_freq / RMII_CLK_HZ;
clk_ll_pll_f50m_set_divider(div);
// compute real RMII CLK frequency
real_freq /= div + 1;
real_freq /= div;
}
// Enable 50MHz MPLL derived clock
esp_clk_tree_enable_src(SOC_MOD_CLK_PLL_F50M, true);
#endif
// If the difference of real RMII CLK frequency is not within 50 ppm, i.e. 2500 Hz, the (A/M)PLL is unusable
ESP_RETURN_ON_FALSE(abs((int)real_freq - (int)expt_freq) <= 2500,