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Merge branch 'fix/fix_p4_lp_adc_unavailable_in_sleep_v6.0' into 'release/v6.0'

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feat(esp_hw_support): support ESP_SLEEP_USE_ADC_TSEN_MONITOR_MODE for esp32p4 (v6.0)

See merge request espressif/esp-idf!45197
This commit is contained in:
Jiang Jiang Jian
2026-01-29 14:11:53 +08:00
parent 9d317f2cb8 a0e94d7f24
commit 9ed8ae514a
3 changed files with 12 additions and 9 deletions
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components/soc/esp32p4/include/soc/clk_tree_defs.h
+4 -4
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -284,16 +284,16 @@ typedef enum {
/**
* @brief Array initializer for all supported clock sources of LP_UART
*/
#define SOC_LP_UART_CLKS {SOC_MOD_CLK_RTC_FAST, SOC_MOD_CLK_XTAL_D2}
#define SOC_LP_UART_CLKS {SOC_MOD_CLK_RC_FAST, SOC_MOD_CLK_XTAL_D2}
/**
* @brief Type of LP_UART clock source
*/
typedef enum {
LP_UART_SCLK_LP_FAST = SOC_MOD_CLK_RTC_FAST, /*!< LP_UART source clock is LP(RTC)_FAST */
LP_UART_SCLK_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< LP_UART source clock is FOSC */
LP_UART_SCLK_XTAL_D2 = SOC_MOD_CLK_XTAL_D2, /*!< LP_UART source clock is XTAL_D2 */
// LP_UART_SCLK_LP_PLL = SOC_MOD_CLK_LP_PLL, /*!< LP_UART source clock is LP_PLL (8M PLL) */ TODO: IDF-9581
LP_UART_SCLK_DEFAULT = SOC_MOD_CLK_RTC_FAST, /*!< LP_UART source clock default choice is LP(RTC)_FAST */
LP_UART_SCLK_DEFAULT = SOC_MOD_CLK_RC_FAST, /*!< LP_UART source clock default choice is FOSC */
} soc_periph_lp_uart_clk_src_t;
//////////////////////////////////////////////////MCPWM/////////////////////////////////////////////////////////////////